Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26321

1

T1

21

T2

35

T3

17

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22897

1

T1

21

T2

35

T3

17

auto[ADC_CTRL_FILTER_COND_OUT]

3424

1

T10

13

T15

7

T55

15

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20801

1

T1

21

T3

17

T5

14

auto[1]

5520

1

T2

35

T6

27

T7

8

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22273

1

T1

16

T2

35

T3

11

auto[1]

4048

1

T1

5

T3

6

T7

7

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	199	1			T55	26		T17	26		T110	14
values[0]	21	1			T259	10		T260	11		-	-
values[1]	572	1			T156	11		T109	17		T208	6
values[2]	566	1			T1	1		T15	3		T18	12
values[3]	640	1			T10	13		T155	21		T51	13
values[4]	588	1			T1	9		T47	5		T16	2
values[5]	822	1			T12	15		T15	1		T156	5
values[6]	805	1			T12	8		T55	15		T155	22
values[7]	915	1			T8	2		T48	6		T115	1
values[8]	2813	1			T2	35		T6	27		T7	8
values[9]	1060	1			T3	17		T15	6		T16	7
minimum	17320	1			T1	11		T5	14		T8	22

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	638	1			T156	11		T109	17		T159	1
values[1]	561	1			T1	1		T15	3		T18	12
values[2]	584	1			T10	13		T47	5		T16	2
values[3]	791	1			T1	9		T166	1		T168	10
values[4]	727	1			T12	23		T15	1		T156	5
values[5]	794	1			T55	15		T155	22		T162	1
values[6]	3010	1			T2	35		T6	27		T7	8
values[7]	634	1			T11	14		T16	7		T158	2
values[8]	982	1			T3	17		T15	6		T17	26
values[9]	154	1			T55	26		T160	13		T187	17
minimum	17446	1			T1	11		T5	14		T8	22

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22289

1

T1

17

T2

3

T3

7

auto[1]

4032

1

T1

4

T2

32

T3

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T176	19		T164	8		T252	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T156	1		T109	9		T159	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T1	1		T18	1		T155	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T15	2		T168	15		T53	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T47	4		T159	1		T224	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T10	1		T16	1		T172	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T1	5		T166	1		T168	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T112	1		T52	10		T170	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T12	13		T15	1		T156	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T109	8		T254	1		T176	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T155	10		T170	9		T54	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T55	8		T162	1		T125	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1562	1			T2	35		T6	27		T7	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T48	5		T217	13		T173	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T11	14		T16	2		T158	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T168	10		T109	14		T171	24
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	296	1			T3	11		T15	2		T158	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T15	3		T17	11		T157	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T55	16		T160	1		T187	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T273	1		T288	1		T320	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17214	1			T1	10		T5	14		T8	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T208	3		T180	1		T182	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T176	20		T164	13		T107	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T156	10		T109	8		T164	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T18	11		T155	10		T51	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T15	1		T53	6		T164	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T47	1		T159	14		T173	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T10	12		T16	1		T172	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T1	4		T49	5		T203	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T112	9		T52	7		T170	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T12	10		T156	4		T214	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T109	14		T254	6		T176	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T155	12		T170	8		T54	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T55	7		T125	11		T129	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	989	1			T7	7		T9	27		T57	20
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T48	1		T217	15		T173	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T16	5		T224	9		T257	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T109	12		T253	12		T163	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T3	6		T110	12		T50	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T15	1		T17	15		T157	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T55	10		T160	12		T187	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T273	11		T288	12		T320	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T1	1		T8	2		T10	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T208	3		T182	10		T321	13

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T55	16		T110	12		T187	16
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T17	11		T273	1		T322	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T259	10		T260	3		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T176	5		T252	14		T189	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T156	1		T109	9		T208	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T1	1		T18	1		T176	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T15	2		T168	15		T159	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T155	11		T51	6		T159	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T10	1		T161	14		T209	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T1	5		T47	4		T166	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T16	1		T52	10		T172	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T12	8		T15	1		T156	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T109	8		T112	1		T170	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T12	5		T155	10		T170	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T55	8		T162	1		T36	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T8	2		T115	1		T171	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T48	5		T217	13		T173	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1521	1			T2	35		T6	27		T7	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T168	10		T109	14		T171	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T3	11		T15	2		T16	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	316	1			T15	3		T157	2		T171	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17181	1			T1	10		T5	14		T8	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T55	10		T110	2		T187	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T17	15		T273	11		T322	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T260	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T176	9		T256	14		T102	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T156	10		T109	8		T208	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T18	11		T176	11		T164	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T15	1		T53	6		T164	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T155	10		T51	7		T159	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T10	12		T186	13		T20	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T1	4		T47	1		T276	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T16	1		T52	7		T172	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T12	7		T156	4		T49	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T109	14		T112	9		T170	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T12	3		T155	12		T170	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T55	7		T36	4		T274	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T214	2		T262	9		T218	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T48	1		T217	15		T173	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	921	1			T7	7		T9	27		T57	20
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T109	12		T253	12		T163	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T3	6		T16	5		T110	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T15	1		T157	13		T159	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T1	1		T8	2		T10	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T176	22		T164	14		T252	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T156	11		T109	9		T159	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T1	1		T18	12		T155	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T15	3		T168	1		T53	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T47	4		T159	15		T224	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T10	13		T16	2		T172	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T1	5		T166	1		T168	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T112	10		T52	13		T170	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T12	14		T15	1		T156	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T109	15		T254	7		T176	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T155	13		T170	9		T54	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T55	8		T162	1		T125	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1325	1			T2	3		T6	2		T7	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T48	4		T217	16		T173	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T11	1		T16	6		T158	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T168	1		T109	13		T171	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T3	7		T15	2		T158	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T15	3		T17	16		T157	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T55	11		T160	13		T187	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T273	12		T288	13		T320	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17350	1			T1	11		T5	14		T8	22
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T208	4		T180	1		T182	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T176	17		T164	7		T252	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T109	8		T164	3		T257	19
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T155	10		T51	2		T161	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T168	14		T53	3		T161	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T47	1		T224	5		T263	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T172	4		T253	4		T20	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T1	4		T168	9		T49	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T52	4		T170	12		T275	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T12	9		T264	11		T265	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T109	7		T176	12		T275	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T155	9		T170	8		T54	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T55	7		T125	12		T313	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1226	1			T2	32		T6	25		T167	30
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T48	2		T217	12		T173	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T11	13		T16	1		T224	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T168	9		T109	13		T171	22
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T3	10		T110	23		T50	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T15	1		T17	10		T163	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T55	15		T187	15		T267	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T323	15		T324	9		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T259	9		T196	2		T325	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T208	2		T326	13		T327	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T55	11		T110	3		T187	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T17	16		T273	12		T322	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T259	1		T260	9		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T176	10		T252	1		T189	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T156	11		T109	9		T208	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T1	1		T18	12		T176	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T15	3		T168	1		T159	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T155	11		T51	11		T159	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T10	13		T161	2		T209	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T1	5		T47	4		T166	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T16	2		T52	13		T172	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T12	9		T15	1		T156	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T109	15		T112	10		T170	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T12	5		T155	13		T170	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T55	8		T162	1		T36	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T8	2		T115	1		T171	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	335	1			T48	4		T217	16		T173	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1253	1			T2	3		T6	2		T7	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T168	1		T109	13		T171	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T3	7		T15	2		T16	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T15	3		T157	15		T171	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17320	1			T1	11		T5	14		T8	22
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T55	15		T110	11		T187	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T17	10		T322	6		T328	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T259	9		T260	2		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T176	4		T252	13		T256	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T109	8		T208	2		T164	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T176	13		T164	7		T36	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T168	14		T53	3		T265	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T155	10		T51	2		T224	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T161	12		T209	15		T20	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T1	4		T47	1		T168	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T52	4		T172	4		T253	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T12	6		T49	3		T270	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T109	7		T170	12		T176	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T12	3		T155	9		T170	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T55	7		T36	3		T86	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T171	6		T262	10		T218	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T48	2		T217	12		T173	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1189	1			T2	32		T6	25		T11	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T168	9		T109	13		T171	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T3	10		T16	1		T110	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T15	1		T171	12		T270	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22289

1

T1

17

T2

3

T3

7

auto[1]

auto[0]

4032

1

T1

4

T2

32

T3

10