Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26321

1

T1

21

T2

35

T3

17

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23094

1

T1

12

T2

35

T3

17

auto[ADC_CTRL_FILTER_COND_OUT]

3227

1

T1

9

T11

14

T12

8

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20117

1

T1

20

T5

14

T8

22

auto[1]

6204

1

T1

1

T2

35

T3

17

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22273

1

T1

16

T2

35

T3

11

auto[1]

4048

1

T1

5

T3

6

T7

7

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	229	1			T156	11		T53	17		T162	1
values[0]	14	1			T271	14		-	-		-	-
values[1]	850	1			T55	15		T157	12		T158	1
values[2]	754	1			T16	2		T155	43		T48	6
values[3]	673	1			T8	2		T158	1		T112	10
values[4]	818	1			T12	8		T55	26		T16	7
values[5]	2896	1			T2	35		T6	27		T7	8
values[6]	592	1			T3	17		T15	2		T18	12
values[7]	626	1			T1	1		T168	10		T159	11
values[8]	595	1			T1	9		T10	13		T15	3
values[9]	954	1			T15	5		T168	10		T49	13
minimum	17320	1			T1	11		T5	14		T8	22

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	795	1			T55	15		T157	12		T155	21
values[1]	764	1			T16	2		T155	22		T109	22
values[2]	793	1			T16	7		T158	1		T48	6
values[3]	2932	1			T2	35		T6	27		T7	8
values[4]	657	1			T11	14		T47	5		T17	26
values[5]	544	1			T3	17		T15	2		T18	12
values[6]	652	1			T1	10		T168	10		T159	10
values[7]	573	1			T10	13		T15	3		T156	5
values[8]	904	1			T15	5		T156	11		T168	10
values[9]	163	1			T253	25		T170	17		T214	3
minimum	17544	1			T1	11		T5	14		T8	22

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22289

1

T1

17

T2

3

T3

7

auto[1]

4032

1

T1

4

T2

32

T3

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T55	8		T157	1		T155	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T166	1		T110	13		T172	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T16	1		T112	1		T217	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T155	10		T109	8		T160	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T16	2		T158	1		T48	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T52	10		T173	1		T262	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1619	1			T2	35		T6	27		T7	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T12	5		T55	16		T198	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T47	4		T17	11		T157	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T11	14		T208	3		T163	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T3	11		T109	14		T162	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T15	2		T18	1		T158	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T1	1		T159	1		T270	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T1	5		T168	10		T176	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T10	1		T15	2		T156	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T51	6		T162	1		T188	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T15	1		T156	1		T110	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T15	3		T168	10		T49	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T253	13		T170	9		T214	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T21	4		T329	5		T67	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17252	1			T1	10		T5	14		T8	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T158	1		T256	12		T313	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T55	7		T157	11		T155	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T110	10		T172	8		T253	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T16	1		T112	9		T217	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T155	12		T109	14		T160	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T16	5		T48	1		T254	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T52	7		T173	10		T262	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	988	1			T7	7		T9	27		T12	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T12	3		T55	10		T164	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T47	1		T17	15		T157	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T208	3		T163	14		T257	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T3	6		T109	12		T163	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T18	11		T20	3		T276	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T159	9		T273	11		T36	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T1	4		T176	11		T179	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T10	12		T15	1		T156	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T51	7		T188	2		T182	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T156	10		T110	2		T159	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T15	1		T49	5		T173	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T253	12		T170	8		T214	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T21	3		T67	1		T330	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T1	1		T8	2		T10	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T256	15		T313	10		T322	6

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T156	1		T53	11		T179	14
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T162	1		T21	4		T129	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T271	7		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T55	8		T157	1		T176	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T158	1		T166	1		T110	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T16	1		T155	11		T48	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T155	10		T109	8		T160	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T8	2		T158	1		T112	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T52	10		T173	1		T270	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T16	2		T161	4		T170	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T12	5		T55	16		T198	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1610	1			T2	35		T6	27		T7	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T11	14		T257	14		T31	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T3	11		T47	4		T109	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T15	2		T18	1		T158	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T1	1		T159	1		T270	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T168	10		T159	1		T179	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T10	1		T15	2		T156	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T1	5		T188	1		T174	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T15	1		T110	12		T115	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T15	3		T168	10		T49	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17181	1			T1	10		T5	14		T8	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T156	10		T53	6		T179	17
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T21	3		T129	1		T331	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T271	7		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T55	7		T157	11		T176	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T110	10		T172	8		T275	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T16	1		T155	10		T48	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T155	12		T109	14		T160	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T112	9		T187	1		T129	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T52	7		T173	10		T254	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T16	5		T170	2		T203	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T12	3		T55	10		T164	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1033	1			T7	7		T9	27		T12	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T257	10		T118	2		T128	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T3	6		T47	1		T109	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T18	11		T208	3		T163	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T159	9		T163	6		T176	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T179	3		T258	6		T238	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T10	12		T15	1		T156	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T1	4		T188	2		T176	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T110	2		T159	14		T253	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T15	1		T49	5		T51	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T1	1		T8	2		T10	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T55	8		T157	12		T155	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T166	1		T110	11		T172	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T16	2		T112	10		T217	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T155	13		T109	15		T160	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T16	6		T158	1		T48	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T52	13		T173	11		T262	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1336	1			T2	3		T6	2		T7	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T12	5		T55	11		T198	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T47	4		T17	16		T157	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T11	1		T208	4		T163	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T3	7		T109	13		T162	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T15	2		T18	12		T158	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T1	1		T159	10		T270	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T1	5		T168	1		T176	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T10	13		T15	3		T156	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T51	11		T162	1		T188	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T15	1		T156	11		T110	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T15	3		T168	1		T49	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T253	13		T170	9		T214	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T21	6		T329	1		T67	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17393	1			T1	11		T5	14		T8	22
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T158	1		T256	16		T313	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T55	7		T155	10		T176	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T110	12		T172	4		T253	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T217	12		T179	17		T263	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T155	9		T109	7		T270	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T16	1		T48	2		T224	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T52	4		T262	10		T35	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1271	1			T2	32		T6	25		T12	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T12	3		T55	15		T198	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T47	1		T17	10		T109	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T11	13		T208	2		T163	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T3	10		T109	13		T209	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T171	12		T20	3		T89	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T270	7		T36	3		T85	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T1	4		T168	9		T176	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T168	14		T50	1		T161	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T51	2		T278	3		T279	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T110	11		T53	3		T170	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T15	1		T168	9		T49	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T253	12		T170	8		T179	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T21	1		T329	4		T67	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T89	2		T285	14		T332	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T256	11		T313	11		T322	6

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T156	11		T53	14		T179	18
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T162	1		T21	6		T129	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T271	8		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T55	8		T157	12		T176	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T158	1		T166	1		T110	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T16	2		T155	11		T48	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T155	13		T109	15		T160	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T8	2		T158	1		T112	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T52	13		T173	11		T270	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T16	6		T161	1		T170	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T12	5		T55	11		T198	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1374	1			T2	3		T6	2		T7	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T11	1		T257	11		T31	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T3	7		T47	4		T109	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T15	2		T18	12		T158	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T1	1		T159	10		T270	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T168	1		T159	1		T179	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T10	13		T15	3		T156	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T1	5		T188	3		T174	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T15	1		T110	3		T115	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T15	3		T168	1		T49	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17320	1			T1	11		T5	14		T8	22
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T53	3		T179	13		T333	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T21	1		T294	2		T329	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T271	6		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T55	7		T176	4		T265	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T110	12		T172	4		T265	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T155	10		T48	2		T217	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T155	9		T109	7		T253	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T224	5		T161	9		T187	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T52	4		T270	11		T262	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T16	1		T161	3		T170	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T12	3		T55	15		T198	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1269	1			T2	32		T6	25		T12	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T11	13		T257	13		T334	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T3	10		T47	1		T109	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T171	12		T208	2		T163	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T270	7		T163	6		T176	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T168	9		T179	10		T238	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T168	14		T50	1		T161	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T1	4		T176	13		T278	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T110	11		T253	12		T170	20
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T15	1		T168	9		T49	3

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22289

1

T1

17

T2

3

T3

7

auto[1]

auto[0]

4032

1

T1

4

T2

32

T3

10