Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26321

1

T1

21

T2

35

T3

17

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20494

1

T1

21

T5

14

T8

22

auto[ADC_CTRL_FILTER_COND_OUT]

5827

1

T2

35

T3

17

T6

27

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20553

1

T1

12

T3

17

T5

14

auto[1]

5768

1

T1

9

T2

35

T6

27

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22273

1

T1

16

T2

35

T3

11

auto[1]

4048

1

T1

5

T3

6

T7

7

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	261	1			T15	3		T55	26		T155	21
values[0]	19	1			T15	2		T228	13		T335	4
values[1]	672	1			T1	9		T12	8		T16	9
values[2]	706	1			T55	15		T157	12		T171	13
values[3]	831	1			T18	12		T110	14		T115	1
values[4]	718	1			T1	1		T11	14		T12	15
values[5]	694	1			T10	13		T47	5		T17	26
values[6]	887	1			T3	17		T158	1		T155	22
values[7]	564	1			T8	2		T15	5		T109	22
values[8]	619	1			T168	10		T109	26		T159	10
values[9]	3030	1			T2	35		T6	27		T7	8
minimum	17320	1			T1	11		T5	14		T8	22

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	690	1			T15	2		T55	15		T16	9
values[1]	2868	1			T2	35		T6	27		T7	8
values[2]	911	1			T11	14		T18	12		T109	17
values[3]	693	1			T1	1		T12	15		T47	5
values[4]	684	1			T10	13		T17	26		T158	1
values[5]	787	1			T3	17		T158	1		T155	22
values[6]	657	1			T8	2		T15	5		T109	26
values[7]	578	1			T168	10		T51	13		T159	10
values[8]	797	1			T15	3		T55	26		T158	1
values[9]	164	1			T336	14		T24	3		T337	19
minimum	17492	1			T1	20		T5	14		T8	22

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22289

1

T1

17

T2

3

T3

7

auto[1]

4032

1

T1

4

T2

32

T3

10

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T156	1		T171	13		T264	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T15	2		T55	8		T16	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T170	9		T179	18		T338	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1567	1			T2	35		T6	27		T7	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T18	1		T254	1		T179	25
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T11	14		T109	9		T110	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T1	1		T157	1		T159	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T12	8		T47	4		T156	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T158	1		T48	5		T49	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T10	1		T17	11		T166	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T170	6		T164	4		T262	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T3	11		T158	1		T155	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T15	4		T109	14		T115	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T8	2		T112	1		T214	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T168	10		T51	6		T53	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T159	1		T164	8		T265	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T15	2		T55	16		T158	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T155	11		T168	15		T162	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T287	8		T289	2		T339	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T336	1		T24	2		T337	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17238	1			T1	15		T5	14		T8	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T12	5		T278	9		T228	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T156	10		T264	13		T125	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T55	7		T16	6		T170	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T170	8		T179	13		T275	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	977	1			T7	7		T9	27		T57	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T18	11		T254	15		T179	20
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T109	8		T110	2		T208	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T157	2		T172	8		T253	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T12	7		T47	1		T156	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T48	1		T49	5		T159	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T10	12		T17	15		T316	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T170	2		T164	9		T262	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T3	6		T155	12		T109	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T15	1		T109	12		T224	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T112	9		T214	2		T305	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T51	7		T53	6		T254	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T159	9		T164	13		T35	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T15	1		T55	10		T52	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T155	10		T186	21		T187	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T287	9		T289	1		T339	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T336	13		T24	1		T337	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T1	5		T8	2		T10	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T12	3		T278	6		T228	12

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T15	2		T55	16		T118	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T155	11		T168	15		T162	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T15	2		T228	1		T335	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T1	5		T156	1		T50	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T12	5		T16	3		T168	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T171	13		T264	12		T179	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T55	8		T157	1		T209	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T18	1		T170	9		T254	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T110	12		T115	1		T162	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T1	1		T157	1		T159	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T11	14		T12	8		T156	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T158	1		T48	5		T49	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T10	1		T47	4		T17	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T159	1		T224	6		T170	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T3	11		T158	1		T155	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T15	4		T115	1		T161	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T8	2		T109	8		T112	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T168	10		T109	14		T224	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T159	1		T214	1		T164	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T158	1		T51	6		T52	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1636	1			T2	35		T6	27		T7	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17181	1			T1	10		T5	14		T8	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T15	1		T55	10		T118	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T155	10		T336	13		T24	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T228	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T1	4		T156	10		T50	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T12	3		T16	6		T170	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T264	13		T179	13		T128	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T55	7		T157	11		T54	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T18	11		T170	8		T254	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T110	2		T176	21		T263	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T157	2		T172	8		T253	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T12	7		T156	4		T109	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T48	1		T49	5		T214	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T10	12		T47	1		T17	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T159	14		T170	2		T164	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T3	6		T155	12		T110	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T15	1		T164	9		T85	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T109	14		T112	9		T305	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T109	12		T224	9		T53	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T159	9		T214	2		T164	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T51	7		T52	7		T160	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1015	1			T7	7		T9	27		T57	20
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T1	1		T8	2		T10	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T156	11		T171	1		T264	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T15	2		T55	8		T16	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T170	9		T179	14		T338	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1311	1			T2	3		T6	2		T7	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T18	12		T254	16		T179	22
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T11	1		T109	9		T110	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T1	1		T157	3		T159	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T12	9		T47	4		T156	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T158	1		T48	4		T49	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T10	13		T17	16		T166	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T170	3		T164	10		T262	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T3	7		T158	1		T155	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T15	4		T109	13		T115	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T8	2		T112	10		T214	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T168	1		T51	11		T53	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T159	10		T164	14		T265	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T15	3		T55	11		T158	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T155	11		T168	1		T162	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T287	10		T289	2		T339	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T336	14		T24	2		T337	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17354	1			T1	16		T5	14		T8	22
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T12	5		T278	12		T228	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T171	12		T264	11		T252	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T55	7		T16	1		T168	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T170	8		T179	17		T275	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1233	1			T2	32		T6	25		T167	30
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T179	23		T86	5		T218	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T11	13		T109	8		T110	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T172	4		T253	16		T198	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T12	6		T47	1		T161	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T48	2		T49	3		T171	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T17	10		T171	6		T277	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T170	5		T164	3		T262	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T3	10		T155	9		T109	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T15	1		T109	13		T224	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T305	9		T275	11		T36	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T168	9		T51	2		T53	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T164	7		T265	9		T35	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T55	15		T52	4		T270	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T155	10		T168	14		T187	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T287	7		T289	1		T339	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T24	1		T337	10		T340	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T1	4		T50	1		T161	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T12	3		T278	3		T341	19

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T15	3		T55	11		T118	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T155	11		T168	1		T162	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T15	2		T228	13		T335	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T1	5		T156	11		T50	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T12	5		T16	8		T168	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T171	1		T264	14		T179	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T55	8		T157	12		T209	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	290	1			T18	12		T170	9		T254	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T110	3		T115	1		T162	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T1	1		T157	3		T159	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T11	1		T12	9		T156	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T158	1		T48	4		T49	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T10	13		T47	4		T17	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T159	15		T224	1		T170	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T3	7		T158	1		T155	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T15	4		T115	1		T161	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T8	2		T109	15		T112	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T168	1		T109	13		T224	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T159	10		T214	3		T164	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T158	1		T51	11		T52	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1368	1			T2	3		T6	2		T7	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17320	1			T1	11		T5	14		T8	22
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T55	15		T205	9		T287	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T155	10		T168	14		T266	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T335	3		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T1	4		T50	1		T161	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T12	3		T16	1		T168	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T171	12		T264	11		T179	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T55	7		T209	15		T54	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T170	8		T179	23		T275	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T110	11		T176	16		T263	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T172	4		T253	16		T256	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T11	13		T12	6		T109	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T48	2		T49	3		T171	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T47	1		T17	10		T161	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T224	5		T170	5		T164	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T3	10		T155	9		T110	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T15	1		T161	14		T85	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T109	7		T305	9		T275	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T168	9		T109	13		T224	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T164	7		T265	9		T275	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T51	2		T52	4		T270	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1283	1			T2	32		T6	25		T167	30

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22289

1

T1

17

T2

3

T3

7

auto[1]

auto[0]

4032

1

T1

4

T2

32

T3

10