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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.72 99.04 96.63 100.00 100.00 98.76 98.33 91.29


Total test records in report: 912
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T75 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.2069074503 Mar 10 12:22:26 PM PDT 24 Mar 10 12:22:29 PM PDT 24 451448180 ps
T65 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.36743155 Mar 10 12:27:07 PM PDT 24 Mar 10 12:27:19 PM PDT 24 8570323906 ps
T66 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.2340619345 Mar 10 12:23:39 PM PDT 24 Mar 10 12:23:52 PM PDT 24 4767250936 ps
T136 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.2560139979 Mar 10 12:24:12 PM PDT 24 Mar 10 12:24:15 PM PDT 24 460130805 ps
T29 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.1522808107 Mar 10 12:20:59 PM PDT 24 Mar 10 12:21:01 PM PDT 24 451326313 ps
T69 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.3242492483 Mar 10 12:18:22 PM PDT 24 Mar 10 12:18:35 PM PDT 24 8352688358 ps
T63 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.3386379667 Mar 10 12:20:17 PM PDT 24 Mar 10 12:21:20 PM PDT 24 30373001999 ps
T147 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.1017155381 Mar 10 12:18:17 PM PDT 24 Mar 10 12:18:18 PM PDT 24 577018205 ps
T39 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.3584533784 Mar 10 12:33:55 PM PDT 24 Mar 10 12:33:57 PM PDT 24 520499285 ps
T40 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.3548148879 Mar 10 12:23:03 PM PDT 24 Mar 10 12:23:06 PM PDT 24 424561175 ps
T792 /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.1409654253 Mar 10 12:18:22 PM PDT 24 Mar 10 12:18:23 PM PDT 24 338719464 ps
T793 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.156726445 Mar 10 12:20:08 PM PDT 24 Mar 10 12:20:08 PM PDT 24 306058330 ps
T137 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.2792861048 Mar 10 12:24:28 PM PDT 24 Mar 10 12:24:29 PM PDT 24 477843523 ps
T64 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.3369767764 Mar 10 12:19:16 PM PDT 24 Mar 10 12:21:07 PM PDT 24 52136908681 ps
T95 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.3613995437 Mar 10 12:22:19 PM PDT 24 Mar 10 12:22:21 PM PDT 24 399671312 ps
T70 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.1893305251 Mar 10 12:18:18 PM PDT 24 Mar 10 12:18:25 PM PDT 24 8370725489 ps
T76 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.3663748024 Mar 10 12:21:32 PM PDT 24 Mar 10 12:21:35 PM PDT 24 550294564 ps
T77 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.1319701687 Mar 10 12:23:39 PM PDT 24 Mar 10 12:23:43 PM PDT 24 598108045 ps
T794 /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.4185514767 Mar 10 12:27:08 PM PDT 24 Mar 10 12:27:09 PM PDT 24 513671383 ps
T96 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.1052647398 Mar 10 12:18:36 PM PDT 24 Mar 10 12:18:38 PM PDT 24 357308215 ps
T148 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.2998170086 Mar 10 12:24:24 PM PDT 24 Mar 10 12:24:31 PM PDT 24 2662827615 ps
T795 /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.2025705821 Mar 10 12:19:14 PM PDT 24 Mar 10 12:19:16 PM PDT 24 373070408 ps
T138 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.406070695 Mar 10 12:20:03 PM PDT 24 Mar 10 12:20:36 PM PDT 24 33284909239 ps
T97 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.2545626265 Mar 10 12:20:30 PM PDT 24 Mar 10 12:20:32 PM PDT 24 477273917 ps
T796 /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.2967063552 Mar 10 12:23:57 PM PDT 24 Mar 10 12:23:59 PM PDT 24 510422630 ps
T797 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.179809709 Mar 10 12:23:59 PM PDT 24 Mar 10 12:24:00 PM PDT 24 443202951 ps
T149 /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.3031576249 Mar 10 12:23:22 PM PDT 24 Mar 10 12:23:27 PM PDT 24 4176270602 ps
T71 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.2867676106 Mar 10 12:27:37 PM PDT 24 Mar 10 12:27:59 PM PDT 24 7990114165 ps
T139 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.2588103641 Mar 10 12:23:02 PM PDT 24 Mar 10 12:23:04 PM PDT 24 425741130 ps
T798 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.3260533654 Mar 10 12:20:03 PM PDT 24 Mar 10 12:20:04 PM PDT 24 481827259 ps
T799 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.3560982748 Mar 10 12:23:55 PM PDT 24 Mar 10 12:23:58 PM PDT 24 587150491 ps
T79 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.1291313795 Mar 10 12:21:33 PM PDT 24 Mar 10 12:21:36 PM PDT 24 582853632 ps
T800 /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.235163203 Mar 10 12:24:24 PM PDT 24 Mar 10 12:24:26 PM PDT 24 403310753 ps
T801 /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.1957373605 Mar 10 12:22:57 PM PDT 24 Mar 10 12:22:58 PM PDT 24 552259045 ps
T368 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.4037441359 Mar 10 12:18:03 PM PDT 24 Mar 10 12:18:25 PM PDT 24 8177314848 ps
T802 /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.2358215639 Mar 10 12:22:36 PM PDT 24 Mar 10 12:22:38 PM PDT 24 456889880 ps
T803 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.1573438790 Mar 10 12:26:49 PM PDT 24 Mar 10 12:26:50 PM PDT 24 536987560 ps
T804 /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.3062240572 Mar 10 12:23:18 PM PDT 24 Mar 10 12:23:19 PM PDT 24 318626895 ps
T805 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.4048352055 Mar 10 12:33:53 PM PDT 24 Mar 10 12:33:56 PM PDT 24 487252418 ps
T806 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.2577215823 Mar 10 12:19:52 PM PDT 24 Mar 10 12:19:53 PM PDT 24 555423072 ps
T807 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.434086553 Mar 10 12:23:59 PM PDT 24 Mar 10 12:24:00 PM PDT 24 436958259 ps
T808 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.2220433531 Mar 10 12:20:03 PM PDT 24 Mar 10 12:20:04 PM PDT 24 526866153 ps
T150 /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.587119345 Mar 10 12:23:01 PM PDT 24 Mar 10 12:23:04 PM PDT 24 2097814962 ps
T140 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.798185815 Mar 10 12:33:42 PM PDT 24 Mar 10 12:33:49 PM PDT 24 1131385984 ps
T809 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.1049717053 Mar 10 12:27:45 PM PDT 24 Mar 10 12:27:47 PM PDT 24 464134279 ps
T810 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.1317432539 Mar 10 12:24:10 PM PDT 24 Mar 10 12:24:28 PM PDT 24 9137563821 ps
T811 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.530399911 Mar 10 12:18:18 PM PDT 24 Mar 10 12:18:19 PM PDT 24 845561634 ps
T812 /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.1639384711 Mar 10 12:23:57 PM PDT 24 Mar 10 12:23:59 PM PDT 24 328548042 ps
T151 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.1031348892 Mar 10 12:21:39 PM PDT 24 Mar 10 12:21:40 PM PDT 24 449654096 ps
T813 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.2155496809 Mar 10 12:23:01 PM PDT 24 Mar 10 12:23:05 PM PDT 24 1153147307 ps
T141 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.993943108 Mar 10 12:20:50 PM PDT 24 Mar 10 12:20:54 PM PDT 24 828609352 ps
T814 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.1544204665 Mar 10 12:23:43 PM PDT 24 Mar 10 12:23:49 PM PDT 24 4451022793 ps
T815 /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.1557364942 Mar 10 12:22:53 PM PDT 24 Mar 10 12:22:54 PM PDT 24 511374429 ps
T816 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.2980708564 Mar 10 12:26:49 PM PDT 24 Mar 10 12:26:51 PM PDT 24 635585175 ps
T817 /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.3572442826 Mar 10 12:24:01 PM PDT 24 Mar 10 12:24:02 PM PDT 24 397151576 ps
T818 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.205274776 Mar 10 12:23:09 PM PDT 24 Mar 10 12:23:12 PM PDT 24 508071596 ps
T819 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.3937986164 Mar 10 12:20:06 PM PDT 24 Mar 10 12:20:07 PM PDT 24 439954960 ps
T366 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.1980773254 Mar 10 12:20:42 PM PDT 24 Mar 10 12:20:54 PM PDT 24 4075906009 ps
T820 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.1919706359 Mar 10 12:18:20 PM PDT 24 Mar 10 12:18:21 PM PDT 24 381807872 ps
T152 /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.2740887224 Mar 10 12:24:11 PM PDT 24 Mar 10 12:24:21 PM PDT 24 2185043782 ps
T78 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.1418252547 Mar 10 12:24:24 PM PDT 24 Mar 10 12:24:26 PM PDT 24 468000161 ps
T142 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.815802674 Mar 10 12:18:20 PM PDT 24 Mar 10 12:18:22 PM PDT 24 363397074 ps
T821 /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.640642048 Mar 10 12:22:45 PM PDT 24 Mar 10 12:22:48 PM PDT 24 422685579 ps
T822 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.3416965685 Mar 10 12:24:31 PM PDT 24 Mar 10 12:24:33 PM PDT 24 798213983 ps
T823 /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.4143208788 Mar 10 12:21:22 PM PDT 24 Mar 10 12:21:27 PM PDT 24 4653704224 ps
T824 /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.1607083833 Mar 10 12:27:01 PM PDT 24 Mar 10 12:27:04 PM PDT 24 2584405964 ps
T825 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.1793507466 Mar 10 12:20:41 PM PDT 24 Mar 10 12:20:45 PM PDT 24 2495084349 ps
T826 /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.3495836402 Mar 10 12:24:32 PM PDT 24 Mar 10 12:24:37 PM PDT 24 2417134057 ps
T827 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.3933787553 Mar 10 12:18:18 PM PDT 24 Mar 10 12:18:20 PM PDT 24 576270383 ps
T143 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.2281613327 Mar 10 12:20:45 PM PDT 24 Mar 10 12:20:48 PM PDT 24 467585843 ps
T828 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.1300193562 Mar 10 12:20:03 PM PDT 24 Mar 10 12:20:19 PM PDT 24 4566415157 ps
T829 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.2766803263 Mar 10 12:22:53 PM PDT 24 Mar 10 12:22:57 PM PDT 24 376846627 ps
T830 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.3249752269 Mar 10 12:24:10 PM PDT 24 Mar 10 12:24:13 PM PDT 24 367202748 ps
T831 /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.4058567912 Mar 10 12:24:45 PM PDT 24 Mar 10 12:24:46 PM PDT 24 375512940 ps
T832 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.2774183151 Mar 10 12:20:42 PM PDT 24 Mar 10 12:21:04 PM PDT 24 8225868975 ps
T833 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.1830190316 Mar 10 12:23:43 PM PDT 24 Mar 10 12:23:48 PM PDT 24 511946908 ps
T80 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.2717346437 Mar 10 12:19:07 PM PDT 24 Mar 10 12:19:18 PM PDT 24 4330808829 ps
T367 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.1057730496 Mar 10 12:24:11 PM PDT 24 Mar 10 12:24:18 PM PDT 24 4418056367 ps
T834 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.38296651 Mar 10 12:24:11 PM PDT 24 Mar 10 12:24:12 PM PDT 24 586502019 ps
T835 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.2554520416 Mar 10 12:24:24 PM PDT 24 Mar 10 12:24:27 PM PDT 24 343799576 ps
T836 /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.107977338 Mar 10 12:19:52 PM PDT 24 Mar 10 12:19:57 PM PDT 24 2131404536 ps
T837 /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.3673220117 Mar 10 12:27:07 PM PDT 24 Mar 10 12:27:10 PM PDT 24 2333911395 ps
T838 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.1869204741 Mar 10 12:21:49 PM PDT 24 Mar 10 12:21:51 PM PDT 24 398393774 ps
T839 /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.2127797381 Mar 10 12:18:34 PM PDT 24 Mar 10 12:18:36 PM PDT 24 497216758 ps
T840 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.3939575880 Mar 10 12:20:39 PM PDT 24 Mar 10 12:20:40 PM PDT 24 814104460 ps
T841 /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.1885513574 Mar 10 12:24:13 PM PDT 24 Mar 10 12:24:15 PM PDT 24 419889355 ps
T842 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.1370161984 Mar 10 12:24:45 PM PDT 24 Mar 10 12:24:47 PM PDT 24 998637435 ps
T843 /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.1970808844 Mar 10 12:18:37 PM PDT 24 Mar 10 12:18:38 PM PDT 24 327895696 ps
T844 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.56015539 Mar 10 12:24:31 PM PDT 24 Mar 10 12:24:34 PM PDT 24 675978365 ps
T845 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.200557590 Mar 10 12:24:01 PM PDT 24 Mar 10 12:24:02 PM PDT 24 317425160 ps
T144 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.1280033640 Mar 10 12:20:10 PM PDT 24 Mar 10 12:20:11 PM PDT 24 580661582 ps
T846 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.3330485750 Mar 10 12:33:55 PM PDT 24 Mar 10 12:34:02 PM PDT 24 4725088481 ps
T847 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.2992700705 Mar 10 12:23:03 PM PDT 24 Mar 10 12:23:05 PM PDT 24 468560603 ps
T848 /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.3453807551 Mar 10 12:18:08 PM PDT 24 Mar 10 12:18:15 PM PDT 24 2406769732 ps
T849 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.4153804968 Mar 10 12:21:52 PM PDT 24 Mar 10 12:21:54 PM PDT 24 470780776 ps
T850 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.3748422158 Mar 10 12:20:38 PM PDT 24 Mar 10 12:20:42 PM PDT 24 4411587700 ps
T851 /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.3531280265 Mar 10 12:23:59 PM PDT 24 Mar 10 12:24:01 PM PDT 24 516116420 ps
T852 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.870016070 Mar 10 12:33:49 PM PDT 24 Mar 10 12:33:53 PM PDT 24 669075105 ps
T853 /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.2072643261 Mar 10 12:19:09 PM PDT 24 Mar 10 12:19:11 PM PDT 24 344031927 ps
T854 /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.1415211841 Mar 10 12:29:21 PM PDT 24 Mar 10 12:29:23 PM PDT 24 453891460 ps
T855 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.3313065200 Mar 10 12:24:31 PM PDT 24 Mar 10 12:24:33 PM PDT 24 342746172 ps
T856 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.4286145637 Mar 10 12:24:45 PM PDT 24 Mar 10 12:24:46 PM PDT 24 695879050 ps
T857 /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.3687113318 Mar 10 12:30:24 PM PDT 24 Mar 10 12:30:25 PM PDT 24 409583896 ps
T858 /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.537952048 Mar 10 12:24:31 PM PDT 24 Mar 10 12:24:36 PM PDT 24 2129379358 ps
T859 /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.3872870626 Mar 10 12:18:18 PM PDT 24 Mar 10 12:18:19 PM PDT 24 542612044 ps
T860 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.130796705 Mar 10 12:19:00 PM PDT 24 Mar 10 12:19:02 PM PDT 24 654284320 ps
T861 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.3436251016 Mar 10 12:18:55 PM PDT 24 Mar 10 12:18:57 PM PDT 24 463283352 ps
T862 /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.2194101052 Mar 10 12:18:33 PM PDT 24 Mar 10 12:18:35 PM PDT 24 437903097 ps
T863 /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.3007937766 Mar 10 12:24:15 PM PDT 24 Mar 10 12:24:19 PM PDT 24 2466350591 ps
T864 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.1323569097 Mar 10 12:23:39 PM PDT 24 Mar 10 12:23:42 PM PDT 24 534166492 ps
T865 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.3263995408 Mar 10 12:24:28 PM PDT 24 Mar 10 12:24:29 PM PDT 24 962257027 ps
T866 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.761320060 Mar 10 12:23:18 PM PDT 24 Mar 10 12:23:21 PM PDT 24 594870950 ps
T867 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.1858803245 Mar 10 12:21:49 PM PDT 24 Mar 10 12:21:51 PM PDT 24 451487022 ps
T868 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.1091871514 Mar 10 12:24:07 PM PDT 24 Mar 10 12:24:09 PM PDT 24 387827685 ps
T869 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.3996676988 Mar 10 12:23:22 PM PDT 24 Mar 10 12:23:23 PM PDT 24 553088697 ps
T870 /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.1259590275 Mar 10 12:23:01 PM PDT 24 Mar 10 12:23:02 PM PDT 24 572203352 ps
T871 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.3130442512 Mar 10 12:20:03 PM PDT 24 Mar 10 12:20:04 PM PDT 24 389680897 ps
T872 /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.3182468416 Mar 10 12:24:24 PM PDT 24 Mar 10 12:24:26 PM PDT 24 427603390 ps
T873 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.2762419976 Mar 10 12:33:47 PM PDT 24 Mar 10 12:33:49 PM PDT 24 1000686857 ps
T874 /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.635235292 Mar 10 12:20:03 PM PDT 24 Mar 10 12:20:05 PM PDT 24 2178777692 ps
T875 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.3420638306 Mar 10 12:24:01 PM PDT 24 Mar 10 12:24:04 PM PDT 24 460370521 ps
T145 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.1682388583 Mar 10 12:27:08 PM PDT 24 Mar 10 12:27:10 PM PDT 24 515016497 ps
T876 /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.386204031 Mar 10 12:19:21 PM PDT 24 Mar 10 12:19:23 PM PDT 24 439896505 ps
T877 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.1660232686 Mar 10 12:21:35 PM PDT 24 Mar 10 12:21:37 PM PDT 24 531109401 ps
T878 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.465341308 Mar 10 12:19:48 PM PDT 24 Mar 10 12:19:50 PM PDT 24 341738645 ps
T879 /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.379459452 Mar 10 12:19:10 PM PDT 24 Mar 10 12:19:12 PM PDT 24 318814957 ps
T880 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.1729346619 Mar 10 12:18:40 PM PDT 24 Mar 10 12:18:41 PM PDT 24 417992300 ps
T881 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.2865019405 Mar 10 12:19:26 PM PDT 24 Mar 10 12:19:29 PM PDT 24 546332426 ps
T882 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.2190477306 Mar 10 12:24:27 PM PDT 24 Mar 10 12:24:31 PM PDT 24 556098454 ps
T883 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.2289259911 Mar 10 12:22:08 PM PDT 24 Mar 10 12:22:10 PM PDT 24 585366585 ps
T146 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.4027584035 Mar 10 12:20:52 PM PDT 24 Mar 10 12:20:55 PM PDT 24 1468730572 ps
T884 /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.1289386640 Mar 10 12:18:21 PM PDT 24 Mar 10 12:18:24 PM PDT 24 2542601120 ps
T885 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.2784967215 Mar 10 12:33:57 PM PDT 24 Mar 10 12:34:01 PM PDT 24 516420932 ps
T886 /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.462594344 Mar 10 12:18:15 PM PDT 24 Mar 10 12:18:16 PM PDT 24 506940030 ps
T887 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.4074085134 Mar 10 12:27:21 PM PDT 24 Mar 10 12:27:23 PM PDT 24 590181934 ps
T888 /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.4214674247 Mar 10 12:23:59 PM PDT 24 Mar 10 12:24:00 PM PDT 24 330235474 ps
T889 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.3100846399 Mar 10 12:21:37 PM PDT 24 Mar 10 12:21:44 PM PDT 24 8100132601 ps
T890 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.1986541096 Mar 10 12:24:31 PM PDT 24 Mar 10 12:24:34 PM PDT 24 2088725182 ps
T891 /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.3297285634 Mar 10 12:33:06 PM PDT 24 Mar 10 12:33:08 PM PDT 24 374515859 ps
T892 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.411134085 Mar 10 12:23:59 PM PDT 24 Mar 10 12:24:01 PM PDT 24 1227003303 ps
T893 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.3758633657 Mar 10 12:19:47 PM PDT 24 Mar 10 12:19:49 PM PDT 24 384939884 ps
T894 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.4223508354 Mar 10 12:23:23 PM PDT 24 Mar 10 12:23:24 PM PDT 24 334336377 ps
T895 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.3588297586 Mar 10 12:24:01 PM PDT 24 Mar 10 12:24:02 PM PDT 24 574056163 ps
T896 /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.4138935442 Mar 10 12:29:21 PM PDT 24 Mar 10 12:29:23 PM PDT 24 421599394 ps
T897 /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.602227833 Mar 10 12:32:53 PM PDT 24 Mar 10 12:32:54 PM PDT 24 381840023 ps
T898 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.2785205725 Mar 10 12:23:09 PM PDT 24 Mar 10 12:23:12 PM PDT 24 2016354948 ps
T899 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.3751033350 Mar 10 12:29:32 PM PDT 24 Mar 10 12:31:34 PM PDT 24 52325556296 ps
T900 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.583578516 Mar 10 12:21:18 PM PDT 24 Mar 10 12:21:20 PM PDT 24 550722951 ps
T901 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.2653002544 Mar 10 12:18:48 PM PDT 24 Mar 10 12:18:50 PM PDT 24 598422510 ps
T902 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.1292436668 Mar 10 12:27:21 PM PDT 24 Mar 10 12:27:24 PM PDT 24 420249986 ps
T903 /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.1479322376 Mar 10 12:29:09 PM PDT 24 Mar 10 12:29:11 PM PDT 24 401606947 ps
T904 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.4066500929 Mar 10 12:27:06 PM PDT 24 Mar 10 12:27:09 PM PDT 24 1037742301 ps
T905 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.4102603548 Mar 10 12:24:44 PM PDT 24 Mar 10 12:24:47 PM PDT 24 2419741710 ps
T906 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.2699954719 Mar 10 12:23:59 PM PDT 24 Mar 10 12:24:00 PM PDT 24 355222793 ps
T81 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.3054600348 Mar 10 12:23:54 PM PDT 24 Mar 10 12:24:20 PM PDT 24 8861758709 ps
T907 /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.2670769709 Mar 10 12:26:23 PM PDT 24 Mar 10 12:26:26 PM PDT 24 2294518318 ps
T908 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.460428109 Mar 10 12:27:06 PM PDT 24 Mar 10 12:27:07 PM PDT 24 425016526 ps
T909 /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.2425036356 Mar 10 12:19:06 PM PDT 24 Mar 10 12:19:07 PM PDT 24 430155751 ps
T910 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.3663645220 Mar 10 12:24:01 PM PDT 24 Mar 10 12:24:11 PM PDT 24 4111301944 ps
T911 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.3406619453 Mar 10 12:24:57 PM PDT 24 Mar 10 12:25:10 PM PDT 24 8473102366 ps
T912 /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.3350661254 Mar 10 12:27:21 PM PDT 24 Mar 10 12:27:23 PM PDT 24 340987824 ps
T82 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.2372763823 Mar 10 12:33:55 PM PDT 24 Mar 10 12:34:09 PM PDT 24 8363382096 ps

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.522568503
Short name T1
Test name
Test status
Simulation time 463459792262 ps
CPU time 1078.18 seconds
Started Mar 10 12:29:47 PM PDT 24
Finished Mar 10 12:47:46 PM PDT 24
Peak memory 201448 kb
Host smart-4564792b-cd99-4ad0-823d-2f47253fd25f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522568503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all.
522568503
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.1899367890
Short name T15
Test name
Test status
Simulation time 767393126806 ps
CPU time 302.33 seconds
Started Mar 10 12:30:07 PM PDT 24
Finished Mar 10 12:35:09 PM PDT 24
Peak memory 210216 kb
Host smart-e03e5e0a-d63c-4976-b4d1-bf527b868aa6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899367890 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.1899367890
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.1372478299
Short name T58
Test name
Test status
Simulation time 156549778910 ps
CPU time 760.4 seconds
Started Mar 10 12:30:06 PM PDT 24
Finished Mar 10 12:42:47 PM PDT 24
Peak memory 201676 kb
Host smart-56f7a625-0166-43a1-bc2f-7403996675d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372478299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all
.1372478299
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.2217137719
Short name T155
Test name
Test status
Simulation time 349070958908 ps
CPU time 405.66 seconds
Started Mar 10 12:30:04 PM PDT 24
Finished Mar 10 12:36:49 PM PDT 24
Peak memory 201424 kb
Host smart-1f047ee8-a2ad-47c5-be0c-b02cd1329810
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217137719 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gat
ing.2217137719
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.3544159028
Short name T55
Test name
Test status
Simulation time 362655107390 ps
CPU time 674.8 seconds
Started Mar 10 12:28:40 PM PDT 24
Finished Mar 10 12:39:56 PM PDT 24
Peak memory 201376 kb
Host smart-4c12339f-94d2-49dc-9020-89da77525504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544159028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.3544159028
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.3742183888
Short name T109
Test name
Test status
Simulation time 524663729069 ps
CPU time 1249.12 seconds
Started Mar 10 12:30:33 PM PDT 24
Finished Mar 10 12:51:23 PM PDT 24
Peak memory 201428 kb
Host smart-82d4d163-7656-4ba6-9547-277a0e3fa73c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742183888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.3742183888
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.3864266057
Short name T28
Test name
Test status
Simulation time 4033924270 ps
CPU time 10.29 seconds
Started Mar 10 12:20:39 PM PDT 24
Finished Mar 10 12:20:49 PM PDT 24
Peak memory 201220 kb
Host smart-07c24744-b6b9-4681-a62d-484a15de10c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864266057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_i
ntg_err.3864266057
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.1702089969
Short name T170
Test name
Test status
Simulation time 545564520418 ps
CPU time 241.13 seconds
Started Mar 10 12:31:32 PM PDT 24
Finished Mar 10 12:35:34 PM PDT 24
Peak memory 201356 kb
Host smart-8fdaede3-df5f-455e-a8a4-5cc31cc68b7b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702089969 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gat
ing.1702089969
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.3244124185
Short name T176
Test name
Test status
Simulation time 521129190669 ps
CPU time 264.63 seconds
Started Mar 10 12:29:11 PM PDT 24
Finished Mar 10 12:33:36 PM PDT 24
Peak memory 201416 kb
Host smart-c6e872c4-05b4-4780-b17e-938c4b062fea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244124185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.3244124185
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.2544812888
Short name T179
Test name
Test status
Simulation time 549718522778 ps
CPU time 276.57 seconds
Started Mar 10 12:31:33 PM PDT 24
Finished Mar 10 12:36:10 PM PDT 24
Peak memory 201460 kb
Host smart-2d67dc41-8398-41e0-b584-0d23ec8681c9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544812888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gat
ing.2544812888
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.1157710292
Short name T275
Test name
Test status
Simulation time 495613969224 ps
CPU time 580.93 seconds
Started Mar 10 12:29:27 PM PDT 24
Finished Mar 10 12:39:08 PM PDT 24
Peak memory 201384 kb
Host smart-895221fd-dea9-4dae-8b37-3fdb63e5c56c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157710292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.1157710292
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.179848145
Short name T171
Test name
Test status
Simulation time 584675478626 ps
CPU time 1425.75 seconds
Started Mar 10 12:30:10 PM PDT 24
Finished Mar 10 12:53:57 PM PDT 24
Peak memory 201432 kb
Host smart-f8ce8d85-0d61-453e-803b-6eeb90d188af
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179848145 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_
wakeup.179848145
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.3150365652
Short name T36
Test name
Test status
Simulation time 258613489943 ps
CPU time 120.25 seconds
Started Mar 10 12:29:40 PM PDT 24
Finished Mar 10 12:31:41 PM PDT 24
Peak memory 212108 kb
Host smart-2a6c4605-058e-4838-8815-101d765bb014
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150365652 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.3150365652
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.2498011595
Short name T10
Test name
Test status
Simulation time 197904786313 ps
CPU time 461.95 seconds
Started Mar 10 12:30:23 PM PDT 24
Finished Mar 10 12:38:06 PM PDT 24
Peak memory 201368 kb
Host smart-49fc7734-89fd-44cb-a393-9cbccaca10d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498011595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all
.2498011595
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.3548148879
Short name T40
Test name
Test status
Simulation time 424561175 ps
CPU time 3.01 seconds
Started Mar 10 12:23:03 PM PDT 24
Finished Mar 10 12:23:06 PM PDT 24
Peak memory 210432 kb
Host smart-9c84bec3-1cfb-46e5-a01b-2e8a3fa384f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548148879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.3548148879
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.283923787
Short name T164
Test name
Test status
Simulation time 532983476641 ps
CPU time 1091.17 seconds
Started Mar 10 12:29:28 PM PDT 24
Finished Mar 10 12:47:39 PM PDT 24
Peak memory 201416 kb
Host smart-56e9f66f-b0a4-4caa-99c3-f75e9d19e4a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283923787 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.283923787
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.1250040564
Short name T13
Test name
Test status
Simulation time 433915015 ps
CPU time 1.1 seconds
Started Mar 10 12:36:49 PM PDT 24
Finished Mar 10 12:36:51 PM PDT 24
Peak memory 201408 kb
Host smart-57e9e98e-5f1f-4849-a535-34d177ec45de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250040564 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.1250040564
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.406070695
Short name T138
Test name
Test status
Simulation time 33284909239 ps
CPU time 32.12 seconds
Started Mar 10 12:20:03 PM PDT 24
Finished Mar 10 12:20:36 PM PDT 24
Peak memory 201136 kb
Host smart-0d81c0e2-c300-48f8-8f89-6ea18d1dde2f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406070695 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_b
ash.406070695
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.368158138
Short name T85
Test name
Test status
Simulation time 827385775576 ps
CPU time 135.98 seconds
Started Mar 10 12:28:53 PM PDT 24
Finished Mar 10 12:31:09 PM PDT 24
Peak memory 209776 kb
Host smart-582fc65a-6957-4973-a863-b031f2537534
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368158138 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.368158138
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.1904449574
Short name T187
Test name
Test status
Simulation time 353833084296 ps
CPU time 748.09 seconds
Started Mar 10 12:39:18 PM PDT 24
Finished Mar 10 12:51:47 PM PDT 24
Peak memory 201528 kb
Host smart-e7f559de-6ede-4134-9f6a-8a7b560c9eb0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904449574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gat
ing.1904449574
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.2628095876
Short name T264
Test name
Test status
Simulation time 321792852935 ps
CPU time 830.76 seconds
Started Mar 10 12:29:19 PM PDT 24
Finished Mar 10 12:43:10 PM PDT 24
Peak memory 201388 kb
Host smart-151b7752-c7ba-4e1f-af9c-6e8a59877efa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628095876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.2628095876
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.3515243204
Short name T57
Test name
Test status
Simulation time 335491541911 ps
CPU time 201.92 seconds
Started Mar 10 12:28:50 PM PDT 24
Finished Mar 10 12:32:12 PM PDT 24
Peak memory 201392 kb
Host smart-337a8a89-73d6-4bc1-8ef6-fadde09a4576
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515243204 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrup
t_fixed.3515243204
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.2701720318
Short name T228
Test name
Test status
Simulation time 498876691225 ps
CPU time 321.46 seconds
Started Mar 10 12:30:14 PM PDT 24
Finished Mar 10 12:35:36 PM PDT 24
Peak memory 201440 kb
Host smart-41afa889-5167-45f2-b835-357bb687bfcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701720318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.2701720318
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.1420961165
Short name T168
Test name
Test status
Simulation time 533763353479 ps
CPU time 1262.09 seconds
Started Mar 10 12:30:14 PM PDT 24
Finished Mar 10 12:51:16 PM PDT 24
Peak memory 201388 kb
Host smart-c60834b4-18cb-430d-b04c-c260072c6f60
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420961165 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters
_wakeup.1420961165
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.3207667046
Short name T271
Test name
Test status
Simulation time 524712429102 ps
CPU time 1026.43 seconds
Started Mar 10 12:29:43 PM PDT 24
Finished Mar 10 12:46:50 PM PDT 24
Peak memory 201428 kb
Host smart-ff10c794-4a72-4ce8-8d36-8b047ae13b9e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207667046 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gat
ing.3207667046
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.2413496804
Short name T343
Test name
Test status
Simulation time 201859308389 ps
CPU time 211.1 seconds
Started Mar 10 12:30:13 PM PDT 24
Finished Mar 10 12:33:44 PM PDT 24
Peak memory 209956 kb
Host smart-f7323028-4317-46a2-855f-b97f2c4b157c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413496804 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.2413496804
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.298663074
Short name T286
Test name
Test status
Simulation time 159747209895 ps
CPU time 403.09 seconds
Started Mar 10 12:29:18 PM PDT 24
Finished Mar 10 12:36:01 PM PDT 24
Peak memory 201388 kb
Host smart-c0d2bf36-591a-4e89-9bff-a78af82ddaef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298663074 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.298663074
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.826521891
Short name T218
Test name
Test status
Simulation time 549073940960 ps
CPU time 289.59 seconds
Started Mar 10 12:31:16 PM PDT 24
Finished Mar 10 12:36:06 PM PDT 24
Peak memory 201496 kb
Host smart-36833ca6-a451-4fcb-9446-3d5f63fa3819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826521891 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.826521891
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.1173480874
Short name T256
Test name
Test status
Simulation time 330875811931 ps
CPU time 324.64 seconds
Started Mar 10 12:31:44 PM PDT 24
Finished Mar 10 12:37:09 PM PDT 24
Peak memory 201388 kb
Host smart-2f770ea9-6480-41cf-8137-758a425b9399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173480874 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.1173480874
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.3156223173
Short name T84
Test name
Test status
Simulation time 3978766887 ps
CPU time 5.63 seconds
Started Mar 10 12:28:57 PM PDT 24
Finished Mar 10 12:29:03 PM PDT 24
Peak memory 216628 kb
Host smart-25014823-2ac0-43e3-83e0-9db83e6c85c2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156223173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.3156223173
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.3836385596
Short name T257
Test name
Test status
Simulation time 593141856623 ps
CPU time 362.49 seconds
Started Mar 10 12:30:57 PM PDT 24
Finished Mar 10 12:37:00 PM PDT 24
Peak memory 201428 kb
Host smart-14a66eaa-4494-4e5f-bcfa-6b211f82df96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836385596 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.3836385596
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.3388702057
Short name T345
Test name
Test status
Simulation time 163296003696 ps
CPU time 374.39 seconds
Started Mar 10 12:29:00 PM PDT 24
Finished Mar 10 12:35:15 PM PDT 24
Peak memory 201476 kb
Host smart-a84a2a01-983c-4b85-a8a7-53a4e51f1412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388702057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.3388702057
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.466315407
Short name T285
Test name
Test status
Simulation time 345605367444 ps
CPU time 411.31 seconds
Started Mar 10 12:28:53 PM PDT 24
Finished Mar 10 12:35:45 PM PDT 24
Peak memory 201428 kb
Host smart-285105e4-a48b-4b0d-aa6e-739867a1c86f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466315407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gatin
g.466315407
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.1660409995
Short name T173
Test name
Test status
Simulation time 433470258661 ps
CPU time 477.64 seconds
Started Mar 10 12:29:42 PM PDT 24
Finished Mar 10 12:37:40 PM PDT 24
Peak memory 211876 kb
Host smart-89b1353b-b811-4a1c-ab5e-0f3fcd679976
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660409995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all
.1660409995
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.1445131694
Short name T21
Test name
Test status
Simulation time 39354519620 ps
CPU time 129.11 seconds
Started Mar 10 12:29:42 PM PDT 24
Finished Mar 10 12:31:52 PM PDT 24
Peak memory 210044 kb
Host smart-966c78ee-b37f-4b52-8c27-8e954e4601ad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445131694 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.1445131694
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.1438080641
Short name T232
Test name
Test status
Simulation time 524885520564 ps
CPU time 1234.91 seconds
Started Mar 10 12:30:26 PM PDT 24
Finished Mar 10 12:51:01 PM PDT 24
Peak memory 201364 kb
Host smart-1f0bf5cd-920d-4ae2-bc07-d9f7fac2f364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438080641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.1438080641
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.3562310427
Short name T260
Test name
Test status
Simulation time 540991113700 ps
CPU time 435.7 seconds
Started Mar 10 12:29:48 PM PDT 24
Finished Mar 10 12:37:04 PM PDT 24
Peak memory 201464 kb
Host smart-ef17c975-861f-41b5-a1bf-73c3d43fa691
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562310427 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gat
ing.3562310427
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.4106255265
Short name T287
Test name
Test status
Simulation time 531809690547 ps
CPU time 1109.73 seconds
Started Mar 10 12:30:10 PM PDT 24
Finished Mar 10 12:48:40 PM PDT 24
Peak memory 201404 kb
Host smart-ea57c550-8f66-497f-999d-0fc81ed0cf8b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106255265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gat
ing.4106255265
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.3284308826
Short name T344
Test name
Test status
Simulation time 501224550177 ps
CPU time 396.46 seconds
Started Mar 10 12:29:16 PM PDT 24
Finished Mar 10 12:35:53 PM PDT 24
Peak memory 201428 kb
Host smart-85c39b41-9de8-42b5-85f5-62658d1f9798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284308826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.3284308826
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.1744917141
Short name T156
Test name
Test status
Simulation time 327329480673 ps
CPU time 203.42 seconds
Started Mar 10 12:29:37 PM PDT 24
Finished Mar 10 12:33:00 PM PDT 24
Peak memory 201476 kb
Host smart-99a49e87-b90c-4c9c-816b-7f18779a082b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744917141 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.1744917141
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.1855766820
Short name T314
Test name
Test status
Simulation time 493971137250 ps
CPU time 293.23 seconds
Started Mar 10 12:28:43 PM PDT 24
Finished Mar 10 12:33:38 PM PDT 24
Peak memory 201368 kb
Host smart-7be2e535-b4ab-41e1-8c66-2118f2a62bf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855766820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.1855766820
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.324276381
Short name T269
Test name
Test status
Simulation time 518757254909 ps
CPU time 674.27 seconds
Started Mar 10 12:31:43 PM PDT 24
Finished Mar 10 12:42:59 PM PDT 24
Peak memory 201380 kb
Host smart-4176e1b4-2721-4b38-adb8-a232f676cd15
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324276381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_
wakeup.324276381
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.1260896285
Short name T312
Test name
Test status
Simulation time 512234725762 ps
CPU time 1194.38 seconds
Started Mar 10 12:29:32 PM PDT 24
Finished Mar 10 12:49:26 PM PDT 24
Peak memory 201544 kb
Host smart-51b70cc3-f403-46b5-a494-199d3f9bfb35
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260896285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gat
ing.1260896285
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.2792861048
Short name T137
Test name
Test status
Simulation time 477843523 ps
CPU time 0.99 seconds
Started Mar 10 12:24:28 PM PDT 24
Finished Mar 10 12:24:29 PM PDT 24
Peak memory 200088 kb
Host smart-f32b1f75-d938-4d44-9774-c5c0af1d27c2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792861048 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.2792861048
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.809010600
Short name T327
Test name
Test status
Simulation time 156643147770 ps
CPU time 93.76 seconds
Started Mar 10 12:29:19 PM PDT 24
Finished Mar 10 12:30:53 PM PDT 24
Peak memory 201488 kb
Host smart-951f94d5-f9a6-4cc7-8858-4d79c43c16da
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809010600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gati
ng.809010600
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.2066865595
Short name T181
Test name
Test status
Simulation time 321110250645 ps
CPU time 356.57 seconds
Started Mar 10 12:29:58 PM PDT 24
Finished Mar 10 12:35:55 PM PDT 24
Peak memory 201420 kb
Host smart-bbc7b23a-1107-43e4-960a-a18fe5d2f36f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066865595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.2066865595
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.2511083684
Short name T239
Test name
Test status
Simulation time 115827582498 ps
CPU time 413.16 seconds
Started Mar 10 12:30:35 PM PDT 24
Finished Mar 10 12:37:28 PM PDT 24
Peak memory 201696 kb
Host smart-5b7538b1-3e54-4570-b27a-40305abdc29d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511083684 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.2511083684
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.2717346437
Short name T80
Test name
Test status
Simulation time 4330808829 ps
CPU time 10.76 seconds
Started Mar 10 12:19:07 PM PDT 24
Finished Mar 10 12:19:18 PM PDT 24
Peak memory 201172 kb
Host smart-f6dbc5a5-41d4-4927-8e0d-765fb798c95c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717346437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_in
tg_err.2717346437
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.1835927461
Short name T307
Test name
Test status
Simulation time 30663639329 ps
CPU time 39.84 seconds
Started Mar 10 12:29:07 PM PDT 24
Finished Mar 10 12:29:47 PM PDT 24
Peak memory 209792 kb
Host smart-aefff495-7aa9-4696-8b26-632f92cc0c7d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835927461 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.1835927461
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.553341678
Short name T265
Test name
Test status
Simulation time 520423494377 ps
CPU time 1216.28 seconds
Started Mar 10 12:30:30 PM PDT 24
Finished Mar 10 12:50:47 PM PDT 24
Peak memory 201484 kb
Host smart-2d64511c-dcac-40b9-b6ba-140430307bc6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553341678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_
wakeup.553341678
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.399249002
Short name T282
Test name
Test status
Simulation time 559429268338 ps
CPU time 326.56 seconds
Started Mar 10 12:30:47 PM PDT 24
Finished Mar 10 12:36:14 PM PDT 24
Peak memory 201464 kb
Host smart-3d9465ab-3d53-42ee-bb03-9484e72fdada
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399249002 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_
wakeup.399249002
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.692343218
Short name T274
Test name
Test status
Simulation time 485855047836 ps
CPU time 1174.91 seconds
Started Mar 10 12:30:54 PM PDT 24
Finished Mar 10 12:50:29 PM PDT 24
Peak memory 201456 kb
Host smart-a74405fa-423d-49f7-8dff-62fa6de2c7c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692343218 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.692343218
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.3663748024
Short name T76
Test name
Test status
Simulation time 550294564 ps
CPU time 2.88 seconds
Started Mar 10 12:21:32 PM PDT 24
Finished Mar 10 12:21:35 PM PDT 24
Peak memory 217532 kb
Host smart-793669ca-1154-4a33-bade-701f9b692c5a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663748024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.3663748024
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.498216446
Short name T394
Test name
Test status
Simulation time 212286182196 ps
CPU time 140.03 seconds
Started Mar 10 12:29:22 PM PDT 24
Finished Mar 10 12:31:44 PM PDT 24
Peak memory 201428 kb
Host smart-6f31e57a-0ca5-4245-a242-49d496970300
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498216446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
adc_ctrl_filters_wakeup_fixed.498216446
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.2910783449
Short name T335
Test name
Test status
Simulation time 578093764684 ps
CPU time 1392 seconds
Started Mar 10 12:29:33 PM PDT 24
Finished Mar 10 12:52:46 PM PDT 24
Peak memory 201432 kb
Host smart-6a3435a9-1996-4711-b4ed-48b0549e26f7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910783449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters
_wakeup.2910783449
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.3197895391
Short name T251
Test name
Test status
Simulation time 383010604451 ps
CPU time 881.55 seconds
Started Mar 10 12:29:19 PM PDT 24
Finished Mar 10 12:44:01 PM PDT 24
Peak memory 201348 kb
Host smart-f1572162-5a11-4296-b063-ca64d1a15def
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197895391 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_
wakeup.3197895391
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.347257041
Short name T238
Test name
Test status
Simulation time 462295781596 ps
CPU time 876.47 seconds
Started Mar 10 12:29:21 PM PDT 24
Finished Mar 10 12:43:58 PM PDT 24
Peak memory 201612 kb
Host smart-8b26942b-25b1-4b3e-9343-1c2ea8c203dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347257041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all.
347257041
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.4166156453
Short name T47
Test name
Test status
Simulation time 69782253309 ps
CPU time 311.18 seconds
Started Mar 10 12:29:23 PM PDT 24
Finished Mar 10 12:34:36 PM PDT 24
Peak memory 209992 kb
Host smart-baa11b2d-34fc-4d64-b2e1-6a33f0a89600
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166156453 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.4166156453
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.1582298430
Short name T279
Test name
Test status
Simulation time 343873963510 ps
CPU time 415.73 seconds
Started Mar 10 12:29:54 PM PDT 24
Finished Mar 10 12:36:50 PM PDT 24
Peak memory 201292 kb
Host smart-bd7bf8fc-3037-4a1d-8df3-84b627993940
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582298430 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters
_wakeup.1582298430
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.2215704064
Short name T284
Test name
Test status
Simulation time 380529868817 ps
CPU time 91.09 seconds
Started Mar 10 12:29:00 PM PDT 24
Finished Mar 10 12:30:31 PM PDT 24
Peak memory 201532 kb
Host smart-0446580c-863b-43e9-938e-42f3f97e38f3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215704064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_
wakeup.2215704064
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.733892909
Short name T116
Test name
Test status
Simulation time 181267639204 ps
CPU time 212.13 seconds
Started Mar 10 12:30:09 PM PDT 24
Finished Mar 10 12:33:42 PM PDT 24
Peak memory 201460 kb
Host smart-7605f7cc-d454-470f-8196-7f9b8dbfe65a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733892909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_
wakeup.733892909
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.2419952481
Short name T233
Test name
Test status
Simulation time 524560759849 ps
CPU time 851.33 seconds
Started Mar 10 12:30:19 PM PDT 24
Finished Mar 10 12:44:31 PM PDT 24
Peak memory 201480 kb
Host smart-2d09ba0a-3b91-49ae-a1a9-5483a67c0010
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419952481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gat
ing.2419952481
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.1510412723
Short name T293
Test name
Test status
Simulation time 165104064393 ps
CPU time 96.89 seconds
Started Mar 10 12:31:23 PM PDT 24
Finished Mar 10 12:33:00 PM PDT 24
Peak memory 201460 kb
Host smart-849f0248-2e9b-4d5b-ba92-921a9eb0a0cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510412723 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.1510412723
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.3242492483
Short name T69
Test name
Test status
Simulation time 8352688358 ps
CPU time 12.63 seconds
Started Mar 10 12:18:22 PM PDT 24
Finished Mar 10 12:18:35 PM PDT 24
Peak memory 201208 kb
Host smart-b50bff28-2727-4c20-85ab-9e268842b1fd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242492483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_i
ntg_err.3242492483
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.2731563434
Short name T332
Test name
Test status
Simulation time 338686761718 ps
CPU time 218.92 seconds
Started Mar 10 12:29:19 PM PDT 24
Finished Mar 10 12:32:59 PM PDT 24
Peak memory 201364 kb
Host smart-39adc936-cd22-468e-9299-22c2fbd50bec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731563434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all
.2731563434
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.3049110151
Short name T32
Test name
Test status
Simulation time 78481949622 ps
CPU time 231.2 seconds
Started Mar 10 12:29:20 PM PDT 24
Finished Mar 10 12:33:12 PM PDT 24
Peak memory 201768 kb
Host smart-16f76b39-f9ac-4b52-aa22-42497b6ee364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049110151 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.3049110151
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.2474832922
Short name T306
Test name
Test status
Simulation time 166538893020 ps
CPU time 380.66 seconds
Started Mar 10 12:29:21 PM PDT 24
Finished Mar 10 12:35:43 PM PDT 24
Peak memory 201424 kb
Host smart-130d1782-0fae-4ee2-a400-f63ad7e87588
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474832922 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gat
ing.2474832922
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.384944974
Short name T301
Test name
Test status
Simulation time 482332101176 ps
CPU time 585.84 seconds
Started Mar 10 12:29:47 PM PDT 24
Finished Mar 10 12:39:33 PM PDT 24
Peak memory 201340 kb
Host smart-a7f3f2b8-56a6-46ae-adca-9e442ea01e3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384944974 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.384944974
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.2159312060
Short name T17
Test name
Test status
Simulation time 184724144194 ps
CPU time 114.57 seconds
Started Mar 10 12:29:55 PM PDT 24
Finished Mar 10 12:31:50 PM PDT 24
Peak memory 201344 kb
Host smart-a3704189-ac4d-462f-aecc-a8cd71e1d058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159312060 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.2159312060
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.637862357
Short name T317
Test name
Test status
Simulation time 164306503346 ps
CPU time 365.57 seconds
Started Mar 10 12:30:11 PM PDT 24
Finished Mar 10 12:36:17 PM PDT 24
Peak memory 201428 kb
Host smart-847ff3f7-5d47-4566-b605-026a9f18237e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637862357 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.637862357
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.4014856912
Short name T244
Test name
Test status
Simulation time 70780766616 ps
CPU time 369.78 seconds
Started Mar 10 12:29:21 PM PDT 24
Finished Mar 10 12:35:32 PM PDT 24
Peak memory 201580 kb
Host smart-eec078c6-62ba-4ef3-be41-fc60c98d856b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014856912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.4014856912
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.2646446093
Short name T324
Test name
Test status
Simulation time 379821744177 ps
CPU time 193.14 seconds
Started Mar 10 12:29:20 PM PDT 24
Finished Mar 10 12:32:33 PM PDT 24
Peak memory 201384 kb
Host smart-e196ac18-0c50-480a-94ea-ee176ea61bd1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646446093 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters
_wakeup.2646446093
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.2966338235
Short name T316
Test name
Test status
Simulation time 302333802373 ps
CPU time 1094.38 seconds
Started Mar 10 12:29:17 PM PDT 24
Finished Mar 10 12:47:32 PM PDT 24
Peak memory 209784 kb
Host smart-18b92f93-c2d4-49e0-9b8c-6ca35d553057
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966338235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all
.2966338235
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.4226408465
Short name T24
Test name
Test status
Simulation time 23827361064 ps
CPU time 38.29 seconds
Started Mar 10 12:29:19 PM PDT 24
Finished Mar 10 12:29:58 PM PDT 24
Peak memory 201556 kb
Host smart-0e0955b5-f7f6-405f-abc6-9f443ad48352
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226408465 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.4226408465
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.1656056203
Short name T235
Test name
Test status
Simulation time 91039690115 ps
CPU time 387.23 seconds
Started Mar 10 12:29:25 PM PDT 24
Finished Mar 10 12:35:53 PM PDT 24
Peak memory 201684 kb
Host smart-9a638bb7-1149-40bf-9053-6d28832c5c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656056203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.1656056203
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.1191229299
Short name T304
Test name
Test status
Simulation time 329134539579 ps
CPU time 69.18 seconds
Started Mar 10 12:29:27 PM PDT 24
Finished Mar 10 12:30:37 PM PDT 24
Peak memory 201348 kb
Host smart-6b24c590-68f4-4a7a-9c41-8b15d33ef5c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191229299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.1191229299
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.2569431778
Short name T356
Test name
Test status
Simulation time 185275788354 ps
CPU time 226.8 seconds
Started Mar 10 12:29:44 PM PDT 24
Finished Mar 10 12:33:31 PM PDT 24
Peak memory 201412 kb
Host smart-22c5002f-b713-4c15-82cb-22414402d312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569431778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.2569431778
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.1528145039
Short name T201
Test name
Test status
Simulation time 84529960500 ps
CPU time 452.1 seconds
Started Mar 10 12:29:41 PM PDT 24
Finished Mar 10 12:37:14 PM PDT 24
Peak memory 201728 kb
Host smart-a18c7e28-eb42-4492-9dc1-03d67c27e7e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528145039 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.1528145039
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.3510177535
Short name T351
Test name
Test status
Simulation time 251552616934 ps
CPU time 297.5 seconds
Started Mar 10 12:29:07 PM PDT 24
Finished Mar 10 12:34:04 PM PDT 24
Peak memory 209856 kb
Host smart-8cd3fb6d-7b4e-4453-b93b-15b773ee6a18
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510177535 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.3510177535
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.2547782001
Short name T732
Test name
Test status
Simulation time 81510619110 ps
CPU time 373.15 seconds
Started Mar 10 12:29:58 PM PDT 24
Finished Mar 10 12:36:11 PM PDT 24
Peak memory 201832 kb
Host smart-864f95e6-e1ff-461a-8740-1d70983ccf81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547782001 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.2547782001
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.935386669
Short name T245
Test name
Test status
Simulation time 91180214540 ps
CPU time 380.45 seconds
Started Mar 10 12:30:24 PM PDT 24
Finished Mar 10 12:36:45 PM PDT 24
Peak memory 201840 kb
Host smart-8768c5dc-f2f6-422b-b49f-2c28be21e8ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935386669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.935386669
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.3605197575
Short name T299
Test name
Test status
Simulation time 300060304619 ps
CPU time 967.07 seconds
Started Mar 10 12:30:24 PM PDT 24
Finished Mar 10 12:46:31 PM PDT 24
Peak memory 211672 kb
Host smart-9d391b93-8693-4c9d-924c-a83ce1a0b959
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605197575 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all
.3605197575
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.1507792885
Short name T241
Test name
Test status
Simulation time 111635288148 ps
CPU time 636.02 seconds
Started Mar 10 12:30:30 PM PDT 24
Finished Mar 10 12:41:06 PM PDT 24
Peak memory 201696 kb
Host smart-de09b78a-6d82-4257-910e-4771fe2a561a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507792885 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all
.1507792885
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.2763684170
Short name T186
Test name
Test status
Simulation time 493503711857 ps
CPU time 225.93 seconds
Started Mar 10 12:29:01 PM PDT 24
Finished Mar 10 12:32:47 PM PDT 24
Peak memory 201404 kb
Host smart-25be89ce-6f3a-4764-ae56-a5fcc09ae6da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763684170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.2763684170
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.1938508794
Short name T373
Test name
Test status
Simulation time 121421020551 ps
CPU time 421.77 seconds
Started Mar 10 12:29:13 PM PDT 24
Finished Mar 10 12:36:15 PM PDT 24
Peak memory 201696 kb
Host smart-43283c26-5259-4a7f-8b70-5d732b5cacc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938508794 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.1938508794
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.2127551103
Short name T371
Test name
Test status
Simulation time 26216808676 ps
CPU time 73.68 seconds
Started Mar 10 12:29:21 PM PDT 24
Finished Mar 10 12:30:36 PM PDT 24
Peak memory 209796 kb
Host smart-a3e435ca-dd71-47ea-b48b-f3d937ca566c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127551103 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.2127551103
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.4027584035
Short name T146
Test name
Test status
Simulation time 1468730572 ps
CPU time 2.92 seconds
Started Mar 10 12:20:52 PM PDT 24
Finished Mar 10 12:20:55 PM PDT 24
Peak memory 201128 kb
Host smart-5a1663b6-dc05-47b4-b3b6-337154d71610
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027584035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alia
sing.4027584035
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.3263995408
Short name T865
Test name
Test status
Simulation time 962257027 ps
CPU time 1.22 seconds
Started Mar 10 12:24:28 PM PDT 24
Finished Mar 10 12:24:29 PM PDT 24
Peak memory 200100 kb
Host smart-f27e5c3b-fe92-415e-b87f-a4c7783be397
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263995408 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_r
eset.3263995408
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.3260533654
Short name T798
Test name
Test status
Simulation time 481827259 ps
CPU time 1.8 seconds
Started Mar 10 12:20:03 PM PDT 24
Finished Mar 10 12:20:04 PM PDT 24
Peak memory 200316 kb
Host smart-152851dd-9f1e-4ca5-b614-ef89a3d44d6c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260533654 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.3260533654
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.3758633657
Short name T893
Test name
Test status
Simulation time 384939884 ps
CPU time 1.04 seconds
Started Mar 10 12:19:47 PM PDT 24
Finished Mar 10 12:19:49 PM PDT 24
Peak memory 200964 kb
Host smart-c57a1085-9b2a-4987-b3f2-042757212d2a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758633657 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.3758633657
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.602227833
Short name T897
Test name
Test status
Simulation time 381840023 ps
CPU time 0.87 seconds
Started Mar 10 12:32:53 PM PDT 24
Finished Mar 10 12:32:54 PM PDT 24
Peak memory 200952 kb
Host smart-bc591dbe-72ac-41c3-9584-0f75a338f34a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602227833 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.602227833
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.4102603548
Short name T905
Test name
Test status
Simulation time 2419741710 ps
CPU time 2.27 seconds
Started Mar 10 12:24:44 PM PDT 24
Finished Mar 10 12:24:47 PM PDT 24
Peak memory 201016 kb
Host smart-1249372e-df65-43a1-807d-a9bbd94d80d0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102603548 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_c
trl_same_csr_outstanding.4102603548
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.1660232686
Short name T877
Test name
Test status
Simulation time 531109401 ps
CPU time 1.93 seconds
Started Mar 10 12:21:35 PM PDT 24
Finished Mar 10 12:21:37 PM PDT 24
Peak memory 201200 kb
Host smart-924fae90-d56b-468d-87f5-220d3ffbfdbb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660232686 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.1660232686
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.2372763823
Short name T82
Test name
Test status
Simulation time 8363382096 ps
CPU time 13.07 seconds
Started Mar 10 12:33:55 PM PDT 24
Finished Mar 10 12:34:09 PM PDT 24
Peak memory 201180 kb
Host smart-83ebee0a-f04e-4e9a-aade-5e2c6eade4c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372763823 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_in
tg_err.2372763823
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.870016070
Short name T852
Test name
Test status
Simulation time 669075105 ps
CPU time 3.16 seconds
Started Mar 10 12:33:49 PM PDT 24
Finished Mar 10 12:33:53 PM PDT 24
Peak memory 201180 kb
Host smart-963dad28-92cc-4767-b531-b28a72fce3d8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870016070 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alias
ing.870016070
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.1032306917
Short name T62
Test name
Test status
Simulation time 2788855288 ps
CPU time 7.21 seconds
Started Mar 10 12:24:29 PM PDT 24
Finished Mar 10 12:24:36 PM PDT 24
Peak memory 201120 kb
Host smart-4ba60cdf-8ede-43f0-8e5c-08496f371d52
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032306917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_
bash.1032306917
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.411134085
Short name T892
Test name
Test status
Simulation time 1227003303 ps
CPU time 2.15 seconds
Started Mar 10 12:23:59 PM PDT 24
Finished Mar 10 12:24:01 PM PDT 24
Peak memory 200532 kb
Host smart-b5b7796d-fe7b-4a3b-8ea7-d8afb07663ca
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411134085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_re
set.411134085
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.4048352055
Short name T805
Test name
Test status
Simulation time 487252418 ps
CPU time 2.04 seconds
Started Mar 10 12:33:53 PM PDT 24
Finished Mar 10 12:33:56 PM PDT 24
Peak memory 201036 kb
Host smart-ebcfa38d-3ec8-41b1-8700-2662d79dc590
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048352055 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.4048352055
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.4214674247
Short name T888
Test name
Test status
Simulation time 330235474 ps
CPU time 1.12 seconds
Started Mar 10 12:23:59 PM PDT 24
Finished Mar 10 12:24:00 PM PDT 24
Peak memory 199380 kb
Host smart-7df4842b-6e92-43d7-a1a0-1d2e40af1306
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214674247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.4214674247
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.1793507466
Short name T825
Test name
Test status
Simulation time 2495084349 ps
CPU time 3.76 seconds
Started Mar 10 12:20:41 PM PDT 24
Finished Mar 10 12:20:45 PM PDT 24
Peak memory 201064 kb
Host smart-7dc8a53f-d4ed-49f6-beab-c7c6464c2704
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793507466 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_c
trl_same_csr_outstanding.1793507466
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.3939575880
Short name T840
Test name
Test status
Simulation time 814104460 ps
CPU time 1.18 seconds
Started Mar 10 12:20:39 PM PDT 24
Finished Mar 10 12:20:40 PM PDT 24
Peak memory 201056 kb
Host smart-40da9ed5-3dc5-4b1a-8b0e-8b762d72700e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939575880 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.3939575880
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.1682388583
Short name T145
Test name
Test status
Simulation time 515016497 ps
CPU time 2.11 seconds
Started Mar 10 12:27:08 PM PDT 24
Finished Mar 10 12:27:10 PM PDT 24
Peak memory 200960 kb
Host smart-807f78a7-4178-472d-b10d-309c935c98cc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682388583 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.1682388583
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.1885513574
Short name T841
Test name
Test status
Simulation time 419889355 ps
CPU time 1.57 seconds
Started Mar 10 12:24:13 PM PDT 24
Finished Mar 10 12:24:15 PM PDT 24
Peak memory 200128 kb
Host smart-98b275b4-9496-4346-8328-13e84c7df506
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885513574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.1885513574
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.2785205725
Short name T898
Test name
Test status
Simulation time 2016354948 ps
CPU time 2.18 seconds
Started Mar 10 12:23:09 PM PDT 24
Finished Mar 10 12:23:12 PM PDT 24
Peak memory 200860 kb
Host smart-6d9092e4-8e84-4ecd-9b43-86cb39267a2e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785205725 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_
ctrl_same_csr_outstanding.2785205725
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.3416965685
Short name T822
Test name
Test status
Simulation time 798213983 ps
CPU time 2.37 seconds
Started Mar 10 12:24:31 PM PDT 24
Finished Mar 10 12:24:33 PM PDT 24
Peak memory 209376 kb
Host smart-a0c23e27-2fc6-4579-9ae2-a956c2cc051c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416965685 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.3416965685
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.56015539
Short name T844
Test name
Test status
Simulation time 675978365 ps
CPU time 2.47 seconds
Started Mar 10 12:24:31 PM PDT 24
Finished Mar 10 12:24:34 PM PDT 24
Peak memory 200988 kb
Host smart-85e2b9f3-0604-4c87-8119-aae977ef0e8f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56015539 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.56015539
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.460428109
Short name T908
Test name
Test status
Simulation time 425016526 ps
CPU time 1.25 seconds
Started Mar 10 12:27:06 PM PDT 24
Finished Mar 10 12:27:07 PM PDT 24
Peak memory 200964 kb
Host smart-f4fe1ff5-f354-42ca-935d-121ead926f8d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460428109 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.460428109
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.200557590
Short name T845
Test name
Test status
Simulation time 317425160 ps
CPU time 1.3 seconds
Started Mar 10 12:24:01 PM PDT 24
Finished Mar 10 12:24:02 PM PDT 24
Peak memory 200876 kb
Host smart-4fde922a-6be1-445e-8c59-35740e95df08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200557590 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.200557590
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.3031576249
Short name T149
Test name
Test status
Simulation time 4176270602 ps
CPU time 4.75 seconds
Started Mar 10 12:23:22 PM PDT 24
Finished Mar 10 12:23:27 PM PDT 24
Peak memory 200100 kb
Host smart-211dfc39-24c6-485e-a456-ab54a1fa8595
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031576249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_
ctrl_same_csr_outstanding.3031576249
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.1319701687
Short name T77
Test name
Test status
Simulation time 598108045 ps
CPU time 2.95 seconds
Started Mar 10 12:23:39 PM PDT 24
Finished Mar 10 12:23:43 PM PDT 24
Peak memory 201208 kb
Host smart-fd9fd017-759e-4227-9467-d0c8194841f6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319701687 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.1319701687
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.2774183151
Short name T832
Test name
Test status
Simulation time 8225868975 ps
CPU time 20.74 seconds
Started Mar 10 12:20:42 PM PDT 24
Finished Mar 10 12:21:04 PM PDT 24
Peak memory 201184 kb
Host smart-7c096bac-bb7a-417e-8515-ccfb20aa0364
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774183151 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_i
ntg_err.2774183151
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.1052647398
Short name T96
Test name
Test status
Simulation time 357308215 ps
CPU time 1.68 seconds
Started Mar 10 12:18:36 PM PDT 24
Finished Mar 10 12:18:38 PM PDT 24
Peak memory 201300 kb
Host smart-41116fa9-738e-47ce-a7c1-29456866cd9a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052647398 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.1052647398
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.1573438790
Short name T803
Test name
Test status
Simulation time 536987560 ps
CPU time 0.83 seconds
Started Mar 10 12:26:49 PM PDT 24
Finished Mar 10 12:26:50 PM PDT 24
Peak memory 199792 kb
Host smart-f01d0f52-de8e-4556-830f-d1843559ebf1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573438790 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.1573438790
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.3313065200
Short name T855
Test name
Test status
Simulation time 342746172 ps
CPU time 1.03 seconds
Started Mar 10 12:24:31 PM PDT 24
Finished Mar 10 12:24:33 PM PDT 24
Peak memory 200808 kb
Host smart-11ece13c-ed3e-4d9b-9293-d57293842efc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313065200 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.3313065200
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.3007937766
Short name T863
Test name
Test status
Simulation time 2466350591 ps
CPU time 3.73 seconds
Started Mar 10 12:24:15 PM PDT 24
Finished Mar 10 12:24:19 PM PDT 24
Peak memory 199856 kb
Host smart-41803dca-0b0b-497b-b61d-59b8a5ba9585
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007937766 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_
ctrl_same_csr_outstanding.3007937766
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.4066500929
Short name T904
Test name
Test status
Simulation time 1037742301 ps
CPU time 2.68 seconds
Started Mar 10 12:27:06 PM PDT 24
Finished Mar 10 12:27:09 PM PDT 24
Peak memory 201240 kb
Host smart-8c6e3994-030e-4623-8dd8-90c96a859804
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066500929 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.4066500929
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.1544204665
Short name T814
Test name
Test status
Simulation time 4451022793 ps
CPU time 3.83 seconds
Started Mar 10 12:23:43 PM PDT 24
Finished Mar 10 12:23:49 PM PDT 24
Peak memory 199828 kb
Host smart-4c5051ef-c890-4e23-a0b1-62b9907c13a1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544204665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_i
ntg_err.1544204665
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.3613995437
Short name T95
Test name
Test status
Simulation time 399671312 ps
CPU time 1.7 seconds
Started Mar 10 12:22:19 PM PDT 24
Finished Mar 10 12:22:21 PM PDT 24
Peak memory 201176 kb
Host smart-c18705b4-bce8-4b4c-a93a-806b9aa79d6b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613995437 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.3613995437
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.2281613327
Short name T143
Test name
Test status
Simulation time 467585843 ps
CPU time 2.01 seconds
Started Mar 10 12:20:45 PM PDT 24
Finished Mar 10 12:20:48 PM PDT 24
Peak memory 200960 kb
Host smart-909256c7-5fa8-42b4-8d63-4c302a017e4e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281613327 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.2281613327
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.4223508354
Short name T894
Test name
Test status
Simulation time 334336377 ps
CPU time 0.87 seconds
Started Mar 10 12:23:23 PM PDT 24
Finished Mar 10 12:23:24 PM PDT 24
Peak memory 200552 kb
Host smart-619cfcaf-db49-4af6-aff1-4579e7a9ef0f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223508354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.4223508354
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.1986541096
Short name T890
Test name
Test status
Simulation time 2088725182 ps
CPU time 3.28 seconds
Started Mar 10 12:24:31 PM PDT 24
Finished Mar 10 12:24:34 PM PDT 24
Peak memory 200924 kb
Host smart-f5dfda79-8181-4390-82dc-04a3f5541626
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986541096 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_
ctrl_same_csr_outstanding.1986541096
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.205274776
Short name T818
Test name
Test status
Simulation time 508071596 ps
CPU time 2.75 seconds
Started Mar 10 12:23:09 PM PDT 24
Finished Mar 10 12:23:12 PM PDT 24
Peak memory 209356 kb
Host smart-6ed83ed5-ee6d-4400-a788-ed0ec4b2350b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205274776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.205274776
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.3100846399
Short name T889
Test name
Test status
Simulation time 8100132601 ps
CPU time 7.15 seconds
Started Mar 10 12:21:37 PM PDT 24
Finished Mar 10 12:21:44 PM PDT 24
Peak memory 201124 kb
Host smart-760549b9-a683-4bd3-b1c9-38c428c99ed2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100846399 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_i
ntg_err.3100846399
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.3937986164
Short name T819
Test name
Test status
Simulation time 439954960 ps
CPU time 1.86 seconds
Started Mar 10 12:20:06 PM PDT 24
Finished Mar 10 12:20:07 PM PDT 24
Peak memory 201024 kb
Host smart-81fcaa9b-748f-48be-9d80-9cafc42ea194
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937986164 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.3937986164
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.1031348892
Short name T151
Test name
Test status
Simulation time 449654096 ps
CPU time 1.04 seconds
Started Mar 10 12:21:39 PM PDT 24
Finished Mar 10 12:21:40 PM PDT 24
Peak memory 201088 kb
Host smart-9851856f-4ab4-43c9-9787-dea7f74fafb3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031348892 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.1031348892
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.3182468416
Short name T872
Test name
Test status
Simulation time 427603390 ps
CPU time 1.14 seconds
Started Mar 10 12:24:24 PM PDT 24
Finished Mar 10 12:24:26 PM PDT 24
Peak memory 200824 kb
Host smart-017a854e-aa32-42ad-b218-b8f15e2d8167
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182468416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.3182468416
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.2740887224
Short name T152
Test name
Test status
Simulation time 2185043782 ps
CPU time 9.75 seconds
Started Mar 10 12:24:11 PM PDT 24
Finished Mar 10 12:24:21 PM PDT 24
Peak memory 200948 kb
Host smart-c54c6de0-5c15-4fb7-a56e-08c6663be6a2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740887224 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_
ctrl_same_csr_outstanding.2740887224
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.2069074503
Short name T75
Test name
Test status
Simulation time 451448180 ps
CPU time 2.43 seconds
Started Mar 10 12:22:26 PM PDT 24
Finished Mar 10 12:22:29 PM PDT 24
Peak memory 201160 kb
Host smart-ab4526f7-4f2a-44e6-84b1-db5b5b97064c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069074503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.2069074503
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.2340619345
Short name T66
Test name
Test status
Simulation time 4767250936 ps
CPU time 12.36 seconds
Started Mar 10 12:23:39 PM PDT 24
Finished Mar 10 12:23:52 PM PDT 24
Peak memory 201132 kb
Host smart-4f695bcf-1028-47bf-b7b4-340262636439
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340619345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_i
ntg_err.2340619345
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.1869204741
Short name T838
Test name
Test status
Simulation time 398393774 ps
CPU time 1.65 seconds
Started Mar 10 12:21:49 PM PDT 24
Finished Mar 10 12:21:51 PM PDT 24
Peak memory 201176 kb
Host smart-74084d18-f952-496f-9624-a6e6b75fb1fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869204741 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.1869204741
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.2992700705
Short name T847
Test name
Test status
Simulation time 468560603 ps
CPU time 1.75 seconds
Started Mar 10 12:23:03 PM PDT 24
Finished Mar 10 12:23:05 PM PDT 24
Peak memory 200952 kb
Host smart-90d5ec81-a418-4b06-bdb6-d01f5fc7d5a4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992700705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.2992700705
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.2358215639
Short name T802
Test name
Test status
Simulation time 456889880 ps
CPU time 1.01 seconds
Started Mar 10 12:22:36 PM PDT 24
Finished Mar 10 12:22:38 PM PDT 24
Peak memory 199820 kb
Host smart-06d1576e-ce2b-4ab3-8050-2a59ca0d7db8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358215639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.2358215639
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.3453807551
Short name T848
Test name
Test status
Simulation time 2406769732 ps
CPU time 5.9 seconds
Started Mar 10 12:18:08 PM PDT 24
Finished Mar 10 12:18:15 PM PDT 24
Peak memory 201012 kb
Host smart-0f3001b5-6871-4532-b3ea-1b05e3010918
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453807551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_
ctrl_same_csr_outstanding.3453807551
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.2766803263
Short name T829
Test name
Test status
Simulation time 376846627 ps
CPU time 3.28 seconds
Started Mar 10 12:22:53 PM PDT 24
Finished Mar 10 12:22:57 PM PDT 24
Peak memory 201176 kb
Host smart-e83b8023-73c5-4994-9abd-334cdf30b702
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766803263 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.2766803263
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.1057730496
Short name T367
Test name
Test status
Simulation time 4418056367 ps
CPU time 6.85 seconds
Started Mar 10 12:24:11 PM PDT 24
Finished Mar 10 12:24:18 PM PDT 24
Peak memory 201080 kb
Host smart-ae113659-95a3-4ef3-900e-648dd9faeaba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057730496 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_i
ntg_err.1057730496
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.38296651
Short name T834
Test name
Test status
Simulation time 586502019 ps
CPU time 1.16 seconds
Started Mar 10 12:24:11 PM PDT 24
Finished Mar 10 12:24:12 PM PDT 24
Peak memory 200952 kb
Host smart-73f0b449-886a-4400-b968-f56eb87d69af
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38296651 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.38296651
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.2588103641
Short name T139
Test name
Test status
Simulation time 425741130 ps
CPU time 1.86 seconds
Started Mar 10 12:23:02 PM PDT 24
Finished Mar 10 12:23:04 PM PDT 24
Peak memory 200952 kb
Host smart-cc3fd166-9ebd-4071-a15b-92e8cc36af0c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588103641 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.2588103641
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.3872870626
Short name T859
Test name
Test status
Simulation time 542612044 ps
CPU time 1.06 seconds
Started Mar 10 12:18:18 PM PDT 24
Finished Mar 10 12:18:19 PM PDT 24
Peak memory 200788 kb
Host smart-bd5ec9bd-b682-40dc-8ed1-6b3040ecbe83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872870626 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.3872870626
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.2998170086
Short name T148
Test name
Test status
Simulation time 2662827615 ps
CPU time 6.71 seconds
Started Mar 10 12:24:24 PM PDT 24
Finished Mar 10 12:24:31 PM PDT 24
Peak memory 200980 kb
Host smart-411cbcea-9275-49c3-bee5-a0bef4f34e7d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998170086 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_
ctrl_same_csr_outstanding.2998170086
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.4037441359
Short name T368
Test name
Test status
Simulation time 8177314848 ps
CPU time 21.53 seconds
Started Mar 10 12:18:03 PM PDT 24
Finished Mar 10 12:18:25 PM PDT 24
Peak memory 201136 kb
Host smart-8821911d-b7d1-47e7-83f8-e8cfe1d005b9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037441359 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_i
ntg_err.4037441359
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.3560982748
Short name T799
Test name
Test status
Simulation time 587150491 ps
CPU time 1.44 seconds
Started Mar 10 12:23:55 PM PDT 24
Finished Mar 10 12:23:58 PM PDT 24
Peak memory 199548 kb
Host smart-f9a72b64-8af7-4e01-be74-8c72427a49fc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560982748 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.3560982748
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.1091871514
Short name T868
Test name
Test status
Simulation time 387827685 ps
CPU time 1.83 seconds
Started Mar 10 12:24:07 PM PDT 24
Finished Mar 10 12:24:09 PM PDT 24
Peak memory 200524 kb
Host smart-e29662db-0f7c-49a7-82d0-ee7230d96755
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091871514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.1091871514
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.1919706359
Short name T820
Test name
Test status
Simulation time 381807872 ps
CPU time 0.98 seconds
Started Mar 10 12:18:20 PM PDT 24
Finished Mar 10 12:18:21 PM PDT 24
Peak memory 200896 kb
Host smart-1849bffb-7ac4-4f31-af06-10b94522dbe0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919706359 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.1919706359
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.2670769709
Short name T907
Test name
Test status
Simulation time 2294518318 ps
CPU time 2.98 seconds
Started Mar 10 12:26:23 PM PDT 24
Finished Mar 10 12:26:26 PM PDT 24
Peak memory 199916 kb
Host smart-15b1f79e-b871-4494-94e1-a7855b03f626
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670769709 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_
ctrl_same_csr_outstanding.2670769709
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.2554520416
Short name T835
Test name
Test status
Simulation time 343799576 ps
CPU time 1.85 seconds
Started Mar 10 12:24:24 PM PDT 24
Finished Mar 10 12:24:27 PM PDT 24
Peak memory 200940 kb
Host smart-29d8cccb-48a7-4c66-af91-9565c63356f7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554520416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.2554520416
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.530399911
Short name T811
Test name
Test status
Simulation time 845561634 ps
CPU time 1.26 seconds
Started Mar 10 12:18:18 PM PDT 24
Finished Mar 10 12:18:19 PM PDT 24
Peak memory 209424 kb
Host smart-980e2c21-2d9e-4351-b809-5c765caedd6e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530399911 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.530399911
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.815802674
Short name T142
Test name
Test status
Simulation time 363397074 ps
CPU time 1.58 seconds
Started Mar 10 12:18:20 PM PDT 24
Finished Mar 10 12:18:22 PM PDT 24
Peak memory 200968 kb
Host smart-961d59da-0363-45c2-9662-cb0f130b970f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815802674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.815802674
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.235163203
Short name T800
Test name
Test status
Simulation time 403310753 ps
CPU time 1.58 seconds
Started Mar 10 12:24:24 PM PDT 24
Finished Mar 10 12:24:26 PM PDT 24
Peak memory 200852 kb
Host smart-228224eb-fdbf-4101-98cc-fe8a0bf67bed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235163203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.235163203
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.1289386640
Short name T884
Test name
Test status
Simulation time 2542601120 ps
CPU time 3.01 seconds
Started Mar 10 12:18:21 PM PDT 24
Finished Mar 10 12:18:24 PM PDT 24
Peak memory 201032 kb
Host smart-8618cfe3-8ccb-44ef-8949-91797755c807
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289386640 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_
ctrl_same_csr_outstanding.1289386640
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.1418252547
Short name T78
Test name
Test status
Simulation time 468000161 ps
CPU time 1.81 seconds
Started Mar 10 12:24:24 PM PDT 24
Finished Mar 10 12:24:26 PM PDT 24
Peak memory 201132 kb
Host smart-00a96665-538c-4fd4-ae27-0d00c594bf4c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418252547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.1418252547
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.1893305251
Short name T70
Test name
Test status
Simulation time 8370725489 ps
CPU time 6.97 seconds
Started Mar 10 12:18:18 PM PDT 24
Finished Mar 10 12:18:25 PM PDT 24
Peak memory 201212 kb
Host smart-2c3913c8-727d-4bcd-acce-973eda948ab4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893305251 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_i
ntg_err.1893305251
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.1049717053
Short name T809
Test name
Test status
Simulation time 464134279 ps
CPU time 1.05 seconds
Started Mar 10 12:27:45 PM PDT 24
Finished Mar 10 12:27:47 PM PDT 24
Peak memory 201044 kb
Host smart-831e0c5f-6403-424a-bf1c-79967768d839
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049717053 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.1049717053
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.1017155381
Short name T147
Test name
Test status
Simulation time 577018205 ps
CPU time 0.86 seconds
Started Mar 10 12:18:17 PM PDT 24
Finished Mar 10 12:18:18 PM PDT 24
Peak memory 200908 kb
Host smart-8a4507c8-664d-4261-a7fe-15062da72274
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017155381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.1017155381
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.2220433531
Short name T808
Test name
Test status
Simulation time 526866153 ps
CPU time 1.28 seconds
Started Mar 10 12:20:03 PM PDT 24
Finished Mar 10 12:20:04 PM PDT 24
Peak memory 200868 kb
Host smart-31290b3f-7a97-4fa4-9335-899250bbab5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220433531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.2220433531
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.1300193562
Short name T828
Test name
Test status
Simulation time 4566415157 ps
CPU time 15.9 seconds
Started Mar 10 12:20:03 PM PDT 24
Finished Mar 10 12:20:19 PM PDT 24
Peak memory 201204 kb
Host smart-46c3c28c-e486-43ee-a7b9-7d7f4f681f61
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300193562 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_
ctrl_same_csr_outstanding.1300193562
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.2190477306
Short name T882
Test name
Test status
Simulation time 556098454 ps
CPU time 3.3 seconds
Started Mar 10 12:24:27 PM PDT 24
Finished Mar 10 12:24:31 PM PDT 24
Peak memory 209308 kb
Host smart-5f9ebab5-fcc5-44db-bd7b-0a8684a64f9b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190477306 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.2190477306
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.2867676106
Short name T71
Test name
Test status
Simulation time 7990114165 ps
CPU time 21.62 seconds
Started Mar 10 12:27:37 PM PDT 24
Finished Mar 10 12:27:59 PM PDT 24
Peak memory 201176 kb
Host smart-c606cf45-f509-443f-8384-b7a946ea66d3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867676106 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_i
ntg_err.2867676106
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.2762419976
Short name T873
Test name
Test status
Simulation time 1000686857 ps
CPU time 2.74 seconds
Started Mar 10 12:33:47 PM PDT 24
Finished Mar 10 12:33:49 PM PDT 24
Peak memory 201196 kb
Host smart-20c21b2b-fe96-47bb-af66-973cd18f3954
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762419976 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alia
sing.2762419976
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.3386379667
Short name T63
Test name
Test status
Simulation time 30373001999 ps
CPU time 62.04 seconds
Started Mar 10 12:20:17 PM PDT 24
Finished Mar 10 12:21:20 PM PDT 24
Peak memory 201188 kb
Host smart-4dfc7449-26df-4eb8-9bce-6fd7898f6ca8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386379667 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_
bash.3386379667
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.1370161984
Short name T842
Test name
Test status
Simulation time 998637435 ps
CPU time 2.42 seconds
Started Mar 10 12:24:45 PM PDT 24
Finished Mar 10 12:24:47 PM PDT 24
Peak memory 200936 kb
Host smart-1c5a5656-c405-4485-8d4f-ebce2d545b34
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370161984 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_r
eset.1370161984
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.2653002544
Short name T901
Test name
Test status
Simulation time 598422510 ps
CPU time 1.47 seconds
Started Mar 10 12:18:48 PM PDT 24
Finished Mar 10 12:18:50 PM PDT 24
Peak memory 201304 kb
Host smart-e57121ca-255b-44b6-aa2c-4d668e4aadb9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653002544 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.2653002544
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.1522808107
Short name T29
Test name
Test status
Simulation time 451326313 ps
CPU time 1.07 seconds
Started Mar 10 12:20:59 PM PDT 24
Finished Mar 10 12:21:01 PM PDT 24
Peak memory 200968 kb
Host smart-a85bcc4d-e996-48a2-a4f7-03dc72a01408
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522808107 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.1522808107
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.4058567912
Short name T831
Test name
Test status
Simulation time 375512940 ps
CPU time 0.88 seconds
Started Mar 10 12:24:45 PM PDT 24
Finished Mar 10 12:24:46 PM PDT 24
Peak memory 200852 kb
Host smart-4dcf218b-e02a-46fe-85ab-9b33a3471247
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058567912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.4058567912
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.635235292
Short name T874
Test name
Test status
Simulation time 2178777692 ps
CPU time 2.79 seconds
Started Mar 10 12:20:03 PM PDT 24
Finished Mar 10 12:20:05 PM PDT 24
Peak memory 200300 kb
Host smart-13f72d33-4844-4456-a99d-fc4f65e3ce82
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635235292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ct
rl_same_csr_outstanding.635235292
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.2784967215
Short name T885
Test name
Test status
Simulation time 516420932 ps
CPU time 3.64 seconds
Started Mar 10 12:33:57 PM PDT 24
Finished Mar 10 12:34:01 PM PDT 24
Peak memory 210388 kb
Host smart-677cd11c-bd31-4d04-98b2-5feb3339957d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784967215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.2784967215
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.3330485750
Short name T846
Test name
Test status
Simulation time 4725088481 ps
CPU time 7.38 seconds
Started Mar 10 12:33:55 PM PDT 24
Finished Mar 10 12:34:02 PM PDT 24
Peak memory 201156 kb
Host smart-2d7fc282-a13e-4051-9baf-7fa011c269a6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330485750 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_in
tg_err.3330485750
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.462594344
Short name T886
Test name
Test status
Simulation time 506940030 ps
CPU time 0.92 seconds
Started Mar 10 12:18:15 PM PDT 24
Finished Mar 10 12:18:16 PM PDT 24
Peak memory 200876 kb
Host smart-2cc570d9-b3d2-4c2e-8dd9-a215b105508d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462594344 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.462594344
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.1409654253
Short name T792
Test name
Test status
Simulation time 338719464 ps
CPU time 0.83 seconds
Started Mar 10 12:18:22 PM PDT 24
Finished Mar 10 12:18:23 PM PDT 24
Peak memory 200832 kb
Host smart-25df3cd3-0b3f-4846-8d62-a900bbd2f9dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409654253 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.1409654253
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.3436251016
Short name T861
Test name
Test status
Simulation time 463283352 ps
CPU time 1.73 seconds
Started Mar 10 12:18:55 PM PDT 24
Finished Mar 10 12:18:57 PM PDT 24
Peak memory 200880 kb
Host smart-94b69230-b696-46a3-ac80-93c17cd7541b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436251016 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.3436251016
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.1479322376
Short name T903
Test name
Test status
Simulation time 401606947 ps
CPU time 1.47 seconds
Started Mar 10 12:29:09 PM PDT 24
Finished Mar 10 12:29:11 PM PDT 24
Peak memory 200600 kb
Host smart-bba9cd6f-534a-4286-813e-652f0aab7410
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479322376 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.1479322376
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.1415211841
Short name T854
Test name
Test status
Simulation time 453891460 ps
CPU time 1.73 seconds
Started Mar 10 12:29:21 PM PDT 24
Finished Mar 10 12:29:23 PM PDT 24
Peak memory 200876 kb
Host smart-74e084a4-5a8f-48d9-9c91-f3ad5d02fe9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415211841 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.1415211841
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.4138935442
Short name T896
Test name
Test status
Simulation time 421599394 ps
CPU time 1.68 seconds
Started Mar 10 12:29:21 PM PDT 24
Finished Mar 10 12:29:23 PM PDT 24
Peak memory 200872 kb
Host smart-d2dad812-0b88-444b-b568-481f49fef6d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138935442 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.4138935442
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.1858803245
Short name T867
Test name
Test status
Simulation time 451487022 ps
CPU time 1.57 seconds
Started Mar 10 12:21:49 PM PDT 24
Finished Mar 10 12:21:51 PM PDT 24
Peak memory 201008 kb
Host smart-8f476d6c-f67f-4cf8-b7fa-ae67e023269d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858803245 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.1858803245
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.2194101052
Short name T862
Test name
Test status
Simulation time 437903097 ps
CPU time 1.78 seconds
Started Mar 10 12:18:33 PM PDT 24
Finished Mar 10 12:18:35 PM PDT 24
Peak memory 200868 kb
Host smart-a076078b-2c3b-4ea9-8198-55294ded6eba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194101052 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.2194101052
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.1557364942
Short name T815
Test name
Test status
Simulation time 511374429 ps
CPU time 0.92 seconds
Started Mar 10 12:22:53 PM PDT 24
Finished Mar 10 12:22:54 PM PDT 24
Peak memory 200844 kb
Host smart-91d44046-b355-4751-bc34-fd0833055ee0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557364942 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.1557364942
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.1259590275
Short name T870
Test name
Test status
Simulation time 572203352 ps
CPU time 0.74 seconds
Started Mar 10 12:23:01 PM PDT 24
Finished Mar 10 12:23:02 PM PDT 24
Peak memory 200904 kb
Host smart-e37bfa66-58be-4769-a766-bcb09c962a1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259590275 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.1259590275
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.798185815
Short name T140
Test name
Test status
Simulation time 1131385984 ps
CPU time 5.87 seconds
Started Mar 10 12:33:42 PM PDT 24
Finished Mar 10 12:33:49 PM PDT 24
Peak memory 201368 kb
Host smart-f4556149-17b5-4316-b645-54ab70040766
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798185815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alias
ing.798185815
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.3751033350
Short name T899
Test name
Test status
Simulation time 52325556296 ps
CPU time 121.12 seconds
Started Mar 10 12:29:32 PM PDT 24
Finished Mar 10 12:31:34 PM PDT 24
Peak memory 201288 kb
Host smart-6a2eacd0-83b5-4f72-9b19-8ca53066046a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751033350 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_
bash.3751033350
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.4286145637
Short name T856
Test name
Test status
Simulation time 695879050 ps
CPU time 1.11 seconds
Started Mar 10 12:24:45 PM PDT 24
Finished Mar 10 12:24:46 PM PDT 24
Peak memory 200936 kb
Host smart-5b3aae75-b233-43d6-aebd-c7fdd9534b3a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286145637 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_r
eset.4286145637
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.3584533784
Short name T39
Test name
Test status
Simulation time 520499285 ps
CPU time 2.02 seconds
Started Mar 10 12:33:55 PM PDT 24
Finished Mar 10 12:33:57 PM PDT 24
Peak memory 200976 kb
Host smart-c4d8779a-7256-41d5-85f8-518a8dcbfba3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584533784 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.3584533784
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.3130442512
Short name T871
Test name
Test status
Simulation time 389680897 ps
CPU time 1.19 seconds
Started Mar 10 12:20:03 PM PDT 24
Finished Mar 10 12:20:04 PM PDT 24
Peak memory 200808 kb
Host smart-8b63e8c3-1155-40a2-906a-137c741a33de
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130442512 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.3130442512
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.2865019405
Short name T881
Test name
Test status
Simulation time 546332426 ps
CPU time 0.94 seconds
Started Mar 10 12:19:26 PM PDT 24
Finished Mar 10 12:19:29 PM PDT 24
Peak memory 200880 kb
Host smart-4cd49bef-9403-44f9-a23c-c9289076b7fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865019405 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.2865019405
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.4143208788
Short name T823
Test name
Test status
Simulation time 4653704224 ps
CPU time 4.15 seconds
Started Mar 10 12:21:22 PM PDT 24
Finished Mar 10 12:21:27 PM PDT 24
Peak memory 201136 kb
Host smart-5f80abb1-f50c-468f-94e6-37892b9b6d6c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143208788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_c
trl_same_csr_outstanding.4143208788
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.1291313795
Short name T79
Test name
Test status
Simulation time 582853632 ps
CPU time 2.92 seconds
Started Mar 10 12:21:33 PM PDT 24
Finished Mar 10 12:21:36 PM PDT 24
Peak memory 201168 kb
Host smart-9837e8d4-423b-40ea-85ae-9a26f0081f69
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291313795 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.1291313795
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.1980773254
Short name T366
Test name
Test status
Simulation time 4075906009 ps
CPU time 11.34 seconds
Started Mar 10 12:20:42 PM PDT 24
Finished Mar 10 12:20:54 PM PDT 24
Peak memory 201216 kb
Host smart-197633cc-f75b-4309-8e3e-61249ac8f7b6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980773254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_in
tg_err.1980773254
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.1970808844
Short name T843
Test name
Test status
Simulation time 327895696 ps
CPU time 0.93 seconds
Started Mar 10 12:18:37 PM PDT 24
Finished Mar 10 12:18:38 PM PDT 24
Peak memory 201332 kb
Host smart-30ec9705-85d8-4f8e-846e-3d22edf25f5e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970808844 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.1970808844
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.1639384711
Short name T812
Test name
Test status
Simulation time 328548042 ps
CPU time 1.02 seconds
Started Mar 10 12:23:57 PM PDT 24
Finished Mar 10 12:23:59 PM PDT 24
Peak memory 200492 kb
Host smart-eddfc217-c9eb-4e5b-8452-e8f3c90245ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639384711 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.1639384711
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.2967063552
Short name T796
Test name
Test status
Simulation time 510422630 ps
CPU time 1.84 seconds
Started Mar 10 12:23:57 PM PDT 24
Finished Mar 10 12:23:59 PM PDT 24
Peak memory 200360 kb
Host smart-9e338101-ce8a-433b-b61a-51a85f55b287
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967063552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.2967063552
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.2425036356
Short name T909
Test name
Test status
Simulation time 430155751 ps
CPU time 1.19 seconds
Started Mar 10 12:19:06 PM PDT 24
Finished Mar 10 12:19:07 PM PDT 24
Peak memory 200888 kb
Host smart-bd231c6b-4ca2-469d-bf0a-205daf7e181a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425036356 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.2425036356
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.2127797381
Short name T839
Test name
Test status
Simulation time 497216758 ps
CPU time 1.22 seconds
Started Mar 10 12:18:34 PM PDT 24
Finished Mar 10 12:18:36 PM PDT 24
Peak memory 200840 kb
Host smart-75292ca0-1843-42ea-87af-62c6809f0bda
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127797381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.2127797381
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.1729346619
Short name T880
Test name
Test status
Simulation time 417992300 ps
CPU time 1.15 seconds
Started Mar 10 12:18:40 PM PDT 24
Finished Mar 10 12:18:41 PM PDT 24
Peak memory 201172 kb
Host smart-cb73571e-1cff-4cfc-92cb-a7251451fd46
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729346619 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.1729346619
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.1957373605
Short name T801
Test name
Test status
Simulation time 552259045 ps
CPU time 0.93 seconds
Started Mar 10 12:22:57 PM PDT 24
Finished Mar 10 12:22:58 PM PDT 24
Peak memory 200860 kb
Host smart-ed1b6cb1-d89c-4b32-b552-33a8e046422a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957373605 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.1957373605
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.2577215823
Short name T806
Test name
Test status
Simulation time 555423072 ps
CPU time 0.9 seconds
Started Mar 10 12:19:52 PM PDT 24
Finished Mar 10 12:19:53 PM PDT 24
Peak memory 200840 kb
Host smart-80f5b7ee-2fbe-40d1-b2db-16f2f13be127
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577215823 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.2577215823
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.2025705821
Short name T795
Test name
Test status
Simulation time 373070408 ps
CPU time 1.54 seconds
Started Mar 10 12:19:14 PM PDT 24
Finished Mar 10 12:19:16 PM PDT 24
Peak memory 200852 kb
Host smart-4c81caa4-81ac-46ad-9a98-0175311cf5db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025705821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.2025705821
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.3687113318
Short name T857
Test name
Test status
Simulation time 409583896 ps
CPU time 1.08 seconds
Started Mar 10 12:30:24 PM PDT 24
Finished Mar 10 12:30:25 PM PDT 24
Peak memory 200900 kb
Host smart-686a772e-3b39-4def-878f-5de5af6bc997
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687113318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.3687113318
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.2155496809
Short name T813
Test name
Test status
Simulation time 1153147307 ps
CPU time 3.39 seconds
Started Mar 10 12:23:01 PM PDT 24
Finished Mar 10 12:23:05 PM PDT 24
Peak memory 199944 kb
Host smart-1d7f40ef-6e8a-4169-89da-2c0c0bd0fea6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155496809 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alia
sing.2155496809
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.3369767764
Short name T64
Test name
Test status
Simulation time 52136908681 ps
CPU time 111.7 seconds
Started Mar 10 12:19:16 PM PDT 24
Finished Mar 10 12:21:07 PM PDT 24
Peak memory 201168 kb
Host smart-64ef9ba8-bcaf-4049-848a-4e0f02d8795d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369767764 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_
bash.3369767764
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.993943108
Short name T141
Test name
Test status
Simulation time 828609352 ps
CPU time 2.57 seconds
Started Mar 10 12:20:50 PM PDT 24
Finished Mar 10 12:20:54 PM PDT 24
Peak memory 200952 kb
Host smart-9643d57f-a74d-4d63-8f5e-715045c5c4ff
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993943108 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_re
set.993943108
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.2545626265
Short name T97
Test name
Test status
Simulation time 477273917 ps
CPU time 1.3 seconds
Started Mar 10 12:20:30 PM PDT 24
Finished Mar 10 12:20:32 PM PDT 24
Peak memory 201028 kb
Host smart-936e87b7-2f6e-4c43-9207-643a19495a0e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545626265 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.2545626265
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.1280033640
Short name T144
Test name
Test status
Simulation time 580661582 ps
CPU time 1.12 seconds
Started Mar 10 12:20:10 PM PDT 24
Finished Mar 10 12:20:11 PM PDT 24
Peak memory 201416 kb
Host smart-71355481-d2bd-4ad3-a5a9-8efa4bf063ef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280033640 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.1280033640
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.3062240572
Short name T804
Test name
Test status
Simulation time 318626895 ps
CPU time 0.79 seconds
Started Mar 10 12:23:18 PM PDT 24
Finished Mar 10 12:23:19 PM PDT 24
Peak memory 200800 kb
Host smart-1b32fbb1-a617-49d8-bab1-f6e073cd44b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062240572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.3062240572
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.587119345
Short name T150
Test name
Test status
Simulation time 2097814962 ps
CPU time 2.15 seconds
Started Mar 10 12:23:01 PM PDT 24
Finished Mar 10 12:23:04 PM PDT 24
Peak memory 199748 kb
Host smart-6c3160c2-94f2-478e-9387-31a14ed2ebd0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587119345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ct
rl_same_csr_outstanding.587119345
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.465341308
Short name T878
Test name
Test status
Simulation time 341738645 ps
CPU time 2.23 seconds
Started Mar 10 12:19:48 PM PDT 24
Finished Mar 10 12:19:50 PM PDT 24
Peak memory 201164 kb
Host smart-43a01d72-1bfe-4f0d-8869-ee3c17489158
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465341308 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.465341308
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.3406619453
Short name T911
Test name
Test status
Simulation time 8473102366 ps
CPU time 12.73 seconds
Started Mar 10 12:24:57 PM PDT 24
Finished Mar 10 12:25:10 PM PDT 24
Peak memory 201160 kb
Host smart-26306d07-15ff-49b7-8b0d-88619d997006
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406619453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_in
tg_err.3406619453
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.2072643261
Short name T853
Test name
Test status
Simulation time 344031927 ps
CPU time 0.88 seconds
Started Mar 10 12:19:09 PM PDT 24
Finished Mar 10 12:19:11 PM PDT 24
Peak memory 201148 kb
Host smart-977116c1-e9e6-426c-8ff4-888f636555d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072643261 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.2072643261
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.640642048
Short name T821
Test name
Test status
Simulation time 422685579 ps
CPU time 1.65 seconds
Started Mar 10 12:22:45 PM PDT 24
Finished Mar 10 12:22:48 PM PDT 24
Peak memory 200032 kb
Host smart-da7aaaae-1268-47fd-9e76-7d30715efe35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640642048 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.640642048
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.434086553
Short name T807
Test name
Test status
Simulation time 436958259 ps
CPU time 0.82 seconds
Started Mar 10 12:23:59 PM PDT 24
Finished Mar 10 12:24:00 PM PDT 24
Peak memory 200628 kb
Host smart-75e4441b-1582-4c01-9f86-f7e3cf02e156
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434086553 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.434086553
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.156726445
Short name T793
Test name
Test status
Simulation time 306058330 ps
CPU time 0.88 seconds
Started Mar 10 12:20:08 PM PDT 24
Finished Mar 10 12:20:08 PM PDT 24
Peak memory 201120 kb
Host smart-e5ee8026-fa95-4f09-a625-d79febdd0369
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156726445 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.156726445
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.2699954719
Short name T906
Test name
Test status
Simulation time 355222793 ps
CPU time 0.91 seconds
Started Mar 10 12:23:59 PM PDT 24
Finished Mar 10 12:24:00 PM PDT 24
Peak memory 199436 kb
Host smart-8e1490cc-bbd2-4f9e-90f7-6b2ba4ca8274
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699954719 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.2699954719
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.379459452
Short name T879
Test name
Test status
Simulation time 318814957 ps
CPU time 1.3 seconds
Started Mar 10 12:19:10 PM PDT 24
Finished Mar 10 12:19:12 PM PDT 24
Peak memory 200876 kb
Host smart-db9886d0-3c84-44c3-9311-286b74747bdd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379459452 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.379459452
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.179809709
Short name T797
Test name
Test status
Simulation time 443202951 ps
CPU time 1.12 seconds
Started Mar 10 12:23:59 PM PDT 24
Finished Mar 10 12:24:00 PM PDT 24
Peak memory 200492 kb
Host smart-26b6da27-8cb2-442b-b0e8-5e6757f7da0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179809709 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.179809709
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.386204031
Short name T876
Test name
Test status
Simulation time 439896505 ps
CPU time 0.86 seconds
Started Mar 10 12:19:21 PM PDT 24
Finished Mar 10 12:19:23 PM PDT 24
Peak memory 200848 kb
Host smart-b31276e5-ddc3-4016-9de8-759c2f0e30b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386204031 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.386204031
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.359633148
Short name T791
Test name
Test status
Simulation time 482196131 ps
CPU time 1.27 seconds
Started Mar 10 12:19:10 PM PDT 24
Finished Mar 10 12:19:12 PM PDT 24
Peak memory 200876 kb
Host smart-2c67a633-326f-4b0f-a133-e339862d5370
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359633148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.359633148
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.3531280265
Short name T851
Test name
Test status
Simulation time 516116420 ps
CPU time 1.85 seconds
Started Mar 10 12:23:59 PM PDT 24
Finished Mar 10 12:24:01 PM PDT 24
Peak memory 199260 kb
Host smart-f807e355-d052-4674-9063-68c7475fefb7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531280265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.3531280265
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.3933787553
Short name T827
Test name
Test status
Simulation time 576270383 ps
CPU time 1.21 seconds
Started Mar 10 12:18:18 PM PDT 24
Finished Mar 10 12:18:20 PM PDT 24
Peak memory 201056 kb
Host smart-41ed1333-dd08-4ee1-a039-8fe32afa4852
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933787553 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.3933787553
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.2560139979
Short name T136
Test name
Test status
Simulation time 460130805 ps
CPU time 1.75 seconds
Started Mar 10 12:24:12 PM PDT 24
Finished Mar 10 12:24:15 PM PDT 24
Peak memory 200172 kb
Host smart-57e73f7d-30b2-400a-a25c-16a2fff95b68
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560139979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.2560139979
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.3297285634
Short name T891
Test name
Test status
Simulation time 374515859 ps
CPU time 1.47 seconds
Started Mar 10 12:33:06 PM PDT 24
Finished Mar 10 12:33:08 PM PDT 24
Peak memory 200808 kb
Host smart-c359c797-feca-4775-82ef-2b25b2bb29ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297285634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.3297285634
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.107977338
Short name T836
Test name
Test status
Simulation time 2131404536 ps
CPU time 4.37 seconds
Started Mar 10 12:19:52 PM PDT 24
Finished Mar 10 12:19:57 PM PDT 24
Peak memory 200984 kb
Host smart-6e9c94a0-41fe-4b92-92ee-e275683e3291
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107977338 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ct
rl_same_csr_outstanding.107977338
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.761320060
Short name T866
Test name
Test status
Simulation time 594870950 ps
CPU time 2.04 seconds
Started Mar 10 12:23:18 PM PDT 24
Finished Mar 10 12:23:21 PM PDT 24
Peak memory 201120 kb
Host smart-aea1354d-a265-44a7-8ee1-da24fd7dd660
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761320060 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.761320060
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.3663645220
Short name T910
Test name
Test status
Simulation time 4111301944 ps
CPU time 10.05 seconds
Started Mar 10 12:24:01 PM PDT 24
Finished Mar 10 12:24:11 PM PDT 24
Peak memory 201168 kb
Host smart-b661d1e4-e2fa-4a18-977a-106135d9e0dd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663645220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_in
tg_err.3663645220
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.2289259911
Short name T883
Test name
Test status
Simulation time 585366585 ps
CPU time 1.53 seconds
Started Mar 10 12:22:08 PM PDT 24
Finished Mar 10 12:22:10 PM PDT 24
Peak memory 201028 kb
Host smart-0640e2dd-602a-4ec8-9fbd-5b880c57e4e0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289259911 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.2289259911
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.3588297586
Short name T895
Test name
Test status
Simulation time 574056163 ps
CPU time 1.09 seconds
Started Mar 10 12:24:01 PM PDT 24
Finished Mar 10 12:24:02 PM PDT 24
Peak memory 200940 kb
Host smart-4488a5f0-cba7-4382-a6a8-2108c1b6497b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588297586 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.3588297586
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.3572442826
Short name T817
Test name
Test status
Simulation time 397151576 ps
CPU time 1.28 seconds
Started Mar 10 12:24:01 PM PDT 24
Finished Mar 10 12:24:02 PM PDT 24
Peak memory 200852 kb
Host smart-c0908d6f-dbc8-475e-8248-452bcfd66972
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572442826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.3572442826
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.1607083833
Short name T824
Test name
Test status
Simulation time 2584405964 ps
CPU time 1.91 seconds
Started Mar 10 12:27:01 PM PDT 24
Finished Mar 10 12:27:04 PM PDT 24
Peak memory 200072 kb
Host smart-46f8f8d3-80a2-42e5-aa0f-f45619985381
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607083833 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_c
trl_same_csr_outstanding.1607083833
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.583578516
Short name T900
Test name
Test status
Simulation time 550722951 ps
CPU time 2.16 seconds
Started Mar 10 12:21:18 PM PDT 24
Finished Mar 10 12:21:20 PM PDT 24
Peak memory 201184 kb
Host smart-738d78d0-0b7e-496e-8cf7-8970e86fd619
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583578516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.583578516
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.1317432539
Short name T810
Test name
Test status
Simulation time 9137563821 ps
CPU time 17.76 seconds
Started Mar 10 12:24:10 PM PDT 24
Finished Mar 10 12:24:28 PM PDT 24
Peak memory 201172 kb
Host smart-4e063475-fae3-458e-a1a2-668cc0c6b7d7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317432539 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_in
tg_err.1317432539
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.4074085134
Short name T887
Test name
Test status
Simulation time 590181934 ps
CPU time 0.95 seconds
Started Mar 10 12:27:21 PM PDT 24
Finished Mar 10 12:27:23 PM PDT 24
Peak memory 200864 kb
Host smart-1913e9b3-2ca2-4a94-905e-fccead2e54e2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074085134 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.4074085134
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.1323569097
Short name T864
Test name
Test status
Simulation time 534166492 ps
CPU time 2.07 seconds
Started Mar 10 12:23:39 PM PDT 24
Finished Mar 10 12:23:42 PM PDT 24
Peak memory 200928 kb
Host smart-191f3575-332f-4fe0-b502-98cce8ed4dd4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323569097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.1323569097
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.3350661254
Short name T912
Test name
Test status
Simulation time 340987824 ps
CPU time 1.38 seconds
Started Mar 10 12:27:21 PM PDT 24
Finished Mar 10 12:27:23 PM PDT 24
Peak memory 200640 kb
Host smart-a5b35627-a0e4-497e-88fb-cc9040cf0cd5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350661254 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.3350661254
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.3495836402
Short name T826
Test name
Test status
Simulation time 2417134057 ps
CPU time 5.38 seconds
Started Mar 10 12:24:32 PM PDT 24
Finished Mar 10 12:24:37 PM PDT 24
Peak memory 200968 kb
Host smart-d898cee7-d4b3-4093-87b6-2356f4c12b3c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495836402 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_c
trl_same_csr_outstanding.3495836402
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.3249752269
Short name T830
Test name
Test status
Simulation time 367202748 ps
CPU time 2.53 seconds
Started Mar 10 12:24:10 PM PDT 24
Finished Mar 10 12:24:13 PM PDT 24
Peak memory 201148 kb
Host smart-ea1cd41e-6634-424a-94b9-3e892ae4c3e1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249752269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.3249752269
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.3054600348
Short name T81
Test name
Test status
Simulation time 8861758709 ps
CPU time 25.8 seconds
Started Mar 10 12:23:54 PM PDT 24
Finished Mar 10 12:24:20 PM PDT 24
Peak memory 200776 kb
Host smart-3adbdf20-aaae-4c84-a9c2-9f752a19b228
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054600348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_in
tg_err.3054600348
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.2980708564
Short name T816
Test name
Test status
Simulation time 635585175 ps
CPU time 1.4 seconds
Started Mar 10 12:26:49 PM PDT 24
Finished Mar 10 12:26:51 PM PDT 24
Peak memory 208108 kb
Host smart-a41855b2-0f57-482c-9066-30ffa3d029ff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980708564 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.2980708564
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.3996676988
Short name T869
Test name
Test status
Simulation time 553088697 ps
CPU time 0.74 seconds
Started Mar 10 12:23:22 PM PDT 24
Finished Mar 10 12:23:23 PM PDT 24
Peak memory 199820 kb
Host smart-9917f9a1-5b35-44a1-9091-43fcc796befd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996676988 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.3996676988
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.1292436668
Short name T902
Test name
Test status
Simulation time 420249986 ps
CPU time 1.59 seconds
Started Mar 10 12:27:21 PM PDT 24
Finished Mar 10 12:27:24 PM PDT 24
Peak memory 200836 kb
Host smart-0b438f1b-9872-4131-9dd3-412c60982f5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292436668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.1292436668
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.537952048
Short name T858
Test name
Test status
Simulation time 2129379358 ps
CPU time 5.57 seconds
Started Mar 10 12:24:31 PM PDT 24
Finished Mar 10 12:24:36 PM PDT 24
Peak memory 200920 kb
Host smart-0ad8f2c9-3316-405c-a788-d541203cdf2e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537952048 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ct
rl_same_csr_outstanding.537952048
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.1830190316
Short name T833
Test name
Test status
Simulation time 511946908 ps
CPU time 3.09 seconds
Started Mar 10 12:23:43 PM PDT 24
Finished Mar 10 12:23:48 PM PDT 24
Peak memory 208304 kb
Host smart-fab1f259-b151-42b3-9211-a67d07ec5e09
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830190316 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.1830190316
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.36743155
Short name T65
Test name
Test status
Simulation time 8570323906 ps
CPU time 12.21 seconds
Started Mar 10 12:27:07 PM PDT 24
Finished Mar 10 12:27:19 PM PDT 24
Peak memory 201176 kb
Host smart-583dde6e-c5f3-4526-8446-dccf33f4e0cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36743155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_intg
_err.36743155
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.130796705
Short name T860
Test name
Test status
Simulation time 654284320 ps
CPU time 1.15 seconds
Started Mar 10 12:19:00 PM PDT 24
Finished Mar 10 12:19:02 PM PDT 24
Peak memory 201036 kb
Host smart-294c8e3a-0921-488e-ab30-73cafb4de142
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130796705 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.130796705
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.4153804968
Short name T849
Test name
Test status
Simulation time 470780776 ps
CPU time 0.93 seconds
Started Mar 10 12:21:52 PM PDT 24
Finished Mar 10 12:21:54 PM PDT 24
Peak memory 200964 kb
Host smart-d5fadf47-6a42-456a-be91-000fcc6e10ad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153804968 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.4153804968
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.4185514767
Short name T794
Test name
Test status
Simulation time 513671383 ps
CPU time 0.77 seconds
Started Mar 10 12:27:08 PM PDT 24
Finished Mar 10 12:27:09 PM PDT 24
Peak memory 200880 kb
Host smart-ad8e72ab-cf26-4f28-9e0e-36ed2a9ef4a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185514767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.4185514767
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.3673220117
Short name T837
Test name
Test status
Simulation time 2333911395 ps
CPU time 2.72 seconds
Started Mar 10 12:27:07 PM PDT 24
Finished Mar 10 12:27:10 PM PDT 24
Peak memory 201032 kb
Host smart-3a630d6b-1873-4f9e-a7d1-18db421dfc96
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673220117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_c
trl_same_csr_outstanding.3673220117
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.3420638306
Short name T875
Test name
Test status
Simulation time 460370521 ps
CPU time 2.64 seconds
Started Mar 10 12:24:01 PM PDT 24
Finished Mar 10 12:24:04 PM PDT 24
Peak memory 201152 kb
Host smart-60fa036b-0376-4cc8-8feb-b940b68b4f48
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420638306 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.3420638306
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.3748422158
Short name T850
Test name
Test status
Simulation time 4411587700 ps
CPU time 4.17 seconds
Started Mar 10 12:20:38 PM PDT 24
Finished Mar 10 12:20:42 PM PDT 24
Peak memory 201220 kb
Host smart-cde2ce8a-c4ec-4946-83d9-9c89886d33d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748422158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_in
tg_err.3748422158
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.947649761
Short name T392
Test name
Test status
Simulation time 352329313 ps
CPU time 0.77 seconds
Started Mar 10 12:28:51 PM PDT 24
Finished Mar 10 12:28:52 PM PDT 24
Peak memory 201216 kb
Host smart-0fd0ddf8-1a04-416f-950d-123be13cde19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947649761 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.947649761
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.4270531085
Short name T666
Test name
Test status
Simulation time 524583512585 ps
CPU time 394.6 seconds
Started Mar 10 12:28:37 PM PDT 24
Finished Mar 10 12:35:12 PM PDT 24
Peak memory 201508 kb
Host smart-2c4c4706-b469-4f80-a1ff-1c69020852d9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270531085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gati
ng.4270531085
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.2361469399
Short name T444
Test name
Test status
Simulation time 335320749070 ps
CPU time 827.72 seconds
Started Mar 10 12:28:40 PM PDT 24
Finished Mar 10 12:42:29 PM PDT 24
Peak memory 201476 kb
Host smart-d03b32af-b69d-4531-9537-d627f2751a3a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361469399 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrup
t_fixed.2361469399
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.2440407852
Short name T706
Test name
Test status
Simulation time 321049814794 ps
CPU time 144.24 seconds
Started Mar 10 12:28:41 PM PDT 24
Finished Mar 10 12:31:05 PM PDT 24
Peak memory 201468 kb
Host smart-3c689494-4515-4112-bcc8-ea736b2437ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440407852 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.2440407852
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.247669133
Short name T768
Test name
Test status
Simulation time 333797694423 ps
CPU time 816.98 seconds
Started Mar 10 12:28:41 PM PDT 24
Finished Mar 10 12:42:19 PM PDT 24
Peak memory 201336 kb
Host smart-c6603c60-7bdd-4bde-801a-e99040638ad8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=247669133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixed
.247669133
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.4150549398
Short name T259
Test name
Test status
Simulation time 186080988675 ps
CPU time 196.27 seconds
Started Mar 10 12:28:43 PM PDT 24
Finished Mar 10 12:31:59 PM PDT 24
Peak memory 201368 kb
Host smart-aab47fb7-1ce3-4025-8336-9afa7238df71
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150549398 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_
wakeup.4150549398
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.4187884595
Short name T634
Test name
Test status
Simulation time 399037870953 ps
CPU time 797.79 seconds
Started Mar 10 12:28:42 PM PDT 24
Finished Mar 10 12:42:00 PM PDT 24
Peak memory 201408 kb
Host smart-f2893b7d-4aee-49a9-a68f-66bbfcc03d83
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187884595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
adc_ctrl_filters_wakeup_fixed.4187884595
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.2279069581
Short name T622
Test name
Test status
Simulation time 138821870212 ps
CPU time 548.02 seconds
Started Mar 10 12:28:47 PM PDT 24
Finished Mar 10 12:37:55 PM PDT 24
Peak memory 201648 kb
Host smart-236cac29-9667-4d9f-868d-5dd6a3b80f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279069581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.2279069581
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.3503604691
Short name T499
Test name
Test status
Simulation time 31811860037 ps
CPU time 38.92 seconds
Started Mar 10 12:28:54 PM PDT 24
Finished Mar 10 12:29:33 PM PDT 24
Peak memory 201316 kb
Host smart-c97d5929-d5b9-4ffe-822f-18889d25ddc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503604691 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.3503604691
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.3210079916
Short name T474
Test name
Test status
Simulation time 3889616960 ps
CPU time 10.79 seconds
Started Mar 10 12:28:58 PM PDT 24
Finished Mar 10 12:29:09 PM PDT 24
Peak memory 201240 kb
Host smart-29d08a1e-b757-4bd3-abce-e5181e28d7dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210079916 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.3210079916
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.1224516022
Short name T113
Test name
Test status
Simulation time 6105854841 ps
CPU time 15.05 seconds
Started Mar 10 12:28:38 PM PDT 24
Finished Mar 10 12:28:53 PM PDT 24
Peak memory 201432 kb
Host smart-bdb73e57-6c6d-48d1-8cba-451685660a8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224516022 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.1224516022
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.2366810235
Short name T198
Test name
Test status
Simulation time 189946995863 ps
CPU time 452.78 seconds
Started Mar 10 12:28:50 PM PDT 24
Finished Mar 10 12:36:23 PM PDT 24
Peak memory 201388 kb
Host smart-e7be8a8c-525a-4138-b13c-260f269557e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366810235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.
2366810235
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.1440748136
Short name T311
Test name
Test status
Simulation time 26726971699 ps
CPU time 32.05 seconds
Started Mar 10 12:28:54 PM PDT 24
Finished Mar 10 12:29:26 PM PDT 24
Peak memory 210004 kb
Host smart-a970ca1c-6ff4-4cab-ad7f-dea6d8b8faa1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440748136 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.1440748136
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.3681192500
Short name T396
Test name
Test status
Simulation time 358911710 ps
CPU time 1.48 seconds
Started Mar 10 12:28:54 PM PDT 24
Finished Mar 10 12:28:55 PM PDT 24
Peak memory 201228 kb
Host smart-72ece8d8-2e16-4fb0-9e88-81b7c636de93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681192500 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.3681192500
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.3591673935
Short name T272
Test name
Test status
Simulation time 343957022953 ps
CPU time 410.16 seconds
Started Mar 10 12:28:50 PM PDT 24
Finished Mar 10 12:35:40 PM PDT 24
Peak memory 201268 kb
Host smart-c64e81d0-ff6a-4d80-bed2-40088c19183c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591673935 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.3591673935
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.1153832397
Short name T704
Test name
Test status
Simulation time 165105131111 ps
CPU time 380.56 seconds
Started Mar 10 12:28:51 PM PDT 24
Finished Mar 10 12:35:11 PM PDT 24
Peak memory 201336 kb
Host smart-21b7c794-2006-49a3-99ab-cd11586ec422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153832397 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.1153832397
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.855178445
Short name T255
Test name
Test status
Simulation time 162200087346 ps
CPU time 90.3 seconds
Started Mar 10 12:28:56 PM PDT 24
Finished Mar 10 12:30:27 PM PDT 24
Peak memory 201380 kb
Host smart-e968b376-bd35-46b1-a077-5d68ae556ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855178445 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.855178445
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.2534683347
Short name T618
Test name
Test status
Simulation time 485401709828 ps
CPU time 262.67 seconds
Started Mar 10 12:28:46 PM PDT 24
Finished Mar 10 12:33:08 PM PDT 24
Peak memory 201416 kb
Host smart-73de1573-7ed5-432e-a9c8-b0043480ddd0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534683347 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixe
d.2534683347
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.3185548312
Short name T568
Test name
Test status
Simulation time 178478757404 ps
CPU time 61.78 seconds
Started Mar 10 12:28:53 PM PDT 24
Finished Mar 10 12:29:56 PM PDT 24
Peak memory 201480 kb
Host smart-ba5f16f6-a3ed-4067-89a3-aa4e9036b42c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185548312 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_
wakeup.3185548312
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.4209429343
Short name T88
Test name
Test status
Simulation time 406967769630 ps
CPU time 900 seconds
Started Mar 10 12:28:48 PM PDT 24
Finished Mar 10 12:43:48 PM PDT 24
Peak memory 201392 kb
Host smart-f942c05d-f513-439f-b5c9-6295276cfa16
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209429343 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
adc_ctrl_filters_wakeup_fixed.4209429343
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.1330523198
Short name T789
Test name
Test status
Simulation time 114064289247 ps
CPU time 376.99 seconds
Started Mar 10 12:28:53 PM PDT 24
Finished Mar 10 12:35:10 PM PDT 24
Peak memory 201692 kb
Host smart-71464d62-d770-4a0c-8305-3ad8d5b65872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330523198 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.1330523198
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.3844399911
Short name T678
Test name
Test status
Simulation time 35222908259 ps
CPU time 20.2 seconds
Started Mar 10 12:28:56 PM PDT 24
Finished Mar 10 12:29:17 PM PDT 24
Peak memory 201216 kb
Host smart-0e82dc8e-6982-4316-aa78-9c64769ccbbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844399911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.3844399911
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.884877642
Short name T713
Test name
Test status
Simulation time 5451797208 ps
CPU time 4.1 seconds
Started Mar 10 12:28:52 PM PDT 24
Finished Mar 10 12:28:57 PM PDT 24
Peak memory 201260 kb
Host smart-6c72f347-d303-4d48-a294-530eedff566f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884877642 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.884877642
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.1969148096
Short name T72
Test name
Test status
Simulation time 7909814483 ps
CPU time 20.79 seconds
Started Mar 10 12:29:01 PM PDT 24
Finished Mar 10 12:29:22 PM PDT 24
Peak memory 217764 kb
Host smart-b88e8fca-585b-4c99-b937-72dfc77705d6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969148096 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.1969148096
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.256028558
Short name T412
Test name
Test status
Simulation time 6087558998 ps
CPU time 14.29 seconds
Started Mar 10 12:28:49 PM PDT 24
Finished Mar 10 12:29:03 PM PDT 24
Peak memory 201312 kb
Host smart-b53e7816-20c8-4608-ae80-ce2344e45c8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256028558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.256028558
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.1990896898
Short name T254
Test name
Test status
Simulation time 340267938914 ps
CPU time 375.96 seconds
Started Mar 10 12:28:55 PM PDT 24
Finished Mar 10 12:35:11 PM PDT 24
Peak memory 201412 kb
Host smart-31ea8904-c05d-449a-8951-0cb562c1d939
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990896898 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.
1990896898
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.3723050012
Short name T751
Test name
Test status
Simulation time 392405159 ps
CPU time 1.59 seconds
Started Mar 10 12:29:19 PM PDT 24
Finished Mar 10 12:29:21 PM PDT 24
Peak memory 201292 kb
Host smart-e85a6496-aa84-4903-a590-f6f59ee916ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723050012 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.3723050012
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.1710373112
Short name T217
Test name
Test status
Simulation time 168386665006 ps
CPU time 96.8 seconds
Started Mar 10 12:29:15 PM PDT 24
Finished Mar 10 12:30:52 PM PDT 24
Peak memory 201336 kb
Host smart-57ad7ff4-235d-4526-a6e6-a95ba63aabbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710373112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.1710373112
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.3392796998
Short name T159
Test name
Test status
Simulation time 481464722143 ps
CPU time 1053.26 seconds
Started Mar 10 12:29:20 PM PDT 24
Finished Mar 10 12:46:54 PM PDT 24
Peak memory 201388 kb
Host smart-308e0640-fd8c-4e71-9bb1-f5985107abd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392796998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.3392796998
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.2506651693
Short name T696
Test name
Test status
Simulation time 491709847328 ps
CPU time 241.9 seconds
Started Mar 10 12:29:21 PM PDT 24
Finished Mar 10 12:33:24 PM PDT 24
Peak memory 201444 kb
Host smart-5e6183b2-df63-46ae-bb9b-d336f2b7a6e8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506651693 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interru
pt_fixed.2506651693
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.198281209
Short name T31
Test name
Test status
Simulation time 170915375570 ps
CPU time 106.7 seconds
Started Mar 10 12:29:21 PM PDT 24
Finished Mar 10 12:31:09 PM PDT 24
Peak memory 201440 kb
Host smart-92851bf5-953c-49af-9265-b218422db24f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198281209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.198281209
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.3984396349
Short name T548
Test name
Test status
Simulation time 169902595282 ps
CPU time 396.08 seconds
Started Mar 10 12:29:11 PM PDT 24
Finished Mar 10 12:35:47 PM PDT 24
Peak memory 201452 kb
Host smart-4f7e5933-c1cb-4819-a451-e0f4779587f6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984396349 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fix
ed.3984396349
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.2115582387
Short name T362
Test name
Test status
Simulation time 554046963760 ps
CPU time 338.98 seconds
Started Mar 10 12:30:21 PM PDT 24
Finished Mar 10 12:36:01 PM PDT 24
Peak memory 200680 kb
Host smart-9f321218-92c4-44b3-b145-16b1c3fc21ae
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115582387 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters
_wakeup.2115582387
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.410934973
Short name T701
Test name
Test status
Simulation time 389636865075 ps
CPU time 466.54 seconds
Started Mar 10 12:29:20 PM PDT 24
Finished Mar 10 12:37:08 PM PDT 24
Peak memory 201352 kb
Host smart-f6128819-3fe0-4164-9ac3-1b59d2ecafb7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410934973 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
adc_ctrl_filters_wakeup_fixed.410934973
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.1931139319
Short name T442
Test name
Test status
Simulation time 38961199943 ps
CPU time 22.03 seconds
Started Mar 10 12:29:19 PM PDT 24
Finished Mar 10 12:29:41 PM PDT 24
Peak memory 201256 kb
Host smart-6bbc3b01-e34d-4752-b2d5-19e42a5a208a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931139319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.1931139319
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.2692705998
Short name T384
Test name
Test status
Simulation time 4898653942 ps
CPU time 12.28 seconds
Started Mar 10 12:29:20 PM PDT 24
Finished Mar 10 12:29:33 PM PDT 24
Peak memory 201248 kb
Host smart-5dd449fa-9656-40bc-be7f-10b954f0edd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692705998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.2692705998
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.3784547025
Short name T464
Test name
Test status
Simulation time 6036587135 ps
CPU time 8.66 seconds
Started Mar 10 12:29:19 PM PDT 24
Finished Mar 10 12:29:28 PM PDT 24
Peak memory 201292 kb
Host smart-0e3911a1-c123-41d0-9a30-980ac936a6a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784547025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.3784547025
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.977310685
Short name T557
Test name
Test status
Simulation time 268168283519 ps
CPU time 80.96 seconds
Started Mar 10 12:29:21 PM PDT 24
Finished Mar 10 12:30:44 PM PDT 24
Peak memory 209972 kb
Host smart-3eee21b1-0f5f-404b-928b-e8671af90705
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977310685 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.977310685
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.3800570580
Short name T583
Test name
Test status
Simulation time 426666796 ps
CPU time 0.86 seconds
Started Mar 10 12:29:22 PM PDT 24
Finished Mar 10 12:29:24 PM PDT 24
Peak memory 201296 kb
Host smart-be4140aa-ccf1-485b-a678-2c88971d7bb7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800570580 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.3800570580
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.3620629684
Short name T660
Test name
Test status
Simulation time 511363331611 ps
CPU time 498.5 seconds
Started Mar 10 12:29:16 PM PDT 24
Finished Mar 10 12:37:35 PM PDT 24
Peak memory 201500 kb
Host smart-2fb049cf-6b9a-4dc2-974e-dc81c834338b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620629684 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gat
ing.3620629684
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.2660689092
Short name T160
Test name
Test status
Simulation time 166844245589 ps
CPU time 103 seconds
Started Mar 10 12:29:16 PM PDT 24
Finished Mar 10 12:31:00 PM PDT 24
Peak memory 201376 kb
Host smart-fa1fb093-f3c9-47d8-951c-876694649122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660689092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.2660689092
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.3021543783
Short name T668
Test name
Test status
Simulation time 313821769381 ps
CPU time 205.85 seconds
Started Mar 10 12:29:20 PM PDT 24
Finished Mar 10 12:32:46 PM PDT 24
Peak memory 201584 kb
Host smart-a01a000b-8b5b-46fc-97b5-c52deeada1b0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021543783 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interru
pt_fixed.3021543783
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.268542547
Short name T689
Test name
Test status
Simulation time 163146067917 ps
CPU time 104.2 seconds
Started Mar 10 12:29:15 PM PDT 24
Finished Mar 10 12:30:59 PM PDT 24
Peak memory 201340 kb
Host smart-a2616518-42f1-40a4-b290-7c574837942e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268542547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.268542547
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.2811106884
Short name T517
Test name
Test status
Simulation time 327864874156 ps
CPU time 164.49 seconds
Started Mar 10 12:29:22 PM PDT 24
Finished Mar 10 12:32:08 PM PDT 24
Peak memory 201348 kb
Host smart-a22feb1e-a1ad-4dcf-8499-0a0c7c98c3bd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811106884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fix
ed.2811106884
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.1989588668
Short name T727
Test name
Test status
Simulation time 22411592796 ps
CPU time 53.77 seconds
Started Mar 10 12:29:21 PM PDT 24
Finished Mar 10 12:30:16 PM PDT 24
Peak memory 201416 kb
Host smart-62c2e687-2d57-420a-b647-c9236424e697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989588668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.1989588668
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.2104759363
Short name T628
Test name
Test status
Simulation time 3290087048 ps
CPU time 2.49 seconds
Started Mar 10 12:29:19 PM PDT 24
Finished Mar 10 12:29:23 PM PDT 24
Peak memory 201292 kb
Host smart-a53f25b6-03d8-4e73-bd46-2a5d371d4f86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104759363 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.2104759363
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.2298734938
Short name T456
Test name
Test status
Simulation time 5711260332 ps
CPU time 13.66 seconds
Started Mar 10 12:29:21 PM PDT 24
Finished Mar 10 12:29:36 PM PDT 24
Peak memory 201312 kb
Host smart-0ffc1be2-8dfb-4a4b-a53d-3aae7d9ffc6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298734938 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.2298734938
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.3471353875
Short name T627
Test name
Test status
Simulation time 234323059468 ps
CPU time 423.71 seconds
Started Mar 10 12:29:19 PM PDT 24
Finished Mar 10 12:36:23 PM PDT 24
Peak memory 210072 kb
Host smart-2da629d1-bc53-48a2-8163-e2c4d9f53448
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471353875 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.3471353875
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.1278553234
Short name T402
Test name
Test status
Simulation time 477277835 ps
CPU time 0.7 seconds
Started Mar 10 12:29:25 PM PDT 24
Finished Mar 10 12:29:26 PM PDT 24
Peak memory 201332 kb
Host smart-79fda020-1bfb-408f-b85a-d899ea40bea0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278553234 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.1278553234
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.181710296
Short name T310
Test name
Test status
Simulation time 176847725929 ps
CPU time 218.79 seconds
Started Mar 10 12:29:16 PM PDT 24
Finished Mar 10 12:32:55 PM PDT 24
Peak memory 201448 kb
Host smart-0b0c2032-085f-413a-8688-a9e4b6822189
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181710296 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gati
ng.181710296
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.3795368722
Short name T112
Test name
Test status
Simulation time 165760289725 ps
CPU time 392.74 seconds
Started Mar 10 12:29:23 PM PDT 24
Finished Mar 10 12:35:57 PM PDT 24
Peak memory 201448 kb
Host smart-cfa446a9-3a04-4c0f-9d9b-61920f116636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795368722 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.3795368722
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.2189409385
Short name T481
Test name
Test status
Simulation time 327197478715 ps
CPU time 199.55 seconds
Started Mar 10 12:29:17 PM PDT 24
Finished Mar 10 12:32:37 PM PDT 24
Peak memory 201532 kb
Host smart-d38fda79-81b5-43f5-81cb-d4ce8286ab94
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189409385 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interru
pt_fixed.2189409385
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.2116338875
Short name T500
Test name
Test status
Simulation time 327523273182 ps
CPU time 203.84 seconds
Started Mar 10 12:29:17 PM PDT 24
Finished Mar 10 12:32:41 PM PDT 24
Peak memory 201388 kb
Host smart-af55f50e-9ccd-4154-b5b8-d1c8e5d11fdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116338875 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.2116338875
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.3762851635
Short name T424
Test name
Test status
Simulation time 328906730787 ps
CPU time 810.36 seconds
Started Mar 10 12:29:25 PM PDT 24
Finished Mar 10 12:42:56 PM PDT 24
Peak memory 201524 kb
Host smart-9c832d28-0785-4d70-bfe9-c5b0d617e368
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762851635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fix
ed.3762851635
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.3370900062
Short name T695
Test name
Test status
Simulation time 455639554147 ps
CPU time 76.38 seconds
Started Mar 10 12:29:19 PM PDT 24
Finished Mar 10 12:30:36 PM PDT 24
Peak memory 201360 kb
Host smart-593f49af-e0b5-44dd-a10f-1273c51bdca6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370900062 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters
_wakeup.3370900062
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.70752192
Short name T774
Test name
Test status
Simulation time 392341133684 ps
CPU time 652.4 seconds
Started Mar 10 12:29:21 PM PDT 24
Finished Mar 10 12:40:15 PM PDT 24
Peak memory 201340 kb
Host smart-e9c44aad-48d0-4016-9a58-353a605fa706
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70752192 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.a
dc_ctrl_filters_wakeup_fixed.70752192
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.3113426418
Short name T686
Test name
Test status
Simulation time 120159547091 ps
CPU time 436.66 seconds
Started Mar 10 12:29:21 PM PDT 24
Finished Mar 10 12:36:39 PM PDT 24
Peak memory 201672 kb
Host smart-58e91a38-595a-439d-bd29-477bc6c6354a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113426418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.3113426418
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.661649792
Short name T546
Test name
Test status
Simulation time 30869899824 ps
CPU time 19.77 seconds
Started Mar 10 12:29:21 PM PDT 24
Finished Mar 10 12:29:42 PM PDT 24
Peak memory 201272 kb
Host smart-0e2c988b-bed8-4808-907a-1dc961c79ab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661649792 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.661649792
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.2568887731
Short name T390
Test name
Test status
Simulation time 4440971305 ps
CPU time 3.23 seconds
Started Mar 10 12:29:15 PM PDT 24
Finished Mar 10 12:29:18 PM PDT 24
Peak memory 201328 kb
Host smart-fda4842e-0a1c-434b-ae23-3bf8d4e44ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568887731 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.2568887731
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.469935165
Short name T216
Test name
Test status
Simulation time 6088985899 ps
CPU time 8.21 seconds
Started Mar 10 12:29:21 PM PDT 24
Finished Mar 10 12:29:31 PM PDT 24
Peak memory 201336 kb
Host smart-6c4154e1-96c8-4c0b-b694-1e48b7722a68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469935165 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.469935165
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.3744048980
Short name T410
Test name
Test status
Simulation time 449424828 ps
CPU time 1 seconds
Started Mar 10 12:29:32 PM PDT 24
Finished Mar 10 12:29:33 PM PDT 24
Peak memory 201300 kb
Host smart-989063a4-b3bb-452a-b806-32bc232de089
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744048980 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.3744048980
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.249727141
Short name T486
Test name
Test status
Simulation time 172643793644 ps
CPU time 417.33 seconds
Started Mar 10 12:29:20 PM PDT 24
Finished Mar 10 12:36:19 PM PDT 24
Peak memory 201348 kb
Host smart-665fb91e-86ca-4b5c-804f-4bbf16faacaa
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249727141 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gati
ng.249727141
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.38800316
Short name T364
Test name
Test status
Simulation time 502333025317 ps
CPU time 1229.76 seconds
Started Mar 10 12:29:21 PM PDT 24
Finished Mar 10 12:49:52 PM PDT 24
Peak memory 201488 kb
Host smart-4a6a2a92-a962-47eb-8aa8-b2dbc106dc5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38800316 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.38800316
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.4003487482
Short name T131
Test name
Test status
Simulation time 333811735957 ps
CPU time 213.8 seconds
Started Mar 10 12:29:22 PM PDT 24
Finished Mar 10 12:32:58 PM PDT 24
Peak memory 201392 kb
Host smart-7efd89ae-4b42-447e-a971-cf58c4155e88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003487482 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.4003487482
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.1593674259
Short name T514
Test name
Test status
Simulation time 497155644691 ps
CPU time 296.82 seconds
Started Mar 10 12:29:21 PM PDT 24
Finished Mar 10 12:34:20 PM PDT 24
Peak memory 201452 kb
Host smart-2124ae35-a353-4d84-96af-d0ac0e658f8b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593674259 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interru
pt_fixed.1593674259
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.1770621440
Short name T644
Test name
Test status
Simulation time 161772362935 ps
CPU time 95.91 seconds
Started Mar 10 12:29:20 PM PDT 24
Finished Mar 10 12:30:56 PM PDT 24
Peak memory 201536 kb
Host smart-c54fd9b7-586e-4598-a847-0093b48c54af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770621440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.1770621440
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.3825308596
Short name T133
Test name
Test status
Simulation time 163724324358 ps
CPU time 104.58 seconds
Started Mar 10 12:29:20 PM PDT 24
Finished Mar 10 12:31:05 PM PDT 24
Peak memory 201420 kb
Host smart-a3de87e2-95e1-4f27-96e8-1dae62bd70ab
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825308596 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fix
ed.3825308596
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.358077741
Short name T511
Test name
Test status
Simulation time 202082579800 ps
CPU time 453.77 seconds
Started Mar 10 12:29:19 PM PDT 24
Finished Mar 10 12:36:53 PM PDT 24
Peak memory 201428 kb
Host smart-f9ef4092-8946-450f-93de-495a07c854a9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358077741 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_
wakeup.358077741
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.250794635
Short name T436
Test name
Test status
Simulation time 419887809573 ps
CPU time 496.05 seconds
Started Mar 10 12:29:22 PM PDT 24
Finished Mar 10 12:37:39 PM PDT 24
Peak memory 201364 kb
Host smart-6d831af9-62e6-4c2c-961a-b054237e9293
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250794635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
adc_ctrl_filters_wakeup_fixed.250794635
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.837172736
Short name T544
Test name
Test status
Simulation time 116454405426 ps
CPU time 453.49 seconds
Started Mar 10 12:29:21 PM PDT 24
Finished Mar 10 12:36:55 PM PDT 24
Peak memory 201680 kb
Host smart-52003e26-d727-41af-94f4-77cfe0d9b7a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837172736 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.837172736
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.2049270386
Short name T99
Test name
Test status
Simulation time 39540963243 ps
CPU time 6.26 seconds
Started Mar 10 12:29:19 PM PDT 24
Finished Mar 10 12:29:26 PM PDT 24
Peak memory 201268 kb
Host smart-9f870223-9cd3-43e8-a8b0-745716f3ee4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049270386 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.2049270386
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.2368381690
Short name T617
Test name
Test status
Simulation time 4521046489 ps
CPU time 11.19 seconds
Started Mar 10 12:29:20 PM PDT 24
Finished Mar 10 12:29:33 PM PDT 24
Peak memory 201256 kb
Host smart-174e348b-84e7-4ce4-b4ec-f82b2176e2f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368381690 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.2368381690
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.3334070019
Short name T407
Test name
Test status
Simulation time 5856186477 ps
CPU time 14.77 seconds
Started Mar 10 12:29:19 PM PDT 24
Finished Mar 10 12:29:35 PM PDT 24
Peak memory 201344 kb
Host smart-59eb9bf1-69d4-4797-a751-ded47a51e497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334070019 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.3334070019
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.3404341824
Short name T570
Test name
Test status
Simulation time 359763742676 ps
CPU time 758 seconds
Started Mar 10 12:29:23 PM PDT 24
Finished Mar 10 12:42:02 PM PDT 24
Peak memory 201480 kb
Host smart-6b968694-e2f5-422d-8540-7598736e8bc7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404341824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all
.3404341824
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.3639158555
Short name T27
Test name
Test status
Simulation time 76936096530 ps
CPU time 79.84 seconds
Started Mar 10 12:29:23 PM PDT 24
Finished Mar 10 12:30:45 PM PDT 24
Peak memory 210032 kb
Host smart-ca35b25e-e3b8-4e53-96c2-480766808fd4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639158555 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.3639158555
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.2052800000
Short name T608
Test name
Test status
Simulation time 519620697 ps
CPU time 0.9 seconds
Started Mar 10 12:29:24 PM PDT 24
Finished Mar 10 12:29:26 PM PDT 24
Peak memory 201276 kb
Host smart-d5452df3-220b-4f57-9274-b3aa15ef9c20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052800000 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.2052800000
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.3477962084
Short name T192
Test name
Test status
Simulation time 486907849137 ps
CPU time 310.84 seconds
Started Mar 10 12:29:23 PM PDT 24
Finished Mar 10 12:34:35 PM PDT 24
Peak memory 201360 kb
Host smart-9b211bbd-f4ee-4a67-a952-091ab9aab9a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477962084 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.3477962084
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.1232068281
Short name T485
Test name
Test status
Simulation time 163599150938 ps
CPU time 87.57 seconds
Started Mar 10 12:29:25 PM PDT 24
Finished Mar 10 12:30:53 PM PDT 24
Peak memory 201520 kb
Host smart-f6fcfd5c-1842-4c2e-b61a-3a2f74eb6eb8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232068281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interru
pt_fixed.1232068281
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.880248268
Short name T185
Test name
Test status
Simulation time 336041484986 ps
CPU time 732.08 seconds
Started Mar 10 12:29:24 PM PDT 24
Finished Mar 10 12:41:38 PM PDT 24
Peak memory 201420 kb
Host smart-e9502787-38af-439b-9fb2-2c506e9eca99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880248268 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.880248268
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.2357194573
Short name T124
Test name
Test status
Simulation time 168688628825 ps
CPU time 62.48 seconds
Started Mar 10 12:29:27 PM PDT 24
Finished Mar 10 12:30:29 PM PDT 24
Peak memory 201388 kb
Host smart-164766dc-8302-4c8d-9341-3bf8041baf94
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357194573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fix
ed.2357194573
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.309931230
Short name T341
Test name
Test status
Simulation time 529218514330 ps
CPU time 149.04 seconds
Started Mar 10 12:29:25 PM PDT 24
Finished Mar 10 12:31:55 PM PDT 24
Peak memory 201408 kb
Host smart-7b901171-b478-486b-98d5-2c38359f795d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309931230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_
wakeup.309931230
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.3100655423
Short name T655
Test name
Test status
Simulation time 392990908089 ps
CPU time 946.78 seconds
Started Mar 10 12:29:25 PM PDT 24
Finished Mar 10 12:45:13 PM PDT 24
Peak memory 201384 kb
Host smart-51f4b3dc-2677-47e4-9787-69f918e1ed12
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100655423 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.adc_ctrl_filters_wakeup_fixed.3100655423
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.2636549257
Short name T596
Test name
Test status
Simulation time 39324860922 ps
CPU time 99.05 seconds
Started Mar 10 12:29:22 PM PDT 24
Finished Mar 10 12:31:03 PM PDT 24
Peak memory 201316 kb
Host smart-7188aae7-4ac4-467f-bdb6-1b438d4bd74a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636549257 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.2636549257
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.1738105988
Short name T380
Test name
Test status
Simulation time 3642590861 ps
CPU time 1.62 seconds
Started Mar 10 12:29:22 PM PDT 24
Finished Mar 10 12:29:25 PM PDT 24
Peak memory 201312 kb
Host smart-859e46dd-4e86-4f55-a06e-5cea21f79994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738105988 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.1738105988
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.2856904951
Short name T786
Test name
Test status
Simulation time 6047047546 ps
CPU time 15.14 seconds
Started Mar 10 12:29:22 PM PDT 24
Finished Mar 10 12:29:39 PM PDT 24
Peak memory 201296 kb
Host smart-12f3abec-2209-4013-877f-0847537cecb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856904951 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.2856904951
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.491017283
Short name T771
Test name
Test status
Simulation time 418624232298 ps
CPU time 603.24 seconds
Started Mar 10 12:29:26 PM PDT 24
Finished Mar 10 12:39:30 PM PDT 24
Peak memory 201624 kb
Host smart-fe599de9-aecf-4d4e-8ab8-2d9dfbf7a8d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491017283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all.
491017283
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.460436700
Short name T598
Test name
Test status
Simulation time 513817592 ps
CPU time 1.78 seconds
Started Mar 10 12:29:32 PM PDT 24
Finished Mar 10 12:29:33 PM PDT 24
Peak memory 201276 kb
Host smart-fb5b66a0-d4e3-4a97-8f5d-c1b6b8b314d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460436700 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.460436700
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.3176119283
Short name T323
Test name
Test status
Simulation time 163519640656 ps
CPU time 90.79 seconds
Started Mar 10 12:29:36 PM PDT 24
Finished Mar 10 12:31:07 PM PDT 24
Peak memory 201336 kb
Host smart-dc1a8305-cdba-44c5-bc6a-5aa9aab766ae
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176119283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gat
ing.3176119283
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.3670035858
Short name T300
Test name
Test status
Simulation time 344098715359 ps
CPU time 230.57 seconds
Started Mar 10 12:29:32 PM PDT 24
Finished Mar 10 12:33:22 PM PDT 24
Peak memory 201424 kb
Host smart-20e54cee-cc3f-43a3-b124-f0a88f793e91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670035858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.3670035858
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.257435135
Short name T98
Test name
Test status
Simulation time 332455424314 ps
CPU time 742.71 seconds
Started Mar 10 12:29:27 PM PDT 24
Finished Mar 10 12:41:50 PM PDT 24
Peak memory 201520 kb
Host smart-8daa35f1-d5cb-4ac3-978c-e645e0fd951f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257435135 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.257435135
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.4256574907
Short name T577
Test name
Test status
Simulation time 490978829149 ps
CPU time 285.38 seconds
Started Mar 10 12:29:21 PM PDT 24
Finished Mar 10 12:34:08 PM PDT 24
Peak memory 201372 kb
Host smart-a1fc10c1-c591-4bb7-95a0-c53d349198b6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256574907 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interru
pt_fixed.4256574907
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.2909766757
Short name T302
Test name
Test status
Simulation time 172440372577 ps
CPU time 376.95 seconds
Started Mar 10 12:29:24 PM PDT 24
Finished Mar 10 12:35:43 PM PDT 24
Peak memory 201428 kb
Host smart-9a88ffb4-63af-4f6d-b83b-cd3a6a4dca49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909766757 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.2909766757
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.2410977607
Short name T723
Test name
Test status
Simulation time 164988368488 ps
CPU time 402.15 seconds
Started Mar 10 12:29:24 PM PDT 24
Finished Mar 10 12:36:08 PM PDT 24
Peak memory 201340 kb
Host smart-d08e36f4-ad83-4078-86d3-031f89f85e86
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410977607 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fix
ed.2410977607
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.4139642083
Short name T358
Test name
Test status
Simulation time 424580661853 ps
CPU time 441.29 seconds
Started Mar 10 12:29:29 PM PDT 24
Finished Mar 10 12:36:50 PM PDT 24
Peak memory 201424 kb
Host smart-6af958ae-45f1-469a-9b40-45d1fc59926c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139642083 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters
_wakeup.4139642083
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.3328013282
Short name T468
Test name
Test status
Simulation time 196661660502 ps
CPU time 64.76 seconds
Started Mar 10 12:29:32 PM PDT 24
Finished Mar 10 12:30:37 PM PDT 24
Peak memory 201432 kb
Host smart-6ac767b9-022c-4791-b88f-625bd4ca17e3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328013282 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.adc_ctrl_filters_wakeup_fixed.3328013282
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.3343890942
Short name T640
Test name
Test status
Simulation time 91636972591 ps
CPU time 515.6 seconds
Started Mar 10 12:29:35 PM PDT 24
Finished Mar 10 12:38:11 PM PDT 24
Peak memory 201616 kb
Host smart-9846686e-cd7f-4203-9903-7b006a35c915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343890942 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.3343890942
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.1119372949
Short name T30
Test name
Test status
Simulation time 38781503220 ps
CPU time 23.98 seconds
Started Mar 10 12:29:27 PM PDT 24
Finished Mar 10 12:29:51 PM PDT 24
Peak memory 201320 kb
Host smart-0cb6e0f7-f2f4-4348-b273-7de5e0ee58b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119372949 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.1119372949
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.1877170725
Short name T526
Test name
Test status
Simulation time 5335752866 ps
CPU time 6.87 seconds
Started Mar 10 12:29:30 PM PDT 24
Finished Mar 10 12:29:37 PM PDT 24
Peak memory 201292 kb
Host smart-0a67b48a-dad4-4bb2-b742-6b098d7fa615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877170725 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.1877170725
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.999537739
Short name T581
Test name
Test status
Simulation time 5780755818 ps
CPU time 14.34 seconds
Started Mar 10 12:29:20 PM PDT 24
Finished Mar 10 12:29:36 PM PDT 24
Peak memory 201336 kb
Host smart-b347f0ff-e290-4fec-ab03-27e5ac168df4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999537739 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.999537739
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.264965165
Short name T25
Test name
Test status
Simulation time 4538829089553 ps
CPU time 376.05 seconds
Started Mar 10 12:29:30 PM PDT 24
Finished Mar 10 12:35:46 PM PDT 24
Peak memory 209940 kb
Host smart-592bd125-fcb8-4465-aa1a-1374d4aa0e59
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264965165 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.264965165
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.4248646672
Short name T670
Test name
Test status
Simulation time 326476815 ps
CPU time 1.28 seconds
Started Mar 10 12:29:35 PM PDT 24
Finished Mar 10 12:29:37 PM PDT 24
Peak memory 201200 kb
Host smart-55737a17-ddcf-4371-9f32-b5673853aaba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248646672 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.4248646672
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.3536955674
Short name T453
Test name
Test status
Simulation time 328524002118 ps
CPU time 388.3 seconds
Started Mar 10 12:29:31 PM PDT 24
Finished Mar 10 12:35:59 PM PDT 24
Peak memory 201324 kb
Host smart-093bf5c5-91c6-4c20-9cb5-97f8514d156e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536955674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interru
pt_fixed.3536955674
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.824138271
Short name T355
Test name
Test status
Simulation time 167703855333 ps
CPU time 116.66 seconds
Started Mar 10 12:29:34 PM PDT 24
Finished Mar 10 12:31:31 PM PDT 24
Peak memory 201388 kb
Host smart-4c7e4fd2-07f1-465b-89bf-59125c56ade6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824138271 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.824138271
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.352072878
Short name T506
Test name
Test status
Simulation time 488106829261 ps
CPU time 318.17 seconds
Started Mar 10 12:29:28 PM PDT 24
Finished Mar 10 12:34:46 PM PDT 24
Peak memory 201352 kb
Host smart-92175ccf-4f12-416f-a911-7f015ae78d3b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=352072878 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fixe
d.352072878
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.1110616760
Short name T674
Test name
Test status
Simulation time 195282275162 ps
CPU time 164.6 seconds
Started Mar 10 12:29:28 PM PDT 24
Finished Mar 10 12:32:13 PM PDT 24
Peak memory 201456 kb
Host smart-a6f40157-a3e8-4655-bb64-65f5a6b84dd6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110616760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16
.adc_ctrl_filters_wakeup_fixed.1110616760
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.1056663340
Short name T698
Test name
Test status
Simulation time 99784313547 ps
CPU time 388.27 seconds
Started Mar 10 12:29:32 PM PDT 24
Finished Mar 10 12:36:00 PM PDT 24
Peak memory 201656 kb
Host smart-47caed3d-78a7-4300-81b2-dc0556103dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056663340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.1056663340
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.996757460
Short name T719
Test name
Test status
Simulation time 27430632120 ps
CPU time 32.43 seconds
Started Mar 10 12:29:31 PM PDT 24
Finished Mar 10 12:30:03 PM PDT 24
Peak memory 201204 kb
Host smart-dd77612c-7169-40f2-96b1-6418065f00dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996757460 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.996757460
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.1707378356
Short name T484
Test name
Test status
Simulation time 3675652565 ps
CPU time 3.12 seconds
Started Mar 10 12:29:33 PM PDT 24
Finished Mar 10 12:29:36 PM PDT 24
Peak memory 201260 kb
Host smart-e839bc45-7667-4a16-9e47-198aad73773b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707378356 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.1707378356
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.185205985
Short name T683
Test name
Test status
Simulation time 5804244329 ps
CPU time 3.77 seconds
Started Mar 10 12:29:36 PM PDT 24
Finished Mar 10 12:29:40 PM PDT 24
Peak memory 201288 kb
Host smart-836056aa-88de-4d30-9dc8-414ac05ac04c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185205985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.185205985
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.2469220810
Short name T315
Test name
Test status
Simulation time 168742139117 ps
CPU time 93.06 seconds
Started Mar 10 12:29:35 PM PDT 24
Finished Mar 10 12:31:08 PM PDT 24
Peak memory 201464 kb
Host smart-5ebe3060-84c3-4012-8410-b816de7f2a32
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469220810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all
.2469220810
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.2393950519
Short name T23
Test name
Test status
Simulation time 79869505473 ps
CPU time 91.89 seconds
Started Mar 10 12:29:34 PM PDT 24
Finished Mar 10 12:31:06 PM PDT 24
Peak memory 210004 kb
Host smart-e2e1b032-88ac-4736-921c-6522c9e94193
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393950519 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.2393950519
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.2683376067
Short name T756
Test name
Test status
Simulation time 334357715478 ps
CPU time 99.95 seconds
Started Mar 10 12:29:42 PM PDT 24
Finished Mar 10 12:31:22 PM PDT 24
Peak memory 201512 kb
Host smart-5098ab49-591e-4b5c-ad11-f20a0192d0e2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683376067 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gat
ing.2683376067
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.1860034565
Short name T536
Test name
Test status
Simulation time 383499826104 ps
CPU time 216.94 seconds
Started Mar 10 12:29:36 PM PDT 24
Finished Mar 10 12:33:13 PM PDT 24
Peak memory 201292 kb
Host smart-2b1ebf37-c9d3-4b30-9a55-90ed5b1589cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860034565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.1860034565
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.705723780
Short name T214
Test name
Test status
Simulation time 491411384167 ps
CPU time 305.96 seconds
Started Mar 10 12:29:39 PM PDT 24
Finished Mar 10 12:34:45 PM PDT 24
Peak memory 201408 kb
Host smart-f6dcddf3-2f65-4438-bc23-341b2a6d398d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705723780 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.705723780
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.980572748
Short name T105
Test name
Test status
Simulation time 166724879131 ps
CPU time 28.08 seconds
Started Mar 10 12:29:32 PM PDT 24
Finished Mar 10 12:30:01 PM PDT 24
Peak memory 201404 kb
Host smart-b2a7b669-63f3-459a-b132-95c92f8d20a6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=980572748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrup
t_fixed.980572748
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.1379584142
Short name T261
Test name
Test status
Simulation time 164364490173 ps
CPU time 35.64 seconds
Started Mar 10 12:29:35 PM PDT 24
Finished Mar 10 12:30:10 PM PDT 24
Peak memory 201476 kb
Host smart-195aa350-0867-4b37-b22b-cdc9ec6a8672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379584142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.1379584142
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.1746266516
Short name T438
Test name
Test status
Simulation time 497488129656 ps
CPU time 304.39 seconds
Started Mar 10 12:29:39 PM PDT 24
Finished Mar 10 12:34:43 PM PDT 24
Peak memory 201328 kb
Host smart-a10ccad3-bc5c-4151-acf3-b881eec76f2c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746266516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fix
ed.1746266516
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.1402646741
Short name T757
Test name
Test status
Simulation time 518459539985 ps
CPU time 1028.48 seconds
Started Mar 10 12:29:37 PM PDT 24
Finished Mar 10 12:46:46 PM PDT 24
Peak memory 201416 kb
Host smart-b772116d-0a6e-4612-8d8f-f2019ff43f84
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402646741 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters
_wakeup.1402646741
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.2216198831
Short name T754
Test name
Test status
Simulation time 394249290803 ps
CPU time 723.65 seconds
Started Mar 10 12:29:31 PM PDT 24
Finished Mar 10 12:41:35 PM PDT 24
Peak memory 201552 kb
Host smart-3f1d6daf-6140-4a12-a3ab-add9c7fa30ee
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216198831 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.adc_ctrl_filters_wakeup_fixed.2216198831
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.4048615675
Short name T554
Test name
Test status
Simulation time 135881484725 ps
CPU time 670.77 seconds
Started Mar 10 12:29:39 PM PDT 24
Finished Mar 10 12:40:50 PM PDT 24
Peak memory 201672 kb
Host smart-234dbce1-cb2e-49d3-9525-f92a3c2a0f95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048615675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.4048615675
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.3052426484
Short name T165
Test name
Test status
Simulation time 29131283468 ps
CPU time 37.1 seconds
Started Mar 10 12:29:32 PM PDT 24
Finished Mar 10 12:30:09 PM PDT 24
Peak memory 201252 kb
Host smart-4c4d65a7-33aa-4830-94dc-43504b33cc01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052426484 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.3052426484
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.3457198651
Short name T469
Test name
Test status
Simulation time 5071224995 ps
CPU time 1.43 seconds
Started Mar 10 12:29:37 PM PDT 24
Finished Mar 10 12:29:39 PM PDT 24
Peak memory 201372 kb
Host smart-d1790df6-ac24-4279-8faf-6ef5c6f9ef37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457198651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.3457198651
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.2834585288
Short name T406
Test name
Test status
Simulation time 5955650609 ps
CPU time 4.11 seconds
Started Mar 10 12:29:32 PM PDT 24
Finished Mar 10 12:29:37 PM PDT 24
Peak memory 201280 kb
Host smart-86a788ba-9ad5-491d-8cd7-df188a325197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834585288 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.2834585288
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.1430367813
Short name T125
Test name
Test status
Simulation time 88072275156 ps
CPU time 57.61 seconds
Started Mar 10 12:29:36 PM PDT 24
Finished Mar 10 12:30:33 PM PDT 24
Peak memory 201448 kb
Host smart-6742aa8d-4978-4a64-a829-5f1365d5afca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430367813 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.1430367813
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.102204005
Short name T699
Test name
Test status
Simulation time 556904057 ps
CPU time 0.83 seconds
Started Mar 10 12:29:42 PM PDT 24
Finished Mar 10 12:29:43 PM PDT 24
Peak memory 201332 kb
Host smart-0b089522-1b44-4af3-880b-4399f6cfdfb5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102204005 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.102204005
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.1964741319
Short name T763
Test name
Test status
Simulation time 163353368846 ps
CPU time 193.8 seconds
Started Mar 10 12:29:38 PM PDT 24
Finished Mar 10 12:32:52 PM PDT 24
Peak memory 201548 kb
Host smart-bf4023e6-cf39-4014-8999-8de9108ef75b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964741319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gat
ing.1964741319
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.2287343443
Short name T541
Test name
Test status
Simulation time 493057797625 ps
CPU time 1079.47 seconds
Started Mar 10 12:29:38 PM PDT 24
Finished Mar 10 12:47:38 PM PDT 24
Peak memory 201468 kb
Host smart-584216b8-a20d-469d-ac8f-117c9445ae8b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287343443 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interru
pt_fixed.2287343443
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.3442602354
Short name T291
Test name
Test status
Simulation time 327668790467 ps
CPU time 391.28 seconds
Started Mar 10 12:29:32 PM PDT 24
Finished Mar 10 12:36:04 PM PDT 24
Peak memory 201424 kb
Host smart-b863b303-2e57-4cfe-a41d-17c25e7af269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442602354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.3442602354
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.2028284208
Short name T765
Test name
Test status
Simulation time 489838935897 ps
CPU time 289.38 seconds
Started Mar 10 12:29:42 PM PDT 24
Finished Mar 10 12:34:31 PM PDT 24
Peak memory 201496 kb
Host smart-d412638f-4df1-4cfc-9a6c-39c72b76f258
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028284208 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fix
ed.2028284208
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.1100395814
Short name T347
Test name
Test status
Simulation time 166820487986 ps
CPU time 99.77 seconds
Started Mar 10 12:29:33 PM PDT 24
Finished Mar 10 12:31:13 PM PDT 24
Peak memory 201332 kb
Host smart-489dbffe-c749-44fd-9aeb-49b89715ac4c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100395814 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters
_wakeup.1100395814
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.3057685622
Short name T712
Test name
Test status
Simulation time 200270788068 ps
CPU time 462.18 seconds
Started Mar 10 12:29:37 PM PDT 24
Finished Mar 10 12:37:20 PM PDT 24
Peak memory 201440 kb
Host smart-2062b7ba-8c7f-4ece-8bf7-36524e5da15c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057685622 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.adc_ctrl_filters_wakeup_fixed.3057685622
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.730006058
Short name T639
Test name
Test status
Simulation time 122748843827 ps
CPU time 632.54 seconds
Started Mar 10 12:29:36 PM PDT 24
Finished Mar 10 12:40:09 PM PDT 24
Peak memory 201676 kb
Host smart-b669d084-38ee-4fad-b887-125f25db5baa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730006058 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.730006058
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.2389535706
Short name T710
Test name
Test status
Simulation time 23142417566 ps
CPU time 50.59 seconds
Started Mar 10 12:29:42 PM PDT 24
Finished Mar 10 12:30:32 PM PDT 24
Peak memory 201420 kb
Host smart-0e2d8906-6a82-4639-a97c-ebf1c80fd1ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389535706 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.2389535706
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.2865515238
Short name T457
Test name
Test status
Simulation time 4206197101 ps
CPU time 2.65 seconds
Started Mar 10 12:29:38 PM PDT 24
Finished Mar 10 12:29:41 PM PDT 24
Peak memory 201196 kb
Host smart-9c5df35d-5a27-4503-ad14-11b44d9cb686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865515238 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.2865515238
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.2618083584
Short name T529
Test name
Test status
Simulation time 5849962001 ps
CPU time 4.24 seconds
Started Mar 10 12:29:38 PM PDT 24
Finished Mar 10 12:29:43 PM PDT 24
Peak memory 201392 kb
Host smart-0c1dd476-1fb7-47a1-ae93-f6d90532eafa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618083584 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.2618083584
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.2512914627
Short name T359
Test name
Test status
Simulation time 256327485599 ps
CPU time 859.02 seconds
Started Mar 10 12:29:42 PM PDT 24
Finished Mar 10 12:44:02 PM PDT 24
Peak memory 201680 kb
Host smart-875a0b45-1bad-4925-b5fa-dd6390080e15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512914627 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all
.2512914627
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.3581453839
Short name T478
Test name
Test status
Simulation time 28926150942 ps
CPU time 15.03 seconds
Started Mar 10 12:29:37 PM PDT 24
Finished Mar 10 12:29:52 PM PDT 24
Peak memory 201532 kb
Host smart-1f53e857-df3c-45be-a6fe-841765e64c0e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581453839 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.3581453839
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.1381021046
Short name T213
Test name
Test status
Simulation time 337792991 ps
CPU time 0.7 seconds
Started Mar 10 12:29:40 PM PDT 24
Finished Mar 10 12:29:41 PM PDT 24
Peak memory 201340 kb
Host smart-3c05c2a8-5dc3-4b3b-93a2-66ccc0f6fbab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381021046 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.1381021046
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.3229338403
Short name T724
Test name
Test status
Simulation time 543763288462 ps
CPU time 1217.51 seconds
Started Mar 10 12:29:43 PM PDT 24
Finished Mar 10 12:50:00 PM PDT 24
Peak memory 201360 kb
Host smart-7175e4f5-5d5a-4c3d-940e-c4d4e36b3f84
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229338403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gat
ing.3229338403
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.2834542124
Short name T207
Test name
Test status
Simulation time 536104251033 ps
CPU time 137.27 seconds
Started Mar 10 12:29:41 PM PDT 24
Finished Mar 10 12:31:58 PM PDT 24
Peak memory 201356 kb
Host smart-429974a8-edf2-4216-beab-0959112037f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834542124 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.2834542124
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.1013373079
Short name T690
Test name
Test status
Simulation time 494337033079 ps
CPU time 563.28 seconds
Started Mar 10 12:29:36 PM PDT 24
Finished Mar 10 12:39:00 PM PDT 24
Peak memory 201420 kb
Host smart-c79abfec-315d-4abd-a7ae-3fbe88a2fed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013373079 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.1013373079
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.3348931613
Short name T7
Test name
Test status
Simulation time 156500723578 ps
CPU time 98.91 seconds
Started Mar 10 12:29:41 PM PDT 24
Finished Mar 10 12:31:20 PM PDT 24
Peak memory 201536 kb
Host smart-819c3e0d-616f-4e7f-89d4-a2985e36a271
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348931613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interru
pt_fixed.3348931613
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.2580130627
Short name T227
Test name
Test status
Simulation time 490314296757 ps
CPU time 307.12 seconds
Started Mar 10 12:29:42 PM PDT 24
Finished Mar 10 12:34:50 PM PDT 24
Peak memory 201412 kb
Host smart-4f6ad8ce-e051-41f3-8939-13525ef771ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580130627 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.2580130627
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.3735452214
Short name T620
Test name
Test status
Simulation time 334438611277 ps
CPU time 404.38 seconds
Started Mar 10 12:29:41 PM PDT 24
Finished Mar 10 12:36:25 PM PDT 24
Peak memory 201344 kb
Host smart-7015b35b-52aa-425a-8da7-6d39be72b4b8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735452214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fix
ed.3735452214
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.2552200218
Short name T629
Test name
Test status
Simulation time 194650744042 ps
CPU time 120.24 seconds
Started Mar 10 12:29:40 PM PDT 24
Finished Mar 10 12:31:41 PM PDT 24
Peak memory 201352 kb
Host smart-1dfed33d-210b-406d-a170-545654ae8eba
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552200218 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters
_wakeup.2552200218
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.4068664120
Short name T403
Test name
Test status
Simulation time 198697875121 ps
CPU time 240.38 seconds
Started Mar 10 12:29:38 PM PDT 24
Finished Mar 10 12:33:39 PM PDT 24
Peak memory 201424 kb
Host smart-1f449609-b106-458c-a135-f117ca331caa
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068664120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.adc_ctrl_filters_wakeup_fixed.4068664120
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.714636939
Short name T755
Test name
Test status
Simulation time 21329385612 ps
CPU time 52.04 seconds
Started Mar 10 12:29:40 PM PDT 24
Finished Mar 10 12:30:33 PM PDT 24
Peak memory 201292 kb
Host smart-cfabc5a3-deed-4265-a621-61172feeaf23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714636939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.714636939
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.1948531901
Short name T721
Test name
Test status
Simulation time 3688831427 ps
CPU time 4.91 seconds
Started Mar 10 12:29:42 PM PDT 24
Finished Mar 10 12:29:47 PM PDT 24
Peak memory 201352 kb
Host smart-4f8e97f0-11ed-41f6-a4af-9da8accaac3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948531901 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.1948531901
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.2783234957
Short name T132
Test name
Test status
Simulation time 5964261263 ps
CPU time 7.44 seconds
Started Mar 10 12:29:41 PM PDT 24
Finished Mar 10 12:29:49 PM PDT 24
Peak memory 201320 kb
Host smart-21084891-656b-4230-9c1d-a02b23ba3e70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783234957 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.2783234957
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.1905911783
Short name T738
Test name
Test status
Simulation time 135525342596 ps
CPU time 449.28 seconds
Started Mar 10 12:29:42 PM PDT 24
Finished Mar 10 12:37:11 PM PDT 24
Peak memory 201776 kb
Host smart-96d2291a-6e15-40db-8cae-8bcb66f71f90
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905911783 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all
.1905911783
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.2315054088
Short name T535
Test name
Test status
Simulation time 475407613 ps
CPU time 1.78 seconds
Started Mar 10 12:29:03 PM PDT 24
Finished Mar 10 12:29:05 PM PDT 24
Peak memory 201292 kb
Host smart-7415f330-1c88-4edc-904f-d244e14e8c1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315054088 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.2315054088
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.424306252
Short name T637
Test name
Test status
Simulation time 356653021685 ps
CPU time 429.18 seconds
Started Mar 10 12:28:54 PM PDT 24
Finished Mar 10 12:36:03 PM PDT 24
Peak memory 201360 kb
Host smart-e091b692-6986-4629-8533-c880d3edbe11
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424306252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gatin
g.424306252
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.3641870322
Short name T586
Test name
Test status
Simulation time 162294144415 ps
CPU time 397.04 seconds
Started Mar 10 12:28:57 PM PDT 24
Finished Mar 10 12:35:35 PM PDT 24
Peak memory 201424 kb
Host smart-f6c3c2c1-d355-47a3-968d-e1085a54bb55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641870322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.3641870322
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.3479849668
Short name T281
Test name
Test status
Simulation time 489288953879 ps
CPU time 1123.56 seconds
Started Mar 10 12:28:56 PM PDT 24
Finished Mar 10 12:47:40 PM PDT 24
Peak memory 201428 kb
Host smart-66463501-b846-4a24-b6d9-1f06f1193ed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479849668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.3479849668
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.1023071274
Short name T441
Test name
Test status
Simulation time 166567023677 ps
CPU time 205.39 seconds
Started Mar 10 12:29:00 PM PDT 24
Finished Mar 10 12:32:25 PM PDT 24
Peak memory 201404 kb
Host smart-c8c11503-b136-4c7f-b65e-254944a9324e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023071274 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrup
t_fixed.1023071274
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.2613492786
Short name T477
Test name
Test status
Simulation time 487534228778 ps
CPU time 613.95 seconds
Started Mar 10 12:28:57 PM PDT 24
Finished Mar 10 12:39:11 PM PDT 24
Peak memory 201404 kb
Host smart-1fe89b08-2d5e-4343-9204-768381c7003f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613492786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.2613492786
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.407674386
Short name T447
Test name
Test status
Simulation time 496924780170 ps
CPU time 447.19 seconds
Started Mar 10 12:28:59 PM PDT 24
Finished Mar 10 12:36:26 PM PDT 24
Peak memory 201360 kb
Host smart-b1176b82-0c05-48d4-aaec-5d5b347e6f35
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=407674386 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixed
.407674386
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.1719829411
Short name T714
Test name
Test status
Simulation time 209231255369 ps
CPU time 358.12 seconds
Started Mar 10 12:28:54 PM PDT 24
Finished Mar 10 12:34:53 PM PDT 24
Peak memory 201528 kb
Host smart-8338968e-fcb5-429d-9772-2d89332dbb87
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719829411 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_
wakeup.1719829411
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.2620858162
Short name T607
Test name
Test status
Simulation time 394038015984 ps
CPU time 67.21 seconds
Started Mar 10 12:28:54 PM PDT 24
Finished Mar 10 12:30:02 PM PDT 24
Peak memory 201464 kb
Host smart-c93db287-9c44-4a7a-858c-ada3e4be699d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620858162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
adc_ctrl_filters_wakeup_fixed.2620858162
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.1453313490
Short name T648
Test name
Test status
Simulation time 92829771240 ps
CPU time 357.06 seconds
Started Mar 10 12:29:01 PM PDT 24
Finished Mar 10 12:34:59 PM PDT 24
Peak memory 201656 kb
Host smart-743fe556-9c7c-4f5f-9c6d-a6497892799a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453313490 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.1453313490
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.192757259
Short name T611
Test name
Test status
Simulation time 32715647882 ps
CPU time 42.15 seconds
Started Mar 10 12:28:53 PM PDT 24
Finished Mar 10 12:29:36 PM PDT 24
Peak memory 201324 kb
Host smart-62a20a59-a219-48a2-8530-6fa8f5a2c90b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192757259 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.192757259
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.20874678
Short name T483
Test name
Test status
Simulation time 4594448845 ps
CPU time 12.35 seconds
Started Mar 10 12:28:55 PM PDT 24
Finished Mar 10 12:29:07 PM PDT 24
Peak memory 201304 kb
Host smart-dd78464d-3629-4304-8c92-f855599211f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20874678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.20874678
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.2471938137
Short name T83
Test name
Test status
Simulation time 4004985486 ps
CPU time 11.01 seconds
Started Mar 10 12:29:08 PM PDT 24
Finished Mar 10 12:29:19 PM PDT 24
Peak memory 216520 kb
Host smart-2cb5067f-1de9-4f40-b4eb-6915ecedabe7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471938137 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.2471938137
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.2438757830
Short name T430
Test name
Test status
Simulation time 5916520400 ps
CPU time 4.79 seconds
Started Mar 10 12:29:01 PM PDT 24
Finished Mar 10 12:29:06 PM PDT 24
Peak memory 201356 kb
Host smart-cd43e1ca-710f-4dc1-a836-3df6097a5ac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438757830 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.2438757830
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.1569204189
Short name T673
Test name
Test status
Simulation time 47137402364 ps
CPU time 51.45 seconds
Started Mar 10 12:29:02 PM PDT 24
Finished Mar 10 12:29:54 PM PDT 24
Peak memory 201312 kb
Host smart-b291b548-bbd9-4f64-974e-0503390af939
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569204189 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.
1569204189
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.462373894
Short name T211
Test name
Test status
Simulation time 466814897 ps
CPU time 1.62 seconds
Started Mar 10 12:29:51 PM PDT 24
Finished Mar 10 12:29:53 PM PDT 24
Peak memory 201280 kb
Host smart-c373eb7c-4829-4dcc-93e3-e99290d1f641
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462373894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.462373894
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.2271806363
Short name T615
Test name
Test status
Simulation time 250663196681 ps
CPU time 65.74 seconds
Started Mar 10 12:29:49 PM PDT 24
Finished Mar 10 12:30:55 PM PDT 24
Peak memory 201304 kb
Host smart-2f15df26-a22f-4d18-a87d-6b0e0659650e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271806363 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.2271806363
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.3198030121
Short name T462
Test name
Test status
Simulation time 162775085262 ps
CPU time 409.45 seconds
Started Mar 10 12:29:42 PM PDT 24
Finished Mar 10 12:36:32 PM PDT 24
Peak memory 201524 kb
Host smart-393263b6-1397-41fb-9552-614758d1f55d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198030121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.3198030121
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.1931682884
Short name T175
Test name
Test status
Simulation time 329321950190 ps
CPU time 68.22 seconds
Started Mar 10 12:29:43 PM PDT 24
Finished Mar 10 12:30:51 PM PDT 24
Peak memory 201436 kb
Host smart-df134d7b-c0db-4e94-b2f2-ee22f06f99fd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931682884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interru
pt_fixed.1931682884
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.1404272314
Short name T460
Test name
Test status
Simulation time 161290145893 ps
CPU time 180.79 seconds
Started Mar 10 12:29:41 PM PDT 24
Finished Mar 10 12:32:42 PM PDT 24
Peak memory 201396 kb
Host smart-e63797df-6795-4dea-b819-fc943c329e8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404272314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.1404272314
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.3081026952
Short name T559
Test name
Test status
Simulation time 490737174757 ps
CPU time 622.88 seconds
Started Mar 10 12:29:41 PM PDT 24
Finished Mar 10 12:40:04 PM PDT 24
Peak memory 201308 kb
Host smart-56362810-b6cf-445a-848e-51d2c207bda5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081026952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fix
ed.3081026952
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.4127053573
Short name T292
Test name
Test status
Simulation time 359065723139 ps
CPU time 222.44 seconds
Started Mar 10 12:29:43 PM PDT 24
Finished Mar 10 12:33:25 PM PDT 24
Peak memory 201404 kb
Host smart-dd879231-485a-4636-9c78-a86217c3523b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127053573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters
_wakeup.4127053573
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.1831478221
Short name T569
Test name
Test status
Simulation time 380205849691 ps
CPU time 66.43 seconds
Started Mar 10 12:29:40 PM PDT 24
Finished Mar 10 12:30:46 PM PDT 24
Peak memory 201356 kb
Host smart-556d9e9d-ef57-4420-9aa3-bed02a290249
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831478221 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20
.adc_ctrl_filters_wakeup_fixed.1831478221
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.1003728890
Short name T550
Test name
Test status
Simulation time 71152478505 ps
CPU time 399.06 seconds
Started Mar 10 12:29:44 PM PDT 24
Finished Mar 10 12:36:23 PM PDT 24
Peak memory 201632 kb
Host smart-3a3d812c-87d6-431a-9abc-66ba07640b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003728890 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.1003728890
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.1916555107
Short name T490
Test name
Test status
Simulation time 23835639855 ps
CPU time 14.75 seconds
Started Mar 10 12:29:44 PM PDT 24
Finished Mar 10 12:29:59 PM PDT 24
Peak memory 201420 kb
Host smart-c42cf934-078c-443d-be23-69d0e8696ef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916555107 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.1916555107
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.1437734335
Short name T465
Test name
Test status
Simulation time 5485579103 ps
CPU time 1.65 seconds
Started Mar 10 12:29:42 PM PDT 24
Finished Mar 10 12:29:44 PM PDT 24
Peak memory 201320 kb
Host smart-39915213-6da3-40e8-a54f-3e99fd4eb150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437734335 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.1437734335
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.2892415113
Short name T538
Test name
Test status
Simulation time 5833454648 ps
CPU time 14.73 seconds
Started Mar 10 12:29:38 PM PDT 24
Finished Mar 10 12:29:53 PM PDT 24
Peak memory 201336 kb
Host smart-a0de25c2-7cf2-415c-873d-95ebd092862f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892415113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.2892415113
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.2771376733
Short name T352
Test name
Test status
Simulation time 359304907456 ps
CPU time 182.43 seconds
Started Mar 10 12:29:47 PM PDT 24
Finished Mar 10 12:32:50 PM PDT 24
Peak memory 201396 kb
Host smart-a82ff2a5-3aa3-40da-bf21-5df78e0ae6b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771376733 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all
.2771376733
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.2032772725
Short name T508
Test name
Test status
Simulation time 511944723 ps
CPU time 1.6 seconds
Started Mar 10 12:29:43 PM PDT 24
Finished Mar 10 12:29:45 PM PDT 24
Peak memory 201240 kb
Host smart-59ae4814-ded2-4bc8-9868-2f6e831e1fd8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032772725 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.2032772725
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.1673718199
Short name T630
Test name
Test status
Simulation time 524318062913 ps
CPU time 154.31 seconds
Started Mar 10 12:29:49 PM PDT 24
Finished Mar 10 12:32:24 PM PDT 24
Peak memory 201436 kb
Host smart-fbfde0b7-9eda-4be1-b7c4-69824ac0e73f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673718199 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gat
ing.1673718199
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.323371485
Short name T322
Test name
Test status
Simulation time 167048345117 ps
CPU time 367.13 seconds
Started Mar 10 12:29:52 PM PDT 24
Finished Mar 10 12:35:59 PM PDT 24
Peak memory 201484 kb
Host smart-119a675a-7e4c-4661-817f-d14821323e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323371485 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.323371485
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.738541707
Short name T195
Test name
Test status
Simulation time 331110793272 ps
CPU time 825.13 seconds
Started Mar 10 12:29:50 PM PDT 24
Finished Mar 10 12:43:35 PM PDT 24
Peak memory 201428 kb
Host smart-bf7e0b91-ca97-4328-aa4a-86123d6a0395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738541707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.738541707
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.2264937287
Short name T114
Test name
Test status
Simulation time 330343050743 ps
CPU time 187.74 seconds
Started Mar 10 12:33:37 PM PDT 24
Finished Mar 10 12:36:46 PM PDT 24
Peak memory 200640 kb
Host smart-846aa75a-414a-43fa-be58-74e4cff503e3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264937287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interru
pt_fixed.2264937287
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.477752767
Short name T180
Test name
Test status
Simulation time 165966689804 ps
CPU time 192.38 seconds
Started Mar 10 12:29:42 PM PDT 24
Finished Mar 10 12:32:55 PM PDT 24
Peak memory 201496 kb
Host smart-8244f993-457c-4081-96dc-3e421ec7d3d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477752767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.477752767
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.2369662178
Short name T594
Test name
Test status
Simulation time 326451913052 ps
CPU time 186.26 seconds
Started Mar 10 12:29:44 PM PDT 24
Finished Mar 10 12:32:50 PM PDT 24
Peak memory 201480 kb
Host smart-d6f1459c-8471-47b4-bfbe-61e09a942c89
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369662178 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fix
ed.2369662178
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.2757524879
Short name T329
Test name
Test status
Simulation time 396452560444 ps
CPU time 464.34 seconds
Started Mar 10 12:29:46 PM PDT 24
Finished Mar 10 12:37:31 PM PDT 24
Peak memory 201304 kb
Host smart-cdbffdda-c5bc-432a-9c96-93fe753a3e83
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757524879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters
_wakeup.2757524879
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.874038868
Short name T434
Test name
Test status
Simulation time 209660688171 ps
CPU time 237.17 seconds
Started Mar 10 12:29:51 PM PDT 24
Finished Mar 10 12:33:48 PM PDT 24
Peak memory 201412 kb
Host smart-86526521-6a0f-4e91-bd35-6b865aa2a2fc
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874038868 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
adc_ctrl_filters_wakeup_fixed.874038868
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.3156920273
Short name T733
Test name
Test status
Simulation time 71765176651 ps
CPU time 258.03 seconds
Started Mar 10 12:29:44 PM PDT 24
Finished Mar 10 12:34:02 PM PDT 24
Peak memory 201832 kb
Host smart-58613346-1b11-439a-a449-c2b49c59b8d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156920273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.3156920273
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.4273137145
Short name T744
Test name
Test status
Simulation time 32855566857 ps
CPU time 40.32 seconds
Started Mar 10 12:29:46 PM PDT 24
Finished Mar 10 12:30:26 PM PDT 24
Peak memory 201456 kb
Host smart-54d846a3-4215-4933-ad33-d217fb9c47ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273137145 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.4273137145
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.287364797
Short name T461
Test name
Test status
Simulation time 2840942154 ps
CPU time 4.1 seconds
Started Mar 10 12:36:43 PM PDT 24
Finished Mar 10 12:36:48 PM PDT 24
Peak memory 199852 kb
Host smart-66b1fe9d-068b-4bfe-8b23-b7bd23ebe446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287364797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.287364797
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.497024174
Short name T694
Test name
Test status
Simulation time 5644030514 ps
CPU time 4.89 seconds
Started Mar 10 12:29:48 PM PDT 24
Finished Mar 10 12:29:53 PM PDT 24
Peak memory 201264 kb
Host smart-5ca36350-cd2d-4a30-9aae-a5275d764b83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497024174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.497024174
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.215386888
Short name T20
Test name
Test status
Simulation time 37791049088 ps
CPU time 72.98 seconds
Started Mar 10 12:29:42 PM PDT 24
Finished Mar 10 12:30:55 PM PDT 24
Peak memory 209736 kb
Host smart-fc8cbbf4-e729-4e06-bc4e-4c0a82ea085d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215386888 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.215386888
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.1761326231
Short name T779
Test name
Test status
Simulation time 424041684 ps
CPU time 0.86 seconds
Started Mar 10 12:29:50 PM PDT 24
Finished Mar 10 12:29:51 PM PDT 24
Peak memory 201288 kb
Host smart-ac0319c1-209b-40bc-b35a-7fc42aa7af5b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761326231 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.1761326231
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.2662716913
Short name T614
Test name
Test status
Simulation time 157602271430 ps
CPU time 102.25 seconds
Started Mar 10 12:29:44 PM PDT 24
Finished Mar 10 12:31:26 PM PDT 24
Peak memory 201472 kb
Host smart-1eca0e90-31e1-4d6c-b942-522276f34284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662716913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.2662716913
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.1822971099
Short name T9
Test name
Test status
Simulation time 483016823311 ps
CPU time 1046.33 seconds
Started Mar 10 12:29:49 PM PDT 24
Finished Mar 10 12:47:15 PM PDT 24
Peak memory 201368 kb
Host smart-8787ff3b-e224-44c1-8e5b-5ffeb710790d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822971099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interru
pt_fixed.1822971099
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.136040852
Short name T158
Test name
Test status
Simulation time 485490825414 ps
CPU time 536.68 seconds
Started Mar 10 12:29:50 PM PDT 24
Finished Mar 10 12:38:46 PM PDT 24
Peak memory 201316 kb
Host smart-ba5f15b3-84cd-499a-991a-9532c38d6fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136040852 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.136040852
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.754409554
Short name T388
Test name
Test status
Simulation time 323669678730 ps
CPU time 822.45 seconds
Started Mar 10 12:29:44 PM PDT 24
Finished Mar 10 12:43:26 PM PDT 24
Peak memory 201460 kb
Host smart-a282aa18-0616-4eba-88a0-18f48108d12c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=754409554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fixe
d.754409554
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.2370982836
Short name T219
Test name
Test status
Simulation time 367078610825 ps
CPU time 253.39 seconds
Started Mar 10 12:29:51 PM PDT 24
Finished Mar 10 12:34:05 PM PDT 24
Peak memory 201424 kb
Host smart-88b2ed05-f8e3-4a81-a899-196ccf6fd32f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370982836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters
_wakeup.2370982836
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.1773443228
Short name T790
Test name
Test status
Simulation time 209079019086 ps
CPU time 116.24 seconds
Started Mar 10 12:29:44 PM PDT 24
Finished Mar 10 12:31:41 PM PDT 24
Peak memory 201356 kb
Host smart-d7953e32-97cd-4f57-a8bf-380462eb9177
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773443228 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22
.adc_ctrl_filters_wakeup_fixed.1773443228
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.3582365714
Short name T563
Test name
Test status
Simulation time 110003337598 ps
CPU time 524.46 seconds
Started Mar 10 12:37:02 PM PDT 24
Finished Mar 10 12:45:47 PM PDT 24
Peak memory 201564 kb
Host smart-1934b34c-8c8b-4678-bb28-7933498ac740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582365714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.3582365714
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.1990206603
Short name T677
Test name
Test status
Simulation time 45672749167 ps
CPU time 99.23 seconds
Started Mar 10 12:36:53 PM PDT 24
Finished Mar 10 12:38:33 PM PDT 24
Peak memory 201624 kb
Host smart-d60e8447-5751-42bb-b680-d162226489b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990206603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.1990206603
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.3310538922
Short name T421
Test name
Test status
Simulation time 4056034922 ps
CPU time 9.79 seconds
Started Mar 10 12:37:47 PM PDT 24
Finished Mar 10 12:37:57 PM PDT 24
Peak memory 201272 kb
Host smart-fdd33144-8b79-448d-8cad-181e2bbdbdcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310538922 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.3310538922
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.3810933738
Short name T584
Test name
Test status
Simulation time 5924979326 ps
CPU time 4.37 seconds
Started Mar 10 12:37:39 PM PDT 24
Finished Mar 10 12:37:43 PM PDT 24
Peak memory 201356 kb
Host smart-29969d6d-236e-446d-9c24-a4ce167062fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810933738 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.3810933738
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.2412357419
Short name T597
Test name
Test status
Simulation time 5238469076 ps
CPU time 3.88 seconds
Started Mar 10 12:29:50 PM PDT 24
Finished Mar 10 12:29:54 PM PDT 24
Peak memory 201192 kb
Host smart-345f5611-b144-482d-ae04-229f46914e47
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412357419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all
.2412357419
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.409216569
Short name T12
Test name
Test status
Simulation time 194240408734 ps
CPU time 278.06 seconds
Started Mar 10 12:29:45 PM PDT 24
Finished Mar 10 12:34:23 PM PDT 24
Peak memory 210160 kb
Host smart-d34d7818-2369-4b1d-a1ca-801c6408f59b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409216569 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.409216569
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.3252297423
Short name T432
Test name
Test status
Simulation time 580923275 ps
CPU time 0.7 seconds
Started Mar 10 12:29:50 PM PDT 24
Finished Mar 10 12:29:51 PM PDT 24
Peak memory 201200 kb
Host smart-e72ff16a-9f11-43d8-80be-6653ba3924b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252297423 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.3252297423
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.1417458537
Short name T647
Test name
Test status
Simulation time 594912044510 ps
CPU time 691.42 seconds
Started Mar 10 12:29:51 PM PDT 24
Finished Mar 10 12:41:23 PM PDT 24
Peak memory 201320 kb
Host smart-54535aaa-1108-400e-9729-90a407ad3d2e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417458537 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gat
ing.1417458537
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.3168942770
Short name T547
Test name
Test status
Simulation time 163061543798 ps
CPU time 390.66 seconds
Started Mar 10 12:29:46 PM PDT 24
Finished Mar 10 12:36:17 PM PDT 24
Peak memory 201420 kb
Host smart-e2e837ed-e90b-4619-892e-e89a1c97f510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168942770 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.3168942770
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.2459929857
Short name T182
Test name
Test status
Simulation time 334825872081 ps
CPU time 205.5 seconds
Started Mar 10 12:29:52 PM PDT 24
Finished Mar 10 12:33:18 PM PDT 24
Peak memory 201436 kb
Host smart-4cfba2fd-2759-4b37-a80a-650c335a4910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459929857 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.2459929857
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.115549036
Short name T391
Test name
Test status
Simulation time 163993224375 ps
CPU time 205.49 seconds
Started Mar 10 12:29:50 PM PDT 24
Finished Mar 10 12:33:21 PM PDT 24
Peak memory 201560 kb
Host smart-05914caf-0441-4b18-839c-66c8f921fa38
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=115549036 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrup
t_fixed.115549036
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.2059562529
Short name T512
Test name
Test status
Simulation time 331316716531 ps
CPU time 817.33 seconds
Started Mar 10 12:30:01 PM PDT 24
Finished Mar 10 12:43:39 PM PDT 24
Peak memory 201260 kb
Host smart-2566abaf-265c-497f-a412-617af39425be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059562529 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.2059562529
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.1462106695
Short name T449
Test name
Test status
Simulation time 164954079928 ps
CPU time 112.52 seconds
Started Mar 10 12:29:54 PM PDT 24
Finished Mar 10 12:31:46 PM PDT 24
Peak memory 201452 kb
Host smart-4deb00d4-a861-45bd-8d42-e731142e81fa
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462106695 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fix
ed.1462106695
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.2263776
Short name T126
Test name
Test status
Simulation time 198380012456 ps
CPU time 473.49 seconds
Started Mar 10 12:29:48 PM PDT 24
Finished Mar 10 12:37:41 PM PDT 24
Peak memory 201480 kb
Host smart-2cd0eb03-7b15-44f7-813f-ead51fa806b2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_w
akeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_wa
keup.2263776
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.274491756
Short name T657
Test name
Test status
Simulation time 196668303173 ps
CPU time 121.72 seconds
Started Mar 10 12:29:52 PM PDT 24
Finished Mar 10 12:31:55 PM PDT 24
Peak memory 201412 kb
Host smart-e980e78c-b611-42aa-97ed-eb9062462bf5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274491756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
adc_ctrl_filters_wakeup_fixed.274491756
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.3166193602
Short name T652
Test name
Test status
Simulation time 32760615165 ps
CPU time 73.37 seconds
Started Mar 10 12:29:58 PM PDT 24
Finished Mar 10 12:31:12 PM PDT 24
Peak memory 201420 kb
Host smart-571905b4-438f-483f-a6b4-8610b272eebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166193602 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.3166193602
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.1782422199
Short name T401
Test name
Test status
Simulation time 3233125754 ps
CPU time 2.24 seconds
Started Mar 10 12:29:50 PM PDT 24
Finished Mar 10 12:29:52 PM PDT 24
Peak memory 201328 kb
Host smart-38400669-c15f-4eea-8ae7-837cb5af8791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782422199 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.1782422199
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.1609103631
Short name T470
Test name
Test status
Simulation time 6144960731 ps
CPU time 1.9 seconds
Started Mar 10 12:29:53 PM PDT 24
Finished Mar 10 12:29:55 PM PDT 24
Peak memory 201380 kb
Host smart-fee2da63-5a27-4b12-9eed-b670f5d80ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609103631 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.1609103631
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.1890256436
Short name T521
Test name
Test status
Simulation time 398508615470 ps
CPU time 168.49 seconds
Started Mar 10 12:29:53 PM PDT 24
Finished Mar 10 12:32:42 PM PDT 24
Peak memory 217448 kb
Host smart-47546859-fe4c-40a9-a0d5-2ead695f56a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890256436 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.1890256436
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.1778310970
Short name T515
Test name
Test status
Simulation time 524828757 ps
CPU time 0.82 seconds
Started Mar 10 12:29:54 PM PDT 24
Finished Mar 10 12:29:55 PM PDT 24
Peak memory 201280 kb
Host smart-27879841-83c0-4c05-83ee-f235afff8eea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778310970 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.1778310970
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.1366739398
Short name T110
Test name
Test status
Simulation time 348822359001 ps
CPU time 99.08 seconds
Started Mar 10 12:29:55 PM PDT 24
Finished Mar 10 12:31:34 PM PDT 24
Peak memory 201492 kb
Host smart-8f43d40a-d481-4440-a31d-58b969210dc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366739398 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.1366739398
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.3799252067
Short name T357
Test name
Test status
Simulation time 489803559472 ps
CPU time 1109.83 seconds
Started Mar 10 12:29:54 PM PDT 24
Finished Mar 10 12:48:24 PM PDT 24
Peak memory 201472 kb
Host smart-810be30e-8d1c-48a8-9f0e-175641770157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799252067 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.3799252067
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.1049893692
Short name T780
Test name
Test status
Simulation time 334262113498 ps
CPU time 204.92 seconds
Started Mar 10 12:29:51 PM PDT 24
Finished Mar 10 12:33:16 PM PDT 24
Peak memory 201400 kb
Host smart-f64db0e2-0d48-4c82-bb2f-3589fb279fdc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049893692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interru
pt_fixed.1049893692
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.1772620331
Short name T735
Test name
Test status
Simulation time 494240317960 ps
CPU time 1090.12 seconds
Started Mar 10 12:29:52 PM PDT 24
Finished Mar 10 12:48:02 PM PDT 24
Peak memory 201344 kb
Host smart-ae5bcc7b-6cd9-437f-9ade-900a8254c663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772620331 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.1772620331
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.1981679215
Short name T624
Test name
Test status
Simulation time 497191947300 ps
CPU time 1195.66 seconds
Started Mar 10 12:29:51 PM PDT 24
Finished Mar 10 12:49:47 PM PDT 24
Peak memory 201344 kb
Host smart-5d29143c-9067-49c3-8b88-9e1e197dc268
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981679215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fix
ed.1981679215
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.2966331735
Short name T266
Test name
Test status
Simulation time 185110006649 ps
CPU time 73.4 seconds
Started Mar 10 12:29:48 PM PDT 24
Finished Mar 10 12:31:01 PM PDT 24
Peak memory 201392 kb
Host smart-76072480-f853-48df-abe0-2274e22bd18b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966331735 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters
_wakeup.2966331735
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.2165914227
Short name T753
Test name
Test status
Simulation time 208581577911 ps
CPU time 142.32 seconds
Started Mar 10 12:30:00 PM PDT 24
Finished Mar 10 12:32:22 PM PDT 24
Peak memory 201436 kb
Host smart-6599f9d0-911e-4571-84db-ef9067e2d96e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165914227 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24
.adc_ctrl_filters_wakeup_fixed.2165914227
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.700694268
Short name T59
Test name
Test status
Simulation time 103050406504 ps
CPU time 414.12 seconds
Started Mar 10 12:29:54 PM PDT 24
Finished Mar 10 12:36:49 PM PDT 24
Peak memory 201748 kb
Host smart-12e2f8ca-ef40-43c1-94e9-dd12af226d12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700694268 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.700694268
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.494158208
Short name T741
Test name
Test status
Simulation time 27074475419 ps
CPU time 64.8 seconds
Started Mar 10 12:29:49 PM PDT 24
Finished Mar 10 12:30:54 PM PDT 24
Peak memory 201196 kb
Host smart-635536bf-35f6-4eaa-92b2-e71611f3034b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494158208 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.494158208
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.973549816
Short name T761
Test name
Test status
Simulation time 2779514199 ps
CPU time 4.27 seconds
Started Mar 10 12:30:02 PM PDT 24
Finished Mar 10 12:30:06 PM PDT 24
Peak memory 201144 kb
Host smart-f245856c-d798-4531-bead-7f90f654b2ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973549816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.973549816
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.2048590974
Short name T626
Test name
Test status
Simulation time 6121438993 ps
CPU time 1.63 seconds
Started Mar 10 12:29:50 PM PDT 24
Finished Mar 10 12:29:52 PM PDT 24
Peak memory 201300 kb
Host smart-d53ec73f-ee13-4f4a-95ee-98ea45ff1bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048590974 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.2048590974
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.4073107579
Short name T42
Test name
Test status
Simulation time 494617051901 ps
CPU time 1036.72 seconds
Started Mar 10 12:29:55 PM PDT 24
Finished Mar 10 12:47:12 PM PDT 24
Peak memory 201444 kb
Host smart-6e4ae11d-daef-4571-9c11-d12ecd6d47b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073107579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all
.4073107579
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.863288278
Short name T564
Test name
Test status
Simulation time 153225114516 ps
CPU time 213.97 seconds
Started Mar 10 12:29:47 PM PDT 24
Finished Mar 10 12:33:21 PM PDT 24
Peak memory 210056 kb
Host smart-64d38e2a-4ef9-46de-81b9-53f27a685c32
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863288278 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.863288278
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.1640549837
Short name T44
Test name
Test status
Simulation time 389604120 ps
CPU time 1.04 seconds
Started Mar 10 12:29:55 PM PDT 24
Finished Mar 10 12:29:56 PM PDT 24
Peak memory 201220 kb
Host smart-2fb9c854-14aa-4fa3-9ec7-a9e5dc311bb8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640549837 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.1640549837
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.3294546293
Short name T746
Test name
Test status
Simulation time 333577506312 ps
CPU time 168.75 seconds
Started Mar 10 12:30:02 PM PDT 24
Finished Mar 10 12:32:51 PM PDT 24
Peak memory 201416 kb
Host smart-51400230-fd0c-45cb-b538-cd2e0bf6130f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294546293 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gat
ing.3294546293
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.10284618
Short name T643
Test name
Test status
Simulation time 162901748248 ps
CPU time 204.4 seconds
Started Mar 10 12:29:54 PM PDT 24
Finished Mar 10 12:33:19 PM PDT 24
Peak memory 201404 kb
Host smart-95814926-19fd-4afc-a035-e2f23480b632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10284618 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.10284618
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.2408124177
Short name T593
Test name
Test status
Simulation time 323664217784 ps
CPU time 362.87 seconds
Started Mar 10 12:30:05 PM PDT 24
Finished Mar 10 12:36:08 PM PDT 24
Peak memory 201244 kb
Host smart-8d253e5e-2fce-4c4d-806d-c23a99b0803e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408124177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.2408124177
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.1074979499
Short name T178
Test name
Test status
Simulation time 489542963026 ps
CPU time 83.94 seconds
Started Mar 10 12:29:50 PM PDT 24
Finished Mar 10 12:31:14 PM PDT 24
Peak memory 201324 kb
Host smart-7fda828d-e566-4974-bb5e-e764d9511390
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074979499 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interru
pt_fixed.1074979499
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.1831051962
Short name T443
Test name
Test status
Simulation time 169018343647 ps
CPU time 373.6 seconds
Started Mar 10 12:30:00 PM PDT 24
Finished Mar 10 12:36:14 PM PDT 24
Peak memory 201432 kb
Host smart-0d934b92-9a23-4065-ae01-26f77debb099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831051962 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.1831051962
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.3066770879
Short name T466
Test name
Test status
Simulation time 500947201784 ps
CPU time 1229.46 seconds
Started Mar 10 12:29:50 PM PDT 24
Finished Mar 10 12:50:20 PM PDT 24
Peak memory 201416 kb
Host smart-139ef886-bb70-4564-ac6c-9dabfca458bb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066770879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fix
ed.3066770879
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.4135583092
Short name T252
Test name
Test status
Simulation time 181851874861 ps
CPU time 422.04 seconds
Started Mar 10 12:29:59 PM PDT 24
Finished Mar 10 12:37:02 PM PDT 24
Peak memory 201492 kb
Host smart-704d985d-cb5d-46ff-a6c2-cae1f4804bb8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135583092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters
_wakeup.4135583092
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.2779481027
Short name T103
Test name
Test status
Simulation time 201825458755 ps
CPU time 504.03 seconds
Started Mar 10 12:29:59 PM PDT 24
Finished Mar 10 12:38:24 PM PDT 24
Peak memory 201484 kb
Host smart-d5a6e68f-8a85-4131-a19d-b83844adee35
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779481027 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25
.adc_ctrl_filters_wakeup_fixed.2779481027
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.1933310783
Short name T60
Test name
Test status
Simulation time 91616765789 ps
CPU time 414 seconds
Started Mar 10 12:30:02 PM PDT 24
Finished Mar 10 12:36:57 PM PDT 24
Peak memory 201676 kb
Host smart-64bd3e03-8fac-4441-b209-c2220921ead8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933310783 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.1933310783
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.2383040941
Short name T653
Test name
Test status
Simulation time 36542943701 ps
CPU time 93.21 seconds
Started Mar 10 12:30:02 PM PDT 24
Finished Mar 10 12:31:36 PM PDT 24
Peak memory 201288 kb
Host smart-35f154d7-7b49-4eef-ba76-c9f542336f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383040941 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.2383040941
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.1899267959
Short name T716
Test name
Test status
Simulation time 2795444800 ps
CPU time 2.34 seconds
Started Mar 10 12:29:54 PM PDT 24
Finished Mar 10 12:29:56 PM PDT 24
Peak memory 201268 kb
Host smart-43d5c1b8-438e-4a6a-bbf3-b2a98dd3a67a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899267959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.1899267959
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.843582777
Short name T688
Test name
Test status
Simulation time 5609808348 ps
CPU time 7.79 seconds
Started Mar 10 12:29:59 PM PDT 24
Finished Mar 10 12:30:07 PM PDT 24
Peak memory 201300 kb
Host smart-f76e2624-e761-4f88-9d85-6db395db767a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843582777 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.843582777
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.2929939904
Short name T236
Test name
Test status
Simulation time 164117710203 ps
CPU time 464.13 seconds
Started Mar 10 12:30:02 PM PDT 24
Finished Mar 10 12:37:47 PM PDT 24
Peak memory 201632 kb
Host smart-d9e37f03-5872-4894-bb91-d0e99c9b346f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929939904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all
.2929939904
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.673063187
Short name T49
Test name
Test status
Simulation time 188457348292 ps
CPU time 464.57 seconds
Started Mar 10 12:29:55 PM PDT 24
Finished Mar 10 12:37:40 PM PDT 24
Peak memory 210052 kb
Host smart-f65ac75f-59f2-4b9e-9f86-57fe56b4be06
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673063187 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.673063187
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.1527473509
Short name T662
Test name
Test status
Simulation time 524458338 ps
CPU time 0.87 seconds
Started Mar 10 12:30:00 PM PDT 24
Finished Mar 10 12:30:01 PM PDT 24
Peak memory 201284 kb
Host smart-45d23bad-f6e2-4498-92fd-9a5aeb7bbc15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527473509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.1527473509
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.3640881385
Short name T229
Test name
Test status
Simulation time 160681294035 ps
CPU time 373.56 seconds
Started Mar 10 12:30:15 PM PDT 24
Finished Mar 10 12:36:29 PM PDT 24
Peak memory 201312 kb
Host smart-e25ca288-1dc9-44bc-8a52-e406bd8e4ab1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640881385 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gat
ing.3640881385
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.3411817449
Short name T157
Test name
Test status
Simulation time 327879956348 ps
CPU time 200.75 seconds
Started Mar 10 12:30:12 PM PDT 24
Finished Mar 10 12:33:33 PM PDT 24
Peak memory 201312 kb
Host smart-10080d3b-8f6f-4026-b14c-60b5f7f6be54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411817449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.3411817449
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.758001231
Short name T778
Test name
Test status
Simulation time 166189339342 ps
CPU time 101.14 seconds
Started Mar 10 12:29:53 PM PDT 24
Finished Mar 10 12:31:34 PM PDT 24
Peak memory 201556 kb
Host smart-f3a64e53-3a99-46ee-974e-0dfdfc7b48d0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=758001231 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrup
t_fixed.758001231
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.1734995740
Short name T190
Test name
Test status
Simulation time 482353707670 ps
CPU time 168.9 seconds
Started Mar 10 12:30:15 PM PDT 24
Finished Mar 10 12:33:04 PM PDT 24
Peak memory 201260 kb
Host smart-50080486-eaa6-44cf-a8e4-0d2d00e153d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734995740 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.1734995740
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.4081169952
Short name T537
Test name
Test status
Simulation time 161067991049 ps
CPU time 350.39 seconds
Started Mar 10 12:30:00 PM PDT 24
Finished Mar 10 12:35:51 PM PDT 24
Peak memory 201408 kb
Host smart-bb4e587c-9f59-4b34-a555-fcabe67d273c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081169952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fix
ed.4081169952
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.1863671983
Short name T387
Test name
Test status
Simulation time 384089740611 ps
CPU time 232.5 seconds
Started Mar 10 12:29:54 PM PDT 24
Finished Mar 10 12:33:47 PM PDT 24
Peak memory 201464 kb
Host smart-7745a2fe-0956-4b5a-843c-b5657dd87d66
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863671983 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26
.adc_ctrl_filters_wakeup_fixed.1863671983
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.1336591567
Short name T374
Test name
Test status
Simulation time 82124411422 ps
CPU time 400.42 seconds
Started Mar 10 12:29:56 PM PDT 24
Finished Mar 10 12:36:36 PM PDT 24
Peak memory 201652 kb
Host smart-fbe110e8-a249-45f3-85ee-57842bc45b82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336591567 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.1336591567
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.2286285111
Short name T711
Test name
Test status
Simulation time 33407298535 ps
CPU time 6.63 seconds
Started Mar 10 12:30:06 PM PDT 24
Finished Mar 10 12:30:12 PM PDT 24
Peak memory 201268 kb
Host smart-b7f79459-0b24-435c-b6fc-43433e4ff2d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286285111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.2286285111
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.2283872733
Short name T420
Test name
Test status
Simulation time 4006411728 ps
CPU time 9.06 seconds
Started Mar 10 12:29:53 PM PDT 24
Finished Mar 10 12:30:03 PM PDT 24
Peak memory 201316 kb
Host smart-7b661f43-7781-4ecc-a9ee-dd1c0ee61e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283872733 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.2283872733
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.2731047241
Short name T431
Test name
Test status
Simulation time 5901215986 ps
CPU time 7.62 seconds
Started Mar 10 12:29:54 PM PDT 24
Finished Mar 10 12:30:01 PM PDT 24
Peak memory 201324 kb
Host smart-69aa4e3d-c1a8-48fd-a05f-5bfceb9629ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731047241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.2731047241
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.2817873305
Short name T349
Test name
Test status
Simulation time 207193329208 ps
CPU time 259.17 seconds
Started Mar 10 12:30:08 PM PDT 24
Finished Mar 10 12:34:27 PM PDT 24
Peak memory 201536 kb
Host smart-b734e40b-660b-4a87-afb7-35238fd2e668
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817873305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all
.2817873305
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.4162468777
Short name T48
Test name
Test status
Simulation time 39746212916 ps
CPU time 74.58 seconds
Started Mar 10 12:29:55 PM PDT 24
Finished Mar 10 12:31:10 PM PDT 24
Peak memory 210068 kb
Host smart-a6de3f33-93cd-4730-a6ac-822cfdf26b62
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162468777 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.4162468777
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.4248085392
Short name T505
Test name
Test status
Simulation time 499222571 ps
CPU time 1.77 seconds
Started Mar 10 12:29:59 PM PDT 24
Finished Mar 10 12:30:01 PM PDT 24
Peak memory 201292 kb
Host smart-6e25c37a-5a59-4b91-bac5-c4a8214959dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248085392 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.4248085392
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.4134454359
Short name T734
Test name
Test status
Simulation time 535405749667 ps
CPU time 1395.24 seconds
Started Mar 10 12:30:05 PM PDT 24
Finished Mar 10 12:53:21 PM PDT 24
Peak memory 201436 kb
Host smart-89a3ebd8-809b-45ee-9ce3-1ed6ad34c07e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134454359 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.4134454359
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.3101709017
Short name T446
Test name
Test status
Simulation time 164939086530 ps
CPU time 85.72 seconds
Started Mar 10 12:29:56 PM PDT 24
Finished Mar 10 12:31:22 PM PDT 24
Peak memory 201444 kb
Host smart-9ccba527-addb-4879-aa85-6803d74e393a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101709017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.3101709017
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.426190991
Short name T501
Test name
Test status
Simulation time 482013101483 ps
CPU time 564.7 seconds
Started Mar 10 12:30:03 PM PDT 24
Finished Mar 10 12:39:28 PM PDT 24
Peak memory 201472 kb
Host smart-d8e828e3-8d68-4de5-951d-751b437e8f14
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=426190991 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrup
t_fixed.426190991
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.622079472
Short name T338
Test name
Test status
Simulation time 332044504889 ps
CPU time 747.68 seconds
Started Mar 10 12:30:21 PM PDT 24
Finished Mar 10 12:42:49 PM PDT 24
Peak memory 201424 kb
Host smart-5e11a55c-4cbb-453c-99ea-86a183220f11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622079472 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.622079472
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.2248237992
Short name T708
Test name
Test status
Simulation time 163732981065 ps
CPU time 22.71 seconds
Started Mar 10 12:30:03 PM PDT 24
Finished Mar 10 12:30:26 PM PDT 24
Peak memory 201468 kb
Host smart-e2c2ff5f-9190-42f5-8ef4-17da96b386c2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248237992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fix
ed.2248237992
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.2772501123
Short name T209
Test name
Test status
Simulation time 170405173135 ps
CPU time 370.02 seconds
Started Mar 10 12:30:04 PM PDT 24
Finished Mar 10 12:36:14 PM PDT 24
Peak memory 201432 kb
Host smart-c68bb04c-9d64-4cf2-ba75-13dccac03555
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772501123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters
_wakeup.2772501123
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.2582975636
Short name T399
Test name
Test status
Simulation time 391704350319 ps
CPU time 937.76 seconds
Started Mar 10 12:30:09 PM PDT 24
Finished Mar 10 12:45:48 PM PDT 24
Peak memory 201396 kb
Host smart-a7eadea8-c5ca-4972-af2a-7195973293c0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582975636 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.adc_ctrl_filters_wakeup_fixed.2582975636
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.143016325
Short name T722
Test name
Test status
Simulation time 117426200103 ps
CPU time 610.47 seconds
Started Mar 10 12:30:04 PM PDT 24
Finished Mar 10 12:40:15 PM PDT 24
Peak memory 201788 kb
Host smart-cc30ed0e-6bc4-4f9a-8138-5c8c3c737ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143016325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.143016325
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.4058010788
Short name T642
Test name
Test status
Simulation time 45215597013 ps
CPU time 15.8 seconds
Started Mar 10 12:30:11 PM PDT 24
Finished Mar 10 12:30:27 PM PDT 24
Peak memory 201376 kb
Host smart-dc24e176-ef9f-4b25-9d00-3485a27ea8b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058010788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.4058010788
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.423367410
Short name T451
Test name
Test status
Simulation time 5342838996 ps
CPU time 3.3 seconds
Started Mar 10 12:30:11 PM PDT 24
Finished Mar 10 12:30:15 PM PDT 24
Peak memory 201424 kb
Host smart-e12654ad-3202-4bd9-80e8-44a434389568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423367410 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.423367410
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.3222976454
Short name T463
Test name
Test status
Simulation time 5695211371 ps
CPU time 13.98 seconds
Started Mar 10 12:29:59 PM PDT 24
Finished Mar 10 12:30:14 PM PDT 24
Peak memory 201380 kb
Host smart-c733ad9a-aa6d-4c62-9400-30dc607d0881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222976454 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.3222976454
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.3932966867
Short name T115
Test name
Test status
Simulation time 350924316794 ps
CPU time 386.68 seconds
Started Mar 10 12:30:12 PM PDT 24
Finished Mar 10 12:36:38 PM PDT 24
Peak memory 201504 kb
Host smart-1726fa64-8b09-40a4-a041-27515cf185d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932966867 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all
.3932966867
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.3634205249
Short name T94
Test name
Test status
Simulation time 133944659846 ps
CPU time 193.67 seconds
Started Mar 10 12:30:01 PM PDT 24
Finished Mar 10 12:33:15 PM PDT 24
Peak memory 210280 kb
Host smart-3dffa95b-b450-4e21-a04c-b67cc8f01655
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634205249 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.3634205249
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.958690908
Short name T567
Test name
Test status
Simulation time 344272740 ps
CPU time 0.84 seconds
Started Mar 10 12:29:59 PM PDT 24
Finished Mar 10 12:30:00 PM PDT 24
Peak memory 201272 kb
Host smart-aa2c5d28-07c4-4ead-bc59-e77c991edda4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958690908 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.958690908
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.1584307287
Short name T361
Test name
Test status
Simulation time 491129846830 ps
CPU time 267.52 seconds
Started Mar 10 12:30:05 PM PDT 24
Finished Mar 10 12:34:33 PM PDT 24
Peak memory 201744 kb
Host smart-33366363-4b0e-467d-b299-16ef2631a298
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584307287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gat
ing.1584307287
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.1288777076
Short name T298
Test name
Test status
Simulation time 166692138492 ps
CPU time 393.66 seconds
Started Mar 10 12:29:58 PM PDT 24
Finished Mar 10 12:36:33 PM PDT 24
Peak memory 201420 kb
Host smart-4312d4c6-e425-4637-9840-6a2495f974a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288777076 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.1288777076
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.1271945336
Short name T346
Test name
Test status
Simulation time 172055718446 ps
CPU time 111.67 seconds
Started Mar 10 12:30:06 PM PDT 24
Finished Mar 10 12:31:58 PM PDT 24
Peak memory 201256 kb
Host smart-28368c5d-bad6-49be-ab2f-ef1b2e07ba36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271945336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.1271945336
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.3272938881
Short name T783
Test name
Test status
Simulation time 331882874106 ps
CPU time 270.43 seconds
Started Mar 10 12:30:01 PM PDT 24
Finished Mar 10 12:34:31 PM PDT 24
Peak memory 201448 kb
Host smart-1cdf0fa7-ccfb-4da1-b896-072d92d051d6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272938881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interru
pt_fixed.3272938881
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.283090451
Short name T776
Test name
Test status
Simulation time 489742618790 ps
CPU time 546.74 seconds
Started Mar 10 12:30:06 PM PDT 24
Finished Mar 10 12:39:13 PM PDT 24
Peak memory 201528 kb
Host smart-0e639ef1-78ae-4ab6-b48f-272b36fa3084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283090451 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.283090451
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.4115043067
Short name T91
Test name
Test status
Simulation time 165620495191 ps
CPU time 91.1 seconds
Started Mar 10 12:29:59 PM PDT 24
Finished Mar 10 12:31:30 PM PDT 24
Peak memory 201420 kb
Host smart-2cb842b9-1bd3-406e-a570-2c02cd17cf11
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115043067 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fix
ed.4115043067
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.492852665
Short name T473
Test name
Test status
Simulation time 212896898313 ps
CPU time 275.96 seconds
Started Mar 10 12:30:01 PM PDT 24
Finished Mar 10 12:34:37 PM PDT 24
Peak memory 201512 kb
Host smart-bc62df4b-8622-417d-91e5-c03967cd766c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492852665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
adc_ctrl_filters_wakeup_fixed.492852665
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.347244348
Short name T250
Test name
Test status
Simulation time 132653451237 ps
CPU time 703.96 seconds
Started Mar 10 12:30:00 PM PDT 24
Finished Mar 10 12:41:45 PM PDT 24
Peak memory 201644 kb
Host smart-2a4de3b4-0dd0-46da-b39c-4e80e5c172bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347244348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.347244348
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.3064485374
Short name T680
Test name
Test status
Simulation time 32441699438 ps
CPU time 19.95 seconds
Started Mar 10 12:37:08 PM PDT 24
Finished Mar 10 12:37:28 PM PDT 24
Peak memory 201244 kb
Host smart-ddd5faf0-1f85-4c20-b119-c8a9ecd7d0b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064485374 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.3064485374
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.1233271086
Short name T492
Test name
Test status
Simulation time 2822173228 ps
CPU time 1.5 seconds
Started Mar 10 12:30:01 PM PDT 24
Finished Mar 10 12:30:03 PM PDT 24
Peak memory 201256 kb
Host smart-da4dfe28-7ebd-4ccb-8685-f2d9df7fd53c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233271086 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.1233271086
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.2338668136
Short name T715
Test name
Test status
Simulation time 5810287464 ps
CPU time 4.06 seconds
Started Mar 10 12:30:06 PM PDT 24
Finished Mar 10 12:30:10 PM PDT 24
Peak memory 201304 kb
Host smart-6dc90973-a463-405d-92f8-28053105016d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338668136 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.2338668136
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.1780905184
Short name T489
Test name
Test status
Simulation time 531367526 ps
CPU time 1.89 seconds
Started Mar 10 12:36:52 PM PDT 24
Finished Mar 10 12:36:56 PM PDT 24
Peak memory 200512 kb
Host smart-e677a415-c660-4652-ba83-cc4bd9d37656
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780905184 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.1780905184
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.3476244329
Short name T435
Test name
Test status
Simulation time 241868849044 ps
CPU time 471.15 seconds
Started Mar 10 12:30:06 PM PDT 24
Finished Mar 10 12:37:57 PM PDT 24
Peak memory 201424 kb
Host smart-4ef7b6d1-a24f-4783-aaea-43c0f3d20fb3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476244329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gat
ing.3476244329
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.3383422617
Short name T669
Test name
Test status
Simulation time 163857293718 ps
CPU time 58.19 seconds
Started Mar 10 12:30:13 PM PDT 24
Finished Mar 10 12:31:11 PM PDT 24
Peak memory 201376 kb
Host smart-dedfe68c-0b8f-4396-8623-97a53ffd10a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383422617 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.3383422617
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.485189626
Short name T258
Test name
Test status
Simulation time 328174376797 ps
CPU time 747.32 seconds
Started Mar 10 12:30:14 PM PDT 24
Finished Mar 10 12:42:41 PM PDT 24
Peak memory 201488 kb
Host smart-522715c2-1ab8-43c5-8dcc-c77773b06003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485189626 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.485189626
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.3974091937
Short name T743
Test name
Test status
Simulation time 489880957266 ps
CPU time 169.32 seconds
Started Mar 10 12:30:13 PM PDT 24
Finished Mar 10 12:33:02 PM PDT 24
Peak memory 201408 kb
Host smart-513c6721-8783-4937-9352-f5ff31ca2f8e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974091937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interru
pt_fixed.3974091937
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.2928535459
Short name T467
Test name
Test status
Simulation time 337097973549 ps
CPU time 218.1 seconds
Started Mar 10 12:30:10 PM PDT 24
Finished Mar 10 12:33:48 PM PDT 24
Peak memory 201228 kb
Host smart-95488d53-7479-4fab-9cba-eec6051526be
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928535459 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fix
ed.2928535459
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.1544975324
Short name T691
Test name
Test status
Simulation time 206048242140 ps
CPU time 239.48 seconds
Started Mar 10 12:30:04 PM PDT 24
Finished Mar 10 12:34:03 PM PDT 24
Peak memory 201284 kb
Host smart-4cf1c41f-17c1-4952-8e53-b26d7372ee81
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544975324 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.adc_ctrl_filters_wakeup_fixed.1544975324
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.920799903
Short name T480
Test name
Test status
Simulation time 121777282561 ps
CPU time 429.74 seconds
Started Mar 10 12:30:06 PM PDT 24
Finished Mar 10 12:37:16 PM PDT 24
Peak memory 201592 kb
Host smart-8bba16ac-f8a8-4497-b2f9-2b4c83007f51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920799903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.920799903
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.212169371
Short name T395
Test name
Test status
Simulation time 30357530313 ps
CPU time 63.98 seconds
Started Mar 10 12:30:05 PM PDT 24
Finished Mar 10 12:31:09 PM PDT 24
Peak memory 201324 kb
Host smart-adf4b0c8-7a9c-464d-a3b7-1f25c1cf0de2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212169371 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.212169371
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.331042805
Short name T19
Test name
Test status
Simulation time 4394206292 ps
CPU time 2.05 seconds
Started Mar 10 12:30:12 PM PDT 24
Finished Mar 10 12:30:14 PM PDT 24
Peak memory 201256 kb
Host smart-ef7d656c-b971-4c5d-b29c-32078b8207b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331042805 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.331042805
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.4207321559
Short name T497
Test name
Test status
Simulation time 5743100267 ps
CPU time 3.97 seconds
Started Mar 10 12:30:04 PM PDT 24
Finished Mar 10 12:30:08 PM PDT 24
Peak memory 201228 kb
Host smart-8fc8ed46-91cb-4969-9966-f7c598454414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207321559 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.4207321559
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.4167515492
Short name T297
Test name
Test status
Simulation time 392097850864 ps
CPU time 147.98 seconds
Started Mar 10 12:30:27 PM PDT 24
Finished Mar 10 12:32:55 PM PDT 24
Peak memory 201324 kb
Host smart-0a0a2e21-85ac-48da-bb92-0d667b997370
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167515492 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all
.4167515492
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.2560145372
Short name T365
Test name
Test status
Simulation time 19552930158 ps
CPU time 73.09 seconds
Started Mar 10 12:30:00 PM PDT 24
Finished Mar 10 12:31:14 PM PDT 24
Peak memory 209940 kb
Host smart-35633f20-dd36-4ba3-a3a7-00e8c6af9bb1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560145372 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.2560145372
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.3303313127
Short name T772
Test name
Test status
Simulation time 296463906 ps
CPU time 1.24 seconds
Started Mar 10 12:28:59 PM PDT 24
Finished Mar 10 12:29:00 PM PDT 24
Peak memory 201308 kb
Host smart-22770bbe-a45f-433f-b818-ec4cb241b349
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303313127 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.3303313127
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.3931586739
Short name T740
Test name
Test status
Simulation time 163808081877 ps
CPU time 49.95 seconds
Started Mar 10 12:29:05 PM PDT 24
Finished Mar 10 12:29:55 PM PDT 24
Peak memory 201436 kb
Host smart-2033482c-dda0-42d6-b9f7-4c727d8dd0ed
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931586739 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gati
ng.3931586739
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.1566304591
Short name T194
Test name
Test status
Simulation time 556059222816 ps
CPU time 88.79 seconds
Started Mar 10 12:29:00 PM PDT 24
Finished Mar 10 12:30:29 PM PDT 24
Peak memory 201428 kb
Host smart-72b0f2d4-e6aa-447c-a551-4f1b9a8f15c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566304591 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.1566304591
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.1401804064
Short name T276
Test name
Test status
Simulation time 324372576850 ps
CPU time 189.75 seconds
Started Mar 10 12:29:06 PM PDT 24
Finished Mar 10 12:32:17 PM PDT 24
Peak memory 201408 kb
Host smart-e81482a3-d26b-4aac-9391-03ae48c8e070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401804064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.1401804064
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.2630438893
Short name T385
Test name
Test status
Simulation time 166730061073 ps
CPU time 190.41 seconds
Started Mar 10 12:29:08 PM PDT 24
Finished Mar 10 12:32:19 PM PDT 24
Peak memory 201324 kb
Host smart-13e980af-2c14-4e8d-9cef-ca9af4fcbd21
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630438893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrup
t_fixed.2630438893
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.74665120
Short name T440
Test name
Test status
Simulation time 321035471216 ps
CPU time 200.77 seconds
Started Mar 10 12:29:11 PM PDT 24
Finished Mar 10 12:32:33 PM PDT 24
Peak memory 201376 kb
Host smart-c4621904-5ec0-452e-ad77-351ceb2a9eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74665120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.74665120
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.391025196
Short name T425
Test name
Test status
Simulation time 335085730366 ps
CPU time 764.29 seconds
Started Mar 10 12:29:00 PM PDT 24
Finished Mar 10 12:41:44 PM PDT 24
Peak memory 201476 kb
Host smart-ca19212c-943c-4d52-a4f8-318900166aa7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=391025196 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixed
.391025196
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.3052450455
Short name T223
Test name
Test status
Simulation time 598460878586 ps
CPU time 660.58 seconds
Started Mar 10 12:29:04 PM PDT 24
Finished Mar 10 12:40:05 PM PDT 24
Peak memory 201464 kb
Host smart-1a6472ef-6d3b-41b0-87f1-62f20d1239f9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052450455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
adc_ctrl_filters_wakeup_fixed.3052450455
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.954153971
Short name T590
Test name
Test status
Simulation time 142235385574 ps
CPU time 747.7 seconds
Started Mar 10 12:29:04 PM PDT 24
Finished Mar 10 12:41:32 PM PDT 24
Peak memory 201696 kb
Host smart-05df93af-fe9e-4943-ac35-f1fb011ca8d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954153971 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.954153971
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.3375578797
Short name T589
Test name
Test status
Simulation time 27195996097 ps
CPU time 8.96 seconds
Started Mar 10 12:29:01 PM PDT 24
Finished Mar 10 12:29:10 PM PDT 24
Peak memory 201296 kb
Host smart-b3cf58f2-95c9-4d59-8501-c765ac78b07a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375578797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.3375578797
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.4008895976
Short name T418
Test name
Test status
Simulation time 3080266843 ps
CPU time 8.01 seconds
Started Mar 10 12:29:01 PM PDT 24
Finished Mar 10 12:29:10 PM PDT 24
Peak memory 201228 kb
Host smart-806bf52d-7b10-41da-8d07-faf96c30ccd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008895976 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.4008895976
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.843354885
Short name T74
Test name
Test status
Simulation time 7531077743 ps
CPU time 17.92 seconds
Started Mar 10 12:29:03 PM PDT 24
Finished Mar 10 12:29:21 PM PDT 24
Peak memory 217556 kb
Host smart-62359027-1c2c-4fa4-b578-4a2689687788
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843354885 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.843354885
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.3796690614
Short name T121
Test name
Test status
Simulation time 5657915625 ps
CPU time 14.75 seconds
Started Mar 10 12:29:00 PM PDT 24
Finished Mar 10 12:29:15 PM PDT 24
Peak memory 201340 kb
Host smart-85e6f5d2-e3a8-4ee4-a03b-145e72782546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796690614 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.3796690614
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.2999495036
Short name T14
Test name
Test status
Simulation time 402055755 ps
CPU time 0.66 seconds
Started Mar 10 12:30:21 PM PDT 24
Finished Mar 10 12:30:22 PM PDT 24
Peak memory 201236 kb
Host smart-25437aa1-9cc2-4b4f-a5aa-4eb57186b39b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999495036 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.2999495036
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.9634358
Short name T337
Test name
Test status
Simulation time 375416422029 ps
CPU time 160.33 seconds
Started Mar 10 12:30:18 PM PDT 24
Finished Mar 10 12:32:59 PM PDT 24
Peak memory 201448 kb
Host smart-c7993abd-7595-4f2c-8144-c96fba6a477a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9634358 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_gat
ing_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gating.9634358
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.3515808434
Short name T305
Test name
Test status
Simulation time 159682111173 ps
CPU time 102.75 seconds
Started Mar 10 12:30:07 PM PDT 24
Finished Mar 10 12:31:50 PM PDT 24
Peak memory 201460 kb
Host smart-30521ebd-f328-4c51-b26e-e3258210908b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515808434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.3515808434
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.1858888768
Short name T336
Test name
Test status
Simulation time 491875611483 ps
CPU time 1071.97 seconds
Started Mar 10 12:30:26 PM PDT 24
Finished Mar 10 12:48:19 PM PDT 24
Peak memory 201320 kb
Host smart-bbff74ea-faff-40dd-9d76-d1d735ec090e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858888768 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.1858888768
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.2986719258
Short name T386
Test name
Test status
Simulation time 165465499071 ps
CPU time 372.82 seconds
Started Mar 10 12:37:40 PM PDT 24
Finished Mar 10 12:43:53 PM PDT 24
Peak memory 201516 kb
Host smart-8fbcf041-c01e-4e9e-9eab-dcd679b4b7b9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986719258 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interru
pt_fixed.2986719258
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.2224925869
Short name T162
Test name
Test status
Simulation time 485232934005 ps
CPU time 1004.76 seconds
Started Mar 10 12:29:59 PM PDT 24
Finished Mar 10 12:46:45 PM PDT 24
Peak memory 201480 kb
Host smart-188eeba6-1179-49e0-a8ec-d62425b6d9ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224925869 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.2224925869
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.103129930
Short name T482
Test name
Test status
Simulation time 486086986045 ps
CPU time 1115.46 seconds
Started Mar 10 12:36:43 PM PDT 24
Finished Mar 10 12:55:20 PM PDT 24
Peak memory 199980 kb
Host smart-6a348097-b81c-4fd7-8bc9-071f7d24d17f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=103129930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fixe
d.103129930
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.3670960674
Short name T525
Test name
Test status
Simulation time 592600666515 ps
CPU time 1368.31 seconds
Started Mar 10 12:30:10 PM PDT 24
Finished Mar 10 12:52:58 PM PDT 24
Peak memory 201432 kb
Host smart-49967025-307b-4a9e-abfc-0ffd1b02c501
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670960674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.adc_ctrl_filters_wakeup_fixed.3670960674
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.1335725670
Short name T61
Test name
Test status
Simulation time 132927646371 ps
CPU time 473.67 seconds
Started Mar 10 12:30:23 PM PDT 24
Finished Mar 10 12:38:17 PM PDT 24
Peak memory 201688 kb
Host smart-bf0a93f4-266b-42a5-a584-c68d501bb50d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335725670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.1335725670
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.2260358791
Short name T510
Test name
Test status
Simulation time 42107677841 ps
CPU time 28.75 seconds
Started Mar 10 12:30:21 PM PDT 24
Finished Mar 10 12:30:50 PM PDT 24
Peak memory 201316 kb
Host smart-eb8efd3f-118e-443d-8670-0b42d6cd15bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260358791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.2260358791
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.3690676353
Short name T411
Test name
Test status
Simulation time 3046632556 ps
CPU time 2.58 seconds
Started Mar 10 12:37:08 PM PDT 24
Finished Mar 10 12:37:10 PM PDT 24
Peak memory 201272 kb
Host smart-93259f7f-72e6-4265-b563-078ea7d39a32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690676353 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.3690676353
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.3405350126
Short name T416
Test name
Test status
Simulation time 5837567107 ps
CPU time 8.34 seconds
Started Mar 10 12:30:27 PM PDT 24
Finished Mar 10 12:30:35 PM PDT 24
Peak memory 201260 kb
Host smart-eae7225f-3ed7-456a-8980-562d00dd22cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405350126 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.3405350126
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.1752734659
Short name T93
Test name
Test status
Simulation time 173009888729 ps
CPU time 202.47 seconds
Started Mar 10 12:30:05 PM PDT 24
Finished Mar 10 12:33:28 PM PDT 24
Peak memory 201460 kb
Host smart-735d6ef9-de21-45e7-a02c-a3f2f42e1a6b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752734659 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all
.1752734659
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.1550499705
Short name T263
Test name
Test status
Simulation time 69307163306 ps
CPU time 195.21 seconds
Started Mar 10 12:30:13 PM PDT 24
Finished Mar 10 12:33:29 PM PDT 24
Peak memory 210072 kb
Host smart-e2c0e0dc-38b7-4a88-ae5d-4217b9c5bd3f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550499705 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.1550499705
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.4187579255
Short name T737
Test name
Test status
Simulation time 320065767 ps
CPU time 1.4 seconds
Started Mar 10 12:30:05 PM PDT 24
Finished Mar 10 12:30:06 PM PDT 24
Peak memory 201172 kb
Host smart-48f002b8-0916-41ec-9e32-422d593d29a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187579255 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.4187579255
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.1547174643
Short name T766
Test name
Test status
Simulation time 522598356496 ps
CPU time 1196.89 seconds
Started Mar 10 12:30:03 PM PDT 24
Finished Mar 10 12:50:01 PM PDT 24
Peak memory 201504 kb
Host smart-7f65383f-254f-45c5-ad6b-54a9c0c6ec30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547174643 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.1547174643
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.613867833
Short name T556
Test name
Test status
Simulation time 490207439138 ps
CPU time 526.4 seconds
Started Mar 10 12:30:16 PM PDT 24
Finished Mar 10 12:39:02 PM PDT 24
Peak memory 201532 kb
Host smart-49b9181e-79b4-4eae-a756-aa19ed13c89b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=613867833 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrup
t_fixed.613867833
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.2643068395
Short name T575
Test name
Test status
Simulation time 329583165714 ps
CPU time 94.8 seconds
Started Mar 10 12:30:03 PM PDT 24
Finished Mar 10 12:31:38 PM PDT 24
Peak memory 201408 kb
Host smart-c8ce0c73-0ea0-4ecb-91af-b6a2cae655ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643068395 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.2643068395
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.914758461
Short name T476
Test name
Test status
Simulation time 488135609053 ps
CPU time 114.39 seconds
Started Mar 10 12:30:05 PM PDT 24
Finished Mar 10 12:32:00 PM PDT 24
Peak memory 201344 kb
Host smart-e666e859-6d83-4d3c-9c2b-2cd6a88845c7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=914758461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fixe
d.914758461
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.530458245
Short name T360
Test name
Test status
Simulation time 343309112492 ps
CPU time 132.44 seconds
Started Mar 10 12:30:10 PM PDT 24
Finished Mar 10 12:32:23 PM PDT 24
Peak memory 201472 kb
Host smart-848c85f7-deee-427e-9271-7827c240a76c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530458245 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_
wakeup.530458245
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.1627259348
Short name T781
Test name
Test status
Simulation time 409667390346 ps
CPU time 938.52 seconds
Started Mar 10 12:30:10 PM PDT 24
Finished Mar 10 12:45:49 PM PDT 24
Peak memory 201336 kb
Host smart-abd4ef1e-01a4-416f-aa04-54d56dbdb34f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627259348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31
.adc_ctrl_filters_wakeup_fixed.1627259348
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.713757728
Short name T100
Test name
Test status
Simulation time 89024374735 ps
CPU time 328.22 seconds
Started Mar 10 12:30:14 PM PDT 24
Finished Mar 10 12:35:43 PM PDT 24
Peak memory 201768 kb
Host smart-b1285302-bdc4-4f21-8693-4e7afe6044ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713757728 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.713757728
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.2355364603
Short name T379
Test name
Test status
Simulation time 27306832612 ps
CPU time 33.63 seconds
Started Mar 10 12:30:06 PM PDT 24
Finished Mar 10 12:30:40 PM PDT 24
Peak memory 201292 kb
Host smart-5e06e79b-c24b-4ccb-99e6-40c3330f4be1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355364603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.2355364603
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.4031006768
Short name T154
Test name
Test status
Simulation time 3280734205 ps
CPU time 2.63 seconds
Started Mar 10 12:30:12 PM PDT 24
Finished Mar 10 12:30:14 PM PDT 24
Peak memory 201304 kb
Host smart-0b6c882b-9d49-44c7-9429-0ffec1df80be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031006768 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.4031006768
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.3570302863
Short name T531
Test name
Test status
Simulation time 5576047369 ps
CPU time 3.84 seconds
Started Mar 10 12:30:10 PM PDT 24
Finished Mar 10 12:30:14 PM PDT 24
Peak memory 201376 kb
Host smart-6add6973-cad8-4389-8f08-3bd0781f99e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570302863 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.3570302863
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.3084929211
Short name T51
Test name
Test status
Simulation time 68719347607 ps
CPU time 171.42 seconds
Started Mar 10 12:30:23 PM PDT 24
Finished Mar 10 12:33:15 PM PDT 24
Peak memory 209744 kb
Host smart-74654224-2495-4e6f-af2e-ea14c9f36623
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084929211 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.3084929211
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.3872801871
Short name T381
Test name
Test status
Simulation time 507016813 ps
CPU time 0.84 seconds
Started Mar 10 12:30:20 PM PDT 24
Finished Mar 10 12:30:21 PM PDT 24
Peak memory 201208 kb
Host smart-b4f13391-1dc7-49c3-8c13-d310c735196e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872801871 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.3872801871
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.799559532
Short name T681
Test name
Test status
Simulation time 538939462880 ps
CPU time 219.27 seconds
Started Mar 10 12:30:10 PM PDT 24
Finished Mar 10 12:33:50 PM PDT 24
Peak memory 201408 kb
Host smart-1dac9179-8441-48da-a974-347a7571b827
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799559532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gati
ng.799559532
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.3466614511
Short name T533
Test name
Test status
Simulation time 324007810006 ps
CPU time 760.56 seconds
Started Mar 10 12:30:24 PM PDT 24
Finished Mar 10 12:43:05 PM PDT 24
Peak memory 201440 kb
Host smart-62668e87-9ba1-4be7-9f1b-9c211ee99a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466614511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.3466614511
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.219207471
Short name T166
Test name
Test status
Simulation time 159438099450 ps
CPU time 365.65 seconds
Started Mar 10 12:30:09 PM PDT 24
Finished Mar 10 12:36:15 PM PDT 24
Peak memory 201460 kb
Host smart-c5d1a002-18fd-44d9-b4cf-840c13244471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219207471 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.219207471
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.2722159804
Short name T503
Test name
Test status
Simulation time 163777061304 ps
CPU time 103.5 seconds
Started Mar 10 12:30:06 PM PDT 24
Finished Mar 10 12:31:50 PM PDT 24
Peak memory 201484 kb
Host smart-edeb2e80-8be4-4ced-b4d9-d2b05ec451c2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722159804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interru
pt_fixed.2722159804
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.2065274047
Short name T610
Test name
Test status
Simulation time 490219956282 ps
CPU time 1124.64 seconds
Started Mar 10 12:30:19 PM PDT 24
Finished Mar 10 12:49:04 PM PDT 24
Peak memory 201540 kb
Host smart-0d04f337-cd17-42ba-882f-dd0a28623606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065274047 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.2065274047
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.491220995
Short name T46
Test name
Test status
Simulation time 163432094304 ps
CPU time 368.95 seconds
Started Mar 10 12:30:06 PM PDT 24
Finished Mar 10 12:36:15 PM PDT 24
Peak memory 201388 kb
Host smart-b8b8d444-1288-4e68-885d-f6aaf833d985
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=491220995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fixe
d.491220995
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.1672223831
Short name T326
Test name
Test status
Simulation time 374935673331 ps
CPU time 184.03 seconds
Started Mar 10 12:30:18 PM PDT 24
Finished Mar 10 12:33:22 PM PDT 24
Peak memory 201408 kb
Host smart-070c6932-dee6-4198-a927-64bf2e395cd5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672223831 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters
_wakeup.1672223831
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.2142959482
Short name T750
Test name
Test status
Simulation time 391342538479 ps
CPU time 93.26 seconds
Started Mar 10 12:30:15 PM PDT 24
Finished Mar 10 12:31:49 PM PDT 24
Peak memory 201412 kb
Host smart-7fb6e21d-fa9e-4e47-888d-15f00942c96e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142959482 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.adc_ctrl_filters_wakeup_fixed.2142959482
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.2893010310
Short name T676
Test name
Test status
Simulation time 115608337541 ps
CPU time 560.2 seconds
Started Mar 10 12:30:26 PM PDT 24
Finished Mar 10 12:39:46 PM PDT 24
Peak memory 201644 kb
Host smart-6f34dbd1-34ea-4337-9b17-7fc738183482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893010310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.2893010310
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.2047042934
Short name T408
Test name
Test status
Simulation time 23563794373 ps
CPU time 14.55 seconds
Started Mar 10 12:30:10 PM PDT 24
Finished Mar 10 12:30:25 PM PDT 24
Peak memory 201220 kb
Host smart-d2838dee-6474-4736-b7e5-edd878c00887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047042934 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.2047042934
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.3097012525
Short name T659
Test name
Test status
Simulation time 4637699435 ps
CPU time 11.53 seconds
Started Mar 10 12:30:11 PM PDT 24
Finished Mar 10 12:30:23 PM PDT 24
Peak memory 201288 kb
Host smart-c6736feb-54e8-4827-b3e1-675b5925b6fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097012525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.3097012525
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.1764304245
Short name T649
Test name
Test status
Simulation time 5685253962 ps
CPU time 4.06 seconds
Started Mar 10 12:30:24 PM PDT 24
Finished Mar 10 12:30:28 PM PDT 24
Peak memory 201332 kb
Host smart-734ba5af-2f8d-470c-b598-c692cdbd95a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764304245 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.1764304245
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.2661084449
Short name T375
Test name
Test status
Simulation time 317791781474 ps
CPU time 1063.31 seconds
Started Mar 10 12:30:09 PM PDT 24
Finished Mar 10 12:47:53 PM PDT 24
Peak memory 201696 kb
Host smart-36a65455-2f19-46d8-8cfb-64533af6d07f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661084449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all
.2661084449
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.1092719727
Short name T4
Test name
Test status
Simulation time 504310644 ps
CPU time 1.73 seconds
Started Mar 10 12:30:07 PM PDT 24
Finished Mar 10 12:30:10 PM PDT 24
Peak memory 201292 kb
Host smart-11dc6fa8-6e0c-4b09-8803-dbbafed32ff4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092719727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.1092719727
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.22651637
Short name T325
Test name
Test status
Simulation time 198503371644 ps
CPU time 121.44 seconds
Started Mar 10 12:30:13 PM PDT 24
Finished Mar 10 12:32:14 PM PDT 24
Peak memory 201388 kb
Host smart-3a8bf99a-1055-4a7e-80a8-4c448979b2fe
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22651637 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gatin
g.22651637
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.827773040
Short name T759
Test name
Test status
Simulation time 160919498539 ps
CPU time 69.33 seconds
Started Mar 10 12:30:21 PM PDT 24
Finished Mar 10 12:31:31 PM PDT 24
Peak memory 201328 kb
Host smart-32ffc34b-b970-4662-80c9-f2f2d35fb4d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827773040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.827773040
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.1252290944
Short name T193
Test name
Test status
Simulation time 329050214704 ps
CPU time 402.56 seconds
Started Mar 10 12:30:14 PM PDT 24
Finished Mar 10 12:36:57 PM PDT 24
Peak memory 201344 kb
Host smart-337e4fb5-3043-4db1-b40f-7167cb9624c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252290944 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.1252290944
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.540870223
Short name T234
Test name
Test status
Simulation time 331869945206 ps
CPU time 395.99 seconds
Started Mar 10 12:30:08 PM PDT 24
Finished Mar 10 12:36:44 PM PDT 24
Peak memory 201420 kb
Host smart-e2d83f5d-0ba0-4841-999b-773c060080e7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=540870223 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrup
t_fixed.540870223
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.1483364377
Short name T661
Test name
Test status
Simulation time 159083409047 ps
CPU time 97.65 seconds
Started Mar 10 12:30:21 PM PDT 24
Finished Mar 10 12:31:59 PM PDT 24
Peak memory 201336 kb
Host smart-05bb3d78-08cd-40cd-8dbb-737e98119b2b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483364377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fix
ed.1483364377
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.185397409
Short name T600
Test name
Test status
Simulation time 351877668987 ps
CPU time 164.98 seconds
Started Mar 10 12:30:10 PM PDT 24
Finished Mar 10 12:32:55 PM PDT 24
Peak memory 201416 kb
Host smart-f43e4fbd-e9a6-45b2-866d-23c29849f2c9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185397409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_
wakeup.185397409
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.1249345176
Short name T397
Test name
Test status
Simulation time 599262994259 ps
CPU time 674.68 seconds
Started Mar 10 12:30:19 PM PDT 24
Finished Mar 10 12:41:34 PM PDT 24
Peak memory 201296 kb
Host smart-e39a53d1-3822-4b23-a0dc-f0fe2513e42b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249345176 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33
.adc_ctrl_filters_wakeup_fixed.1249345176
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.1638849528
Short name T452
Test name
Test status
Simulation time 121392536856 ps
CPU time 675.08 seconds
Started Mar 10 12:30:10 PM PDT 24
Finished Mar 10 12:41:26 PM PDT 24
Peak memory 201596 kb
Host smart-086a9333-1fd9-42ff-8f96-aa12fa873a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638849528 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.1638849528
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.2439738637
Short name T117
Test name
Test status
Simulation time 29721235925 ps
CPU time 62.28 seconds
Started Mar 10 12:30:23 PM PDT 24
Finished Mar 10 12:31:26 PM PDT 24
Peak memory 201320 kb
Host smart-796ec8a6-dc83-428a-91c3-0ae56e67095c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439738637 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.2439738637
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.2581057603
Short name T87
Test name
Test status
Simulation time 3630792926 ps
CPU time 9.13 seconds
Started Mar 10 12:30:09 PM PDT 24
Finished Mar 10 12:30:18 PM PDT 24
Peak memory 201236 kb
Host smart-9766730f-8cdc-4d3d-b654-b800b6e29cf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581057603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.2581057603
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.3485897268
Short name T787
Test name
Test status
Simulation time 5763063272 ps
CPU time 7.7 seconds
Started Mar 10 12:30:12 PM PDT 24
Finished Mar 10 12:30:19 PM PDT 24
Peak memory 201352 kb
Host smart-9217f86d-c8d1-4743-9acf-fa8570d4df47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485897268 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.3485897268
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.3679372962
Short name T605
Test name
Test status
Simulation time 35115852444 ps
CPU time 80.89 seconds
Started Mar 10 12:30:24 PM PDT 24
Finished Mar 10 12:31:45 PM PDT 24
Peak memory 209768 kb
Host smart-8b1cfe90-a40b-4ebd-b7d1-fbfff5aa6f17
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679372962 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.3679372962
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.2127730891
Short name T472
Test name
Test status
Simulation time 532833502 ps
CPU time 1.71 seconds
Started Mar 10 12:30:14 PM PDT 24
Finished Mar 10 12:30:16 PM PDT 24
Peak memory 201268 kb
Host smart-a765a80b-0993-4ee8-9312-10b474f9ec0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127730891 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.2127730891
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.2243998028
Short name T118
Test name
Test status
Simulation time 328176117905 ps
CPU time 738.76 seconds
Started Mar 10 12:30:12 PM PDT 24
Finished Mar 10 12:42:31 PM PDT 24
Peak memory 201380 kb
Host smart-cf812056-add4-4027-b92a-e7e10d64b4a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243998028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.2243998028
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.2551085222
Short name T729
Test name
Test status
Simulation time 332584113953 ps
CPU time 743.96 seconds
Started Mar 10 12:30:10 PM PDT 24
Finished Mar 10 12:42:34 PM PDT 24
Peak memory 201444 kb
Host smart-05487709-fa71-42c5-b416-2c693caa2965
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551085222 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interru
pt_fixed.2551085222
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.3703135791
Short name T717
Test name
Test status
Simulation time 161411599967 ps
CPU time 184.66 seconds
Started Mar 10 12:30:16 PM PDT 24
Finished Mar 10 12:33:21 PM PDT 24
Peak memory 201396 kb
Host smart-4682272f-e89a-45fe-ba02-9447d716e3f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703135791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.3703135791
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.1424975568
Short name T226
Test name
Test status
Simulation time 170002917804 ps
CPU time 86.98 seconds
Started Mar 10 12:30:10 PM PDT 24
Finished Mar 10 12:31:38 PM PDT 24
Peak memory 201512 kb
Host smart-46f4fa68-d2e6-43a8-b784-f28e184eae30
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424975568 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fix
ed.1424975568
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.2962680270
Short name T319
Test name
Test status
Simulation time 181891698070 ps
CPU time 430.77 seconds
Started Mar 10 12:30:24 PM PDT 24
Finished Mar 10 12:37:35 PM PDT 24
Peak memory 201328 kb
Host smart-c6316107-9e23-4c65-a72b-418e237c7320
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962680270 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters
_wakeup.2962680270
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.3324196810
Short name T623
Test name
Test status
Simulation time 208344849964 ps
CPU time 123.65 seconds
Started Mar 10 12:30:15 PM PDT 24
Finished Mar 10 12:32:18 PM PDT 24
Peak memory 201416 kb
Host smart-b8cd0e57-9a2a-4ae9-bfb5-3b2810729127
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324196810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.adc_ctrl_filters_wakeup_fixed.3324196810
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.3662941792
Short name T398
Test name
Test status
Simulation time 34185968664 ps
CPU time 20.63 seconds
Started Mar 10 12:30:25 PM PDT 24
Finished Mar 10 12:30:46 PM PDT 24
Peak memory 201260 kb
Host smart-1a301c40-14af-4f14-9e7e-cd4ed699c82b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662941792 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.3662941792
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.2141890774
Short name T591
Test name
Test status
Simulation time 3844313141 ps
CPU time 9.68 seconds
Started Mar 10 12:30:24 PM PDT 24
Finished Mar 10 12:30:34 PM PDT 24
Peak memory 201232 kb
Host smart-b31fe52d-4127-4198-91e0-d57baf1ce5a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141890774 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.2141890774
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.3836495054
Short name T414
Test name
Test status
Simulation time 5883157017 ps
CPU time 15.59 seconds
Started Mar 10 12:30:13 PM PDT 24
Finished Mar 10 12:30:29 PM PDT 24
Peak memory 201300 kb
Host smart-b55a5a68-4888-49a6-9bcc-b2ff87b31567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836495054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.3836495054
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.3787425534
Short name T196
Test name
Test status
Simulation time 146110757713 ps
CPU time 303.61 seconds
Started Mar 10 12:30:26 PM PDT 24
Finished Mar 10 12:35:30 PM PDT 24
Peak memory 209812 kb
Host smart-217c710f-d573-4680-a500-a9dcccd2e106
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787425534 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.3787425534
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.2125590104
Short name T437
Test name
Test status
Simulation time 422200946 ps
CPU time 0.87 seconds
Started Mar 10 12:33:16 PM PDT 24
Finished Mar 10 12:33:17 PM PDT 24
Peak memory 201188 kb
Host smart-f3e43afb-ba54-4e66-a173-bc465b16f8c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125590104 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.2125590104
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.2830359450
Short name T340
Test name
Test status
Simulation time 369398157219 ps
CPU time 189.93 seconds
Started Mar 10 12:30:21 PM PDT 24
Finished Mar 10 12:33:31 PM PDT 24
Peak memory 201420 kb
Host smart-5f707df5-ccb3-4476-9d50-b02faf77da48
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830359450 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gat
ing.2830359450
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.1892018753
Short name T339
Test name
Test status
Simulation time 352773152951 ps
CPU time 800.72 seconds
Started Mar 10 12:30:26 PM PDT 24
Finished Mar 10 12:43:47 PM PDT 24
Peak memory 201120 kb
Host smart-88f67541-97cd-4972-abe4-7efb7d44aa39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892018753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.1892018753
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.3885057946
Short name T221
Test name
Test status
Simulation time 490986337892 ps
CPU time 160.85 seconds
Started Mar 10 12:30:15 PM PDT 24
Finished Mar 10 12:32:56 PM PDT 24
Peak memory 201364 kb
Host smart-a28374e0-fe16-434d-a80d-ed4a0e373527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885057946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.3885057946
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.655630563
Short name T770
Test name
Test status
Simulation time 335347016447 ps
CPU time 773.09 seconds
Started Mar 10 12:30:27 PM PDT 24
Finished Mar 10 12:43:20 PM PDT 24
Peak memory 201396 kb
Host smart-63cd70bc-9edc-4f9a-bd34-74f11112eae3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=655630563 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrup
t_fixed.655630563
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.4236990894
Short name T189
Test name
Test status
Simulation time 326252761650 ps
CPU time 180.24 seconds
Started Mar 10 12:30:23 PM PDT 24
Finished Mar 10 12:33:24 PM PDT 24
Peak memory 201488 kb
Host smart-6f8207fa-a14e-4075-8b7e-7735ff631269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236990894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.4236990894
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.1177492906
Short name T504
Test name
Test status
Simulation time 499552278855 ps
CPU time 279.53 seconds
Started Mar 10 12:30:23 PM PDT 24
Finished Mar 10 12:35:03 PM PDT 24
Peak memory 201352 kb
Host smart-2312f18c-9719-4511-9924-5b946f1405cc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177492906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fix
ed.1177492906
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.1717545635
Short name T89
Test name
Test status
Simulation time 337681706449 ps
CPU time 89.99 seconds
Started Mar 10 12:30:23 PM PDT 24
Finished Mar 10 12:31:54 PM PDT 24
Peak memory 201360 kb
Host smart-e6883afe-a614-4627-96e5-6749a4343762
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717545635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters
_wakeup.1717545635
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.1011910541
Short name T685
Test name
Test status
Simulation time 600422738195 ps
CPU time 338.68 seconds
Started Mar 10 12:30:13 PM PDT 24
Finished Mar 10 12:35:52 PM PDT 24
Peak memory 201444 kb
Host smart-a91c4d2c-7c27-4904-b904-faa1ac2213a4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011910541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.adc_ctrl_filters_wakeup_fixed.1011910541
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.3083805104
Short name T249
Test name
Test status
Simulation time 115115767746 ps
CPU time 604.29 seconds
Started Mar 10 12:30:23 PM PDT 24
Finished Mar 10 12:40:28 PM PDT 24
Peak memory 201600 kb
Host smart-f24d08b8-eb99-4628-986b-5b4507cb5996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083805104 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.3083805104
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.354444887
Short name T773
Test name
Test status
Simulation time 39440353319 ps
CPU time 14.66 seconds
Started Mar 10 12:32:23 PM PDT 24
Finished Mar 10 12:32:37 PM PDT 24
Peak memory 201212 kb
Host smart-c17ad9b2-ec20-4779-a182-9bc74a01f272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354444887 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.354444887
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.294389854
Short name T558
Test name
Test status
Simulation time 3769555690 ps
CPU time 2.33 seconds
Started Mar 10 12:30:15 PM PDT 24
Finished Mar 10 12:30:18 PM PDT 24
Peak memory 201292 kb
Host smart-1370e758-fc8b-4ac1-b67a-1440e07d1dd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294389854 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.294389854
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.948846196
Short name T528
Test name
Test status
Simulation time 6061158222 ps
CPU time 3.96 seconds
Started Mar 10 12:30:15 PM PDT 24
Finished Mar 10 12:30:20 PM PDT 24
Peak memory 201228 kb
Host smart-26edaace-5242-4dca-a290-0ba2abc34a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948846196 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.948846196
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.2494092552
Short name T641
Test name
Test status
Simulation time 176825284700 ps
CPU time 105.31 seconds
Started Mar 10 12:30:28 PM PDT 24
Finished Mar 10 12:32:14 PM PDT 24
Peak memory 200388 kb
Host smart-44cbcc4c-8b56-4ef6-a994-bf598e9eaf19
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494092552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all
.2494092552
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.868030602
Short name T37
Test name
Test status
Simulation time 205556526844 ps
CPU time 105.54 seconds
Started Mar 10 12:32:22 PM PDT 24
Finished Mar 10 12:34:08 PM PDT 24
Peak memory 209724 kb
Host smart-ee078cfe-1a9e-4142-ad26-4239e41dc58e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868030602 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.868030602
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.1310719709
Short name T409
Test name
Test status
Simulation time 513827031 ps
CPU time 1.74 seconds
Started Mar 10 12:32:11 PM PDT 24
Finished Mar 10 12:32:13 PM PDT 24
Peak memory 201192 kb
Host smart-beecf157-9704-4d6d-9a32-3c9e8d77bc15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310719709 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.1310719709
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.1407373279
Short name T224
Test name
Test status
Simulation time 345151775169 ps
CPU time 797.38 seconds
Started Mar 10 12:30:32 PM PDT 24
Finished Mar 10 12:43:50 PM PDT 24
Peak memory 200664 kb
Host smart-5ef32464-a666-47ef-8565-b0579a72214b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407373279 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gat
ing.1407373279
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.3346323023
Short name T290
Test name
Test status
Simulation time 194457335332 ps
CPU time 231.15 seconds
Started Mar 10 12:30:26 PM PDT 24
Finished Mar 10 12:34:17 PM PDT 24
Peak memory 201404 kb
Host smart-0efc570d-7ff6-4e93-9529-f143e77e8d0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346323023 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.3346323023
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.597941990
Short name T321
Test name
Test status
Simulation time 324031838091 ps
CPU time 392.24 seconds
Started Mar 10 12:30:26 PM PDT 24
Finished Mar 10 12:36:58 PM PDT 24
Peak memory 201392 kb
Host smart-209ed067-3369-4c8c-a03a-2c406952b8ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597941990 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.597941990
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.1137915197
Short name T498
Test name
Test status
Simulation time 158473528448 ps
CPU time 103.31 seconds
Started Mar 10 12:30:24 PM PDT 24
Finished Mar 10 12:32:08 PM PDT 24
Peak memory 201512 kb
Host smart-d6e5816a-67be-452e-ada4-43ba3705782b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137915197 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interru
pt_fixed.1137915197
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.1552290936
Short name T726
Test name
Test status
Simulation time 496349390675 ps
CPU time 296.16 seconds
Started Mar 10 12:33:16 PM PDT 24
Finished Mar 10 12:38:12 PM PDT 24
Peak memory 201316 kb
Host smart-7f30acdc-bc00-4b1c-aec5-e410b846dff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552290936 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.1552290936
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.994999664
Short name T413
Test name
Test status
Simulation time 165372198327 ps
CPU time 391.82 seconds
Started Mar 10 12:30:24 PM PDT 24
Finished Mar 10 12:36:56 PM PDT 24
Peak memory 201304 kb
Host smart-0ca5138a-76ed-428a-bcf6-3c43f40e3f94
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=994999664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fixe
d.994999664
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.3633514401
Short name T267
Test name
Test status
Simulation time 584685645051 ps
CPU time 357.16 seconds
Started Mar 10 12:30:32 PM PDT 24
Finished Mar 10 12:36:29 PM PDT 24
Peak memory 200364 kb
Host smart-7ac364cd-55e1-4233-9065-e4a4fc7c8b25
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633514401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters
_wakeup.3633514401
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.104761478
Short name T38
Test name
Test status
Simulation time 595429646207 ps
CPU time 1260.26 seconds
Started Mar 10 12:30:27 PM PDT 24
Finished Mar 10 12:51:28 PM PDT 24
Peak memory 201408 kb
Host smart-8ca37eed-9949-436e-9794-534edfe80edb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104761478 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
adc_ctrl_filters_wakeup_fixed.104761478
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.1232156495
Short name T237
Test name
Test status
Simulation time 56807370102 ps
CPU time 230.56 seconds
Started Mar 10 12:30:24 PM PDT 24
Finished Mar 10 12:34:15 PM PDT 24
Peak memory 201744 kb
Host smart-8cf37387-3272-4b98-b48b-b689ce5ed9e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232156495 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.1232156495
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.1980434621
Short name T730
Test name
Test status
Simulation time 24251216285 ps
CPU time 52.74 seconds
Started Mar 10 12:30:24 PM PDT 24
Finished Mar 10 12:31:17 PM PDT 24
Peak memory 201380 kb
Host smart-91bfb456-62c3-4012-ade1-897bd7cbbdf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980434621 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.1980434621
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.3336598256
Short name T153
Test name
Test status
Simulation time 4229955772 ps
CPU time 1.78 seconds
Started Mar 10 12:30:24 PM PDT 24
Finished Mar 10 12:30:27 PM PDT 24
Peak memory 201288 kb
Host smart-42eab4de-39cb-4443-a7b4-8d94eecd3cd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336598256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.3336598256
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.1355703704
Short name T555
Test name
Test status
Simulation time 5712508369 ps
CPU time 4.11 seconds
Started Mar 10 12:32:22 PM PDT 24
Finished Mar 10 12:32:27 PM PDT 24
Peak memory 201256 kb
Host smart-f0ff81e0-18e3-4edb-bd21-7a6dec691af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355703704 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.1355703704
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.742034254
Short name T278
Test name
Test status
Simulation time 113319605993 ps
CPU time 259.33 seconds
Started Mar 10 12:30:25 PM PDT 24
Finished Mar 10 12:34:45 PM PDT 24
Peak memory 210044 kb
Host smart-7332f14d-4b7c-4466-b30d-2656c500638b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742034254 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.742034254
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.1597139324
Short name T45
Test name
Test status
Simulation time 522610503 ps
CPU time 0.89 seconds
Started Mar 10 12:30:28 PM PDT 24
Finished Mar 10 12:30:30 PM PDT 24
Peak memory 201380 kb
Host smart-39728a63-bca3-46f8-8f8a-d9b33cf32152
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597139324 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.1597139324
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.1071346856
Short name T203
Test name
Test status
Simulation time 165396141176 ps
CPU time 47.74 seconds
Started Mar 10 12:30:31 PM PDT 24
Finished Mar 10 12:31:19 PM PDT 24
Peak memory 201408 kb
Host smart-82bfcb01-dce9-4e4b-ba8a-e0534477de7f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071346856 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gat
ing.1071346856
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.2725345260
Short name T606
Test name
Test status
Simulation time 347465639718 ps
CPU time 232.6 seconds
Started Mar 10 12:30:29 PM PDT 24
Finished Mar 10 12:34:22 PM PDT 24
Peak memory 201340 kb
Host smart-11f4d79f-7897-44fe-99c5-ec150e68bafa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725345260 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.2725345260
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.215890356
Short name T183
Test name
Test status
Simulation time 327634058073 ps
CPU time 379.61 seconds
Started Mar 10 12:30:30 PM PDT 24
Finished Mar 10 12:36:50 PM PDT 24
Peak memory 201372 kb
Host smart-497f6970-3158-4bf0-8d8f-ded0c28e76da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215890356 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.215890356
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.1722584092
Short name T616
Test name
Test status
Simulation time 333238834331 ps
CPU time 305.64 seconds
Started Mar 10 12:30:30 PM PDT 24
Finished Mar 10 12:35:36 PM PDT 24
Peak memory 201484 kb
Host smart-fc85081a-7004-4b90-a4e4-0c0913893a9a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722584092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interru
pt_fixed.1722584092
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.1166253093
Short name T318
Test name
Test status
Simulation time 322040212119 ps
CPU time 190 seconds
Started Mar 10 12:30:29 PM PDT 24
Finished Mar 10 12:33:40 PM PDT 24
Peak memory 201420 kb
Host smart-fa9c170f-5b50-4f8f-aeae-8380c3b3012c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166253093 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.1166253093
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.43977467
Short name T135
Test name
Test status
Simulation time 488396939846 ps
CPU time 312.27 seconds
Started Mar 10 12:30:29 PM PDT 24
Finished Mar 10 12:35:41 PM PDT 24
Peak memory 201396 kb
Host smart-6975eb77-e2dc-4323-9cb0-93652485c24e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=43977467 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fixed
.43977467
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.1638656400
Short name T2
Test name
Test status
Simulation time 609655160507 ps
CPU time 319.25 seconds
Started Mar 10 12:30:30 PM PDT 24
Finished Mar 10 12:35:50 PM PDT 24
Peak memory 201436 kb
Host smart-babbdd6f-12b2-4872-9f94-ab89e461e88c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638656400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37
.adc_ctrl_filters_wakeup_fixed.1638656400
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.1893260519
Short name T56
Test name
Test status
Simulation time 89306946674 ps
CPU time 423.74 seconds
Started Mar 10 12:30:30 PM PDT 24
Finished Mar 10 12:37:34 PM PDT 24
Peak memory 201672 kb
Host smart-7259aa2f-976c-4755-87cc-4dd55d94bedd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893260519 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.1893260519
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.1227483521
Short name T210
Test name
Test status
Simulation time 38083524457 ps
CPU time 82.97 seconds
Started Mar 10 12:30:33 PM PDT 24
Finished Mar 10 12:31:56 PM PDT 24
Peak memory 201236 kb
Host smart-82472b5b-a838-4088-9d60-94f3223602cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227483521 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.1227483521
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.2591135450
Short name T539
Test name
Test status
Simulation time 5101855057 ps
CPU time 3.47 seconds
Started Mar 10 12:30:30 PM PDT 24
Finished Mar 10 12:30:33 PM PDT 24
Peak memory 201324 kb
Host smart-07c64320-dd76-4bc6-835a-9e817db83198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591135450 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.2591135450
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.3722539779
Short name T748
Test name
Test status
Simulation time 5689090074 ps
CPU time 14.06 seconds
Started Mar 10 12:30:30 PM PDT 24
Finished Mar 10 12:30:44 PM PDT 24
Peak memory 201352 kb
Host smart-6bc9f3cc-5e6d-469d-93dd-37935de56174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722539779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.3722539779
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.280768398
Short name T50
Test name
Test status
Simulation time 9742734903 ps
CPU time 20.7 seconds
Started Mar 10 12:30:31 PM PDT 24
Finished Mar 10 12:30:52 PM PDT 24
Peak memory 201592 kb
Host smart-5f3b3ba4-5625-48f5-8a85-6ba3a5d89310
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280768398 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.280768398
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.1719613908
Short name T445
Test name
Test status
Simulation time 462136017 ps
CPU time 1.63 seconds
Started Mar 10 12:30:39 PM PDT 24
Finished Mar 10 12:30:41 PM PDT 24
Peak memory 201264 kb
Host smart-6ea3b13b-d414-4073-a6a1-2d92ba94556c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719613908 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.1719613908
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.457850506
Short name T3
Test name
Test status
Simulation time 175114934306 ps
CPU time 398.19 seconds
Started Mar 10 12:30:35 PM PDT 24
Finished Mar 10 12:37:14 PM PDT 24
Peak memory 201440 kb
Host smart-04ade57f-61c3-4d8c-97be-bb553e600b83
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457850506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gati
ng.457850506
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.1782324973
Short name T127
Test name
Test status
Simulation time 333343511315 ps
CPU time 64.51 seconds
Started Mar 10 12:30:36 PM PDT 24
Finished Mar 10 12:31:40 PM PDT 24
Peak memory 201484 kb
Host smart-09be4b85-8d40-4322-bda2-4e38874a2bd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782324973 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.1782324973
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.2581637999
Short name T439
Test name
Test status
Simulation time 480407386630 ps
CPU time 565.73 seconds
Started Mar 10 12:30:34 PM PDT 24
Finished Mar 10 12:40:00 PM PDT 24
Peak memory 201376 kb
Host smart-742014f7-528c-4687-87b1-0fa519de4ad4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581637999 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interru
pt_fixed.2581637999
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.4151322598
Short name T231
Test name
Test status
Simulation time 330748514551 ps
CPU time 240.95 seconds
Started Mar 10 12:30:37 PM PDT 24
Finished Mar 10 12:34:38 PM PDT 24
Peak memory 201372 kb
Host smart-0cc1bfd8-41a1-4548-939d-c9ff3c3eaa01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151322598 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.4151322598
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.3522443318
Short name T731
Test name
Test status
Simulation time 326631375051 ps
CPU time 362.25 seconds
Started Mar 10 12:30:34 PM PDT 24
Finished Mar 10 12:36:37 PM PDT 24
Peak memory 201516 kb
Host smart-fe208e83-a009-4f08-aaa5-68fe302e5ad5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522443318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fix
ed.3522443318
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.260691863
Short name T342
Test name
Test status
Simulation time 179865163434 ps
CPU time 98.58 seconds
Started Mar 10 12:30:36 PM PDT 24
Finished Mar 10 12:32:15 PM PDT 24
Peak memory 201476 kb
Host smart-ca25a1ab-4d85-45f3-94b4-b84e7d903ca7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260691863 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_
wakeup.260691863
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.2143224696
Short name T6
Test name
Test status
Simulation time 400505181945 ps
CPU time 970.86 seconds
Started Mar 10 12:30:35 PM PDT 24
Finished Mar 10 12:46:46 PM PDT 24
Peak memory 201400 kb
Host smart-0a47a0d5-faec-4427-82f6-f81ed58c3bae
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143224696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.adc_ctrl_filters_wakeup_fixed.2143224696
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.2119143547
Short name T495
Test name
Test status
Simulation time 45883491792 ps
CPU time 9.4 seconds
Started Mar 10 12:30:36 PM PDT 24
Finished Mar 10 12:30:46 PM PDT 24
Peak memory 201320 kb
Host smart-668ef868-383e-432b-8f19-d055c656b424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119143547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.2119143547
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.416684000
Short name T592
Test name
Test status
Simulation time 2991325094 ps
CPU time 4.1 seconds
Started Mar 10 12:30:37 PM PDT 24
Finished Mar 10 12:30:42 PM PDT 24
Peak memory 201220 kb
Host smart-d74f62c4-7fea-40fc-bc74-2aceaee7987c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416684000 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.416684000
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.1300540247
Short name T400
Test name
Test status
Simulation time 5756601456 ps
CPU time 7.93 seconds
Started Mar 10 12:30:36 PM PDT 24
Finished Mar 10 12:30:44 PM PDT 24
Peak memory 201332 kb
Host smart-2933d0d1-1b22-4bcc-8bdb-9ee15877e1e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300540247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.1300540247
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.2988793868
Short name T68
Test name
Test status
Simulation time 350413714242 ps
CPU time 262.89 seconds
Started Mar 10 12:30:38 PM PDT 24
Finished Mar 10 12:35:01 PM PDT 24
Peak memory 201584 kb
Host smart-e4b82043-a9f7-4cbf-b9a0-8a27a3e823f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988793868 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.2988793868
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.3122146193
Short name T684
Test name
Test status
Simulation time 365671675 ps
CPU time 0.78 seconds
Started Mar 10 12:30:44 PM PDT 24
Finished Mar 10 12:30:45 PM PDT 24
Peak memory 201256 kb
Host smart-0dc4228d-e991-4e76-b261-aeb10a340c24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122146193 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.3122146193
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.599364143
Short name T672
Test name
Test status
Simulation time 334315412139 ps
CPU time 155.72 seconds
Started Mar 10 12:30:44 PM PDT 24
Finished Mar 10 12:33:20 PM PDT 24
Peak memory 201440 kb
Host smart-68e61c74-7dc9-4fd6-ad9a-856fc3f5e3c0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599364143 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gati
ng.599364143
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.1508124088
Short name T280
Test name
Test status
Simulation time 495088643695 ps
CPU time 206.36 seconds
Started Mar 10 12:30:44 PM PDT 24
Finished Mar 10 12:34:10 PM PDT 24
Peak memory 201308 kb
Host smart-3d503621-240c-4fd3-86aa-09fc76d35d1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508124088 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.1508124088
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.1054207301
Short name T288
Test name
Test status
Simulation time 481539249510 ps
CPU time 1059.8 seconds
Started Mar 10 12:30:39 PM PDT 24
Finished Mar 10 12:48:20 PM PDT 24
Peak memory 201808 kb
Host smart-3b8ced8a-17b6-4e0b-b1c9-f4ba60ee8c88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054207301 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.1054207301
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.2221762607
Short name T475
Test name
Test status
Simulation time 493914944990 ps
CPU time 284.64 seconds
Started Mar 10 12:30:47 PM PDT 24
Finished Mar 10 12:35:32 PM PDT 24
Peak memory 201360 kb
Host smart-900ecd84-2845-4ed1-9fa4-99f2088438e2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221762607 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interru
pt_fixed.2221762607
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.3197383057
Short name T230
Test name
Test status
Simulation time 328175079422 ps
CPU time 190.58 seconds
Started Mar 10 12:30:41 PM PDT 24
Finished Mar 10 12:33:52 PM PDT 24
Peak memory 201432 kb
Host smart-fa8cde07-2b9c-4bc8-838e-f85c731112a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197383057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.3197383057
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.49387036
Short name T679
Test name
Test status
Simulation time 330480747967 ps
CPU time 392.32 seconds
Started Mar 10 12:30:39 PM PDT 24
Finished Mar 10 12:37:12 PM PDT 24
Peak memory 201228 kb
Host smart-a9653174-11a4-4b98-98d2-65163cf70416
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=49387036 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fixed
.49387036
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.397478084
Short name T545
Test name
Test status
Simulation time 605050664149 ps
CPU time 1330.87 seconds
Started Mar 10 12:30:49 PM PDT 24
Finished Mar 10 12:53:01 PM PDT 24
Peak memory 201372 kb
Host smart-c6337487-9c4e-4888-97fa-a4968a543e6c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397478084 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
adc_ctrl_filters_wakeup_fixed.397478084
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.2745719717
Short name T248
Test name
Test status
Simulation time 108456322818 ps
CPU time 569.74 seconds
Started Mar 10 12:30:47 PM PDT 24
Finished Mar 10 12:40:17 PM PDT 24
Peak memory 201744 kb
Host smart-a0deb775-99bc-498e-85db-ef5836d9da2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745719717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.2745719717
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.1504499155
Short name T578
Test name
Test status
Simulation time 21806955749 ps
CPU time 14.47 seconds
Started Mar 10 12:30:46 PM PDT 24
Finished Mar 10 12:31:00 PM PDT 24
Peak memory 201280 kb
Host smart-09463205-15c9-488b-9d2e-3db4857e8cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504499155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.1504499155
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.2687127887
Short name T382
Test name
Test status
Simulation time 4784312739 ps
CPU time 1.93 seconds
Started Mar 10 12:30:46 PM PDT 24
Finished Mar 10 12:30:48 PM PDT 24
Peak memory 201328 kb
Host smart-6c53e0f7-62b3-4784-b906-25416a953b09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687127887 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.2687127887
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.2396077668
Short name T560
Test name
Test status
Simulation time 5653127188 ps
CPU time 1.66 seconds
Started Mar 10 12:30:41 PM PDT 24
Finished Mar 10 12:30:43 PM PDT 24
Peak memory 201268 kb
Host smart-195156e4-69bb-4f46-9af7-2916a9421098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396077668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.2396077668
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.2974513054
Short name T582
Test name
Test status
Simulation time 162031310591 ps
CPU time 42.4 seconds
Started Mar 10 12:30:45 PM PDT 24
Finished Mar 10 12:31:27 PM PDT 24
Peak memory 201424 kb
Host smart-811abf18-dbf8-4180-8046-5b0b65f4b8c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974513054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all
.2974513054
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.1549354771
Short name T102
Test name
Test status
Simulation time 656520293170 ps
CPU time 611.46 seconds
Started Mar 10 12:30:45 PM PDT 24
Finished Mar 10 12:40:57 PM PDT 24
Peak memory 210004 kb
Host smart-e69eb70a-e4c2-44a3-a470-755f8aa3b438
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549354771 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.1549354771
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.3982994015
Short name T664
Test name
Test status
Simulation time 362420514 ps
CPU time 1.02 seconds
Started Mar 10 12:29:19 PM PDT 24
Finished Mar 10 12:29:20 PM PDT 24
Peak memory 201184 kb
Host smart-9eabab24-dbf4-4cec-bb09-25a46048420f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982994015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.3982994015
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.1706251691
Short name T348
Test name
Test status
Simulation time 330526497994 ps
CPU time 115.73 seconds
Started Mar 10 12:29:08 PM PDT 24
Finished Mar 10 12:31:04 PM PDT 24
Peak memory 201260 kb
Host smart-11d5ffdc-b948-4768-937e-7305d94f637b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706251691 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gati
ng.1706251691
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.2676841373
Short name T542
Test name
Test status
Simulation time 330182792629 ps
CPU time 775.8 seconds
Started Mar 10 12:29:07 PM PDT 24
Finished Mar 10 12:42:03 PM PDT 24
Peak memory 201280 kb
Host smart-114c664b-2876-4f92-90af-bbd40406494c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676841373 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrup
t_fixed.2676841373
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.1049349846
Short name T174
Test name
Test status
Simulation time 494137743714 ps
CPU time 912.45 seconds
Started Mar 10 12:29:06 PM PDT 24
Finished Mar 10 12:44:19 PM PDT 24
Peak memory 201476 kb
Host smart-e61d0eb5-f55b-4b29-9db6-40c6d7eb9706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049349846 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.1049349846
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.2037534005
Short name T479
Test name
Test status
Simulation time 484974789845 ps
CPU time 609.48 seconds
Started Mar 10 12:29:01 PM PDT 24
Finished Mar 10 12:39:10 PM PDT 24
Peak memory 201340 kb
Host smart-8a7e7878-d355-4aa6-a001-07e4c2989299
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037534005 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixe
d.2037534005
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.631158422
Short name T161
Test name
Test status
Simulation time 567040471312 ps
CPU time 1391.63 seconds
Started Mar 10 12:29:04 PM PDT 24
Finished Mar 10 12:52:16 PM PDT 24
Peak memory 201528 kb
Host smart-5cd6b3f6-d4ed-4d30-a5b1-4c8b04a57281
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631158422 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_w
akeup.631158422
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.4188053818
Short name T92
Test name
Test status
Simulation time 582605609419 ps
CPU time 1373.27 seconds
Started Mar 10 12:29:02 PM PDT 24
Finished Mar 10 12:51:55 PM PDT 24
Peak memory 201392 kb
Host smart-884a29c1-bb8e-4d2b-ac6e-1836dd051129
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188053818 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
adc_ctrl_filters_wakeup_fixed.4188053818
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.2192506081
Short name T697
Test name
Test status
Simulation time 94084347413 ps
CPU time 401.47 seconds
Started Mar 10 12:29:06 PM PDT 24
Finished Mar 10 12:35:49 PM PDT 24
Peak memory 201744 kb
Host smart-6b5d6379-8dac-4b36-b875-b7712ef529a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192506081 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.2192506081
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.1230216343
Short name T427
Test name
Test status
Simulation time 29496895264 ps
CPU time 7.71 seconds
Started Mar 10 12:29:06 PM PDT 24
Finished Mar 10 12:29:14 PM PDT 24
Peak memory 201352 kb
Host smart-f4a45260-e9a7-4aed-8606-48f8ce4666a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230216343 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.1230216343
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.791557860
Short name T775
Test name
Test status
Simulation time 3918234249 ps
CPU time 6.19 seconds
Started Mar 10 12:28:59 PM PDT 24
Finished Mar 10 12:29:06 PM PDT 24
Peak memory 201316 kb
Host smart-17bf2626-3036-4bbd-a074-a653c6cfde26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791557860 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.791557860
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.486285022
Short name T73
Test name
Test status
Simulation time 4192389104 ps
CPU time 2.52 seconds
Started Mar 10 12:29:07 PM PDT 24
Finished Mar 10 12:29:10 PM PDT 24
Peak memory 216636 kb
Host smart-c2bf2e6d-bd7f-427c-b807-5466263218fa
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486285022 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.486285022
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.370768999
Short name T656
Test name
Test status
Simulation time 5702201730 ps
CPU time 2.76 seconds
Started Mar 10 12:29:00 PM PDT 24
Finished Mar 10 12:29:03 PM PDT 24
Peak memory 201404 kb
Host smart-3d1ad94a-3272-4918-b83e-7283d3f492e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370768999 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.370768999
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.2850203945
Short name T26
Test name
Test status
Simulation time 1010310842126 ps
CPU time 1143.5 seconds
Started Mar 10 12:29:07 PM PDT 24
Finished Mar 10 12:48:11 PM PDT 24
Peak memory 210060 kb
Host smart-9cae8c4a-9d36-41f2-9fd6-b1c3824edd0b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850203945 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.2850203945
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.770283993
Short name T767
Test name
Test status
Simulation time 401738762 ps
CPU time 0.67 seconds
Started Mar 10 12:30:50 PM PDT 24
Finished Mar 10 12:30:51 PM PDT 24
Peak memory 201280 kb
Host smart-8cf4f18e-c9f1-4abd-9bcc-1f2102e09491
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770283993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.770283993
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.1219135981
Short name T354
Test name
Test status
Simulation time 352596163530 ps
CPU time 761.66 seconds
Started Mar 10 12:30:50 PM PDT 24
Finished Mar 10 12:43:33 PM PDT 24
Peak memory 201588 kb
Host smart-3725e950-2ee8-421f-ac5c-635af6170856
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219135981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gat
ing.1219135981
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.3983384398
Short name T309
Test name
Test status
Simulation time 332278912094 ps
CPU time 584.77 seconds
Started Mar 10 12:30:51 PM PDT 24
Finished Mar 10 12:40:36 PM PDT 24
Peak memory 201396 kb
Host smart-91845caa-2a55-45be-aabe-e54319dee67d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983384398 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.3983384398
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.1565495534
Short name T758
Test name
Test status
Simulation time 332668824472 ps
CPU time 664.77 seconds
Started Mar 10 12:30:46 PM PDT 24
Finished Mar 10 12:41:51 PM PDT 24
Peak memory 201340 kb
Host smart-16fff113-da25-458f-a3f8-b3b27f4019b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565495534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.1565495534
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.2065057085
Short name T507
Test name
Test status
Simulation time 164259646313 ps
CPU time 98.81 seconds
Started Mar 10 12:30:45 PM PDT 24
Finished Mar 10 12:32:24 PM PDT 24
Peak memory 201524 kb
Host smart-3f1dc2fb-8de8-4289-8a6a-72f664b81784
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065057085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interru
pt_fixed.2065057085
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.1138811968
Short name T353
Test name
Test status
Simulation time 162879892361 ps
CPU time 363.47 seconds
Started Mar 10 12:30:46 PM PDT 24
Finished Mar 10 12:36:49 PM PDT 24
Peak memory 201428 kb
Host smart-1ece5ad8-137a-4f4c-9c01-1bfa382971aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138811968 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.1138811968
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.357112523
Short name T429
Test name
Test status
Simulation time 489743773057 ps
CPU time 301.38 seconds
Started Mar 10 12:30:47 PM PDT 24
Finished Mar 10 12:35:48 PM PDT 24
Peak memory 201280 kb
Host smart-d9f2b42a-3422-4525-8ccb-2b539e30f341
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=357112523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fixe
d.357112523
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.1241238986
Short name T277
Test name
Test status
Simulation time 184906174652 ps
CPU time 199.2 seconds
Started Mar 10 12:30:50 PM PDT 24
Finished Mar 10 12:34:09 PM PDT 24
Peak memory 201428 kb
Host smart-c90d97ba-36b3-4ff5-9e2c-2a8718e08dd6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241238986 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters
_wakeup.1241238986
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.1308428660
Short name T167
Test name
Test status
Simulation time 610400152548 ps
CPU time 1373.77 seconds
Started Mar 10 12:30:50 PM PDT 24
Finished Mar 10 12:53:44 PM PDT 24
Peak memory 201356 kb
Host smart-1af601c4-8a2d-465c-bd52-c3e5d7fdd110
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308428660 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.adc_ctrl_filters_wakeup_fixed.1308428660
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.1196598343
Short name T378
Test name
Test status
Simulation time 98116909372 ps
CPU time 390.17 seconds
Started Mar 10 12:30:50 PM PDT 24
Finished Mar 10 12:37:21 PM PDT 24
Peak memory 201664 kb
Host smart-5e26707c-25b7-43a5-b4cf-0313cfa5e5ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196598343 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.1196598343
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.3443180383
Short name T494
Test name
Test status
Simulation time 22212947067 ps
CPU time 14.03 seconds
Started Mar 10 12:30:49 PM PDT 24
Finished Mar 10 12:31:03 PM PDT 24
Peak memory 201352 kb
Host smart-9766885b-ea5f-4ed6-8107-929b5e5e82e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443180383 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.3443180383
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.1114638540
Short name T422
Test name
Test status
Simulation time 4025358157 ps
CPU time 4.32 seconds
Started Mar 10 12:30:50 PM PDT 24
Finished Mar 10 12:30:55 PM PDT 24
Peak memory 201256 kb
Host smart-cc1e1c84-6e9c-42ef-81ef-061221541371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114638540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.1114638540
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.1225421744
Short name T404
Test name
Test status
Simulation time 5914025336 ps
CPU time 14.8 seconds
Started Mar 10 12:30:50 PM PDT 24
Finished Mar 10 12:31:06 PM PDT 24
Peak memory 201024 kb
Host smart-9f9fc712-2585-4621-963f-c9fab25872da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225421744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.1225421744
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.196840757
Short name T320
Test name
Test status
Simulation time 170926970803 ps
CPU time 193.59 seconds
Started Mar 10 12:30:51 PM PDT 24
Finished Mar 10 12:34:04 PM PDT 24
Peak memory 201444 kb
Host smart-7e4379f1-082e-4588-a850-3021ef31c4eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196840757 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all.
196840757
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.3897787328
Short name T8
Test name
Test status
Simulation time 17256975461 ps
CPU time 42.88 seconds
Started Mar 10 12:30:51 PM PDT 24
Finished Mar 10 12:31:34 PM PDT 24
Peak memory 201560 kb
Host smart-fe330e00-c94b-464b-9f78-5d0e0e1406ac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897787328 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.3897787328
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.4162726976
Short name T120
Test name
Test status
Simulation time 345776417 ps
CPU time 0.79 seconds
Started Mar 10 12:30:56 PM PDT 24
Finished Mar 10 12:30:57 PM PDT 24
Peak memory 201316 kb
Host smart-c24c2582-768a-4092-b197-b39446f64641
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162726976 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.4162726976
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.1498317747
Short name T253
Test name
Test status
Simulation time 327655306753 ps
CPU time 200.95 seconds
Started Mar 10 12:30:56 PM PDT 24
Finished Mar 10 12:34:17 PM PDT 24
Peak memory 201424 kb
Host smart-7187c347-b077-4ecc-b485-aa861ae9f18b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498317747 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gat
ing.1498317747
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.2646346983
Short name T705
Test name
Test status
Simulation time 169977790935 ps
CPU time 94.78 seconds
Started Mar 10 12:30:58 PM PDT 24
Finished Mar 10 12:32:33 PM PDT 24
Peak memory 201432 kb
Host smart-9577da07-32a8-4292-8ebe-70ffea25838e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646346983 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.2646346983
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.3611803285
Short name T169
Test name
Test status
Simulation time 334907062829 ps
CPU time 104.91 seconds
Started Mar 10 12:30:50 PM PDT 24
Finished Mar 10 12:32:35 PM PDT 24
Peak memory 201348 kb
Host smart-a38f6c97-542f-4f41-9ddc-5f499cb05439
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611803285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interru
pt_fixed.3611803285
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.1698572180
Short name T562
Test name
Test status
Simulation time 163847551652 ps
CPU time 356.76 seconds
Started Mar 10 12:30:56 PM PDT 24
Finished Mar 10 12:36:52 PM PDT 24
Peak memory 201380 kb
Host smart-db363d94-4279-4061-bc5b-1545c56006aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698572180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.1698572180
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.1718795107
Short name T725
Test name
Test status
Simulation time 168707516466 ps
CPU time 403.29 seconds
Started Mar 10 12:30:55 PM PDT 24
Finished Mar 10 12:37:39 PM PDT 24
Peak memory 201312 kb
Host smart-b73a4f3b-8f6a-4a1b-9ceb-07fd1cef435c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718795107 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fix
ed.1718795107
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.3588174632
Short name T205
Test name
Test status
Simulation time 349308209726 ps
CPU time 204.01 seconds
Started Mar 10 12:30:52 PM PDT 24
Finished Mar 10 12:34:16 PM PDT 24
Peak memory 201332 kb
Host smart-115152fd-d4bd-42ad-bf32-1c55e5f6e8d9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588174632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters
_wakeup.3588174632
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.1536084007
Short name T599
Test name
Test status
Simulation time 607706594392 ps
CPU time 1454.63 seconds
Started Mar 10 12:30:50 PM PDT 24
Finished Mar 10 12:55:05 PM PDT 24
Peak memory 201580 kb
Host smart-d86a1b52-dcd9-4bc0-a58a-b765c3a062d0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536084007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41
.adc_ctrl_filters_wakeup_fixed.1536084007
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.3322664501
Short name T246
Test name
Test status
Simulation time 131482770209 ps
CPU time 710.38 seconds
Started Mar 10 12:30:56 PM PDT 24
Finished Mar 10 12:42:46 PM PDT 24
Peak memory 201688 kb
Host smart-6449e8c2-8dcc-4d42-9ae0-180e96b33f98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322664501 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.3322664501
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.966955991
Short name T784
Test name
Test status
Simulation time 36796917618 ps
CPU time 24.61 seconds
Started Mar 10 12:30:58 PM PDT 24
Finished Mar 10 12:31:23 PM PDT 24
Peak memory 201212 kb
Host smart-53f50325-4be2-4602-ad47-89673200f532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966955991 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.966955991
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.1376948209
Short name T579
Test name
Test status
Simulation time 3240088515 ps
CPU time 4.77 seconds
Started Mar 10 12:30:55 PM PDT 24
Finished Mar 10 12:31:00 PM PDT 24
Peak memory 201324 kb
Host smart-36cdfa35-a19d-4ba1-8719-dabda6c85c27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376948209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.1376948209
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.1831913753
Short name T675
Test name
Test status
Simulation time 6035859859 ps
CPU time 4.59 seconds
Started Mar 10 12:30:50 PM PDT 24
Finished Mar 10 12:30:55 PM PDT 24
Peak memory 201352 kb
Host smart-ce019a40-20e3-4663-80a0-dce1953556ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831913753 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.1831913753
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.3943407462
Short name T330
Test name
Test status
Simulation time 583213136907 ps
CPU time 499.8 seconds
Started Mar 10 12:30:55 PM PDT 24
Finished Mar 10 12:39:15 PM PDT 24
Peak memory 210076 kb
Host smart-ac9ccb6c-e02b-490a-8839-f2a1b0168a9f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943407462 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.3943407462
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.2073022252
Short name T513
Test name
Test status
Simulation time 433409748 ps
CPU time 1.1 seconds
Started Mar 10 12:31:08 PM PDT 24
Finished Mar 10 12:31:10 PM PDT 24
Peak memory 201192 kb
Host smart-52dcb1d2-87db-47a1-910f-22b35b2946eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073022252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.2073022252
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.3147019464
Short name T289
Test name
Test status
Simulation time 468824795411 ps
CPU time 663.84 seconds
Started Mar 10 12:30:58 PM PDT 24
Finished Mar 10 12:42:02 PM PDT 24
Peak memory 201320 kb
Host smart-e69f2765-cb32-4668-9bb9-cdef9877d54a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147019464 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gat
ing.3147019464
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.3922256557
Short name T509
Test name
Test status
Simulation time 162813167712 ps
CPU time 57.91 seconds
Started Mar 10 12:30:55 PM PDT 24
Finished Mar 10 12:31:54 PM PDT 24
Peak memory 201352 kb
Host smart-bff267d0-b8ed-4d4a-a22d-56d34ad73146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922256557 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.3922256557
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.1808396350
Short name T130
Test name
Test status
Simulation time 328152162638 ps
CPU time 193.96 seconds
Started Mar 10 12:30:58 PM PDT 24
Finished Mar 10 12:34:12 PM PDT 24
Peak memory 201472 kb
Host smart-9f73d156-f943-4843-bedf-d91a8a4e9b50
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808396350 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interru
pt_fixed.1808396350
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.1675994063
Short name T202
Test name
Test status
Simulation time 159512547461 ps
CPU time 96.75 seconds
Started Mar 10 12:30:56 PM PDT 24
Finished Mar 10 12:32:32 PM PDT 24
Peak memory 201372 kb
Host smart-00cb178c-d6d7-44c2-bdb1-9b6e11a40c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675994063 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.1675994063
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.2609082911
Short name T601
Test name
Test status
Simulation time 327349322002 ps
CPU time 226.33 seconds
Started Mar 10 12:30:56 PM PDT 24
Finished Mar 10 12:34:43 PM PDT 24
Peak memory 201312 kb
Host smart-2f2ad295-e1ad-4005-8e99-75e1f1cf290e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609082911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fix
ed.2609082911
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.3926360659
Short name T86
Test name
Test status
Simulation time 586329066315 ps
CPU time 1291.29 seconds
Started Mar 10 12:30:58 PM PDT 24
Finished Mar 10 12:52:30 PM PDT 24
Peak memory 201392 kb
Host smart-17b367cf-fc6e-4c37-a0b9-1548edd40b6e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926360659 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters
_wakeup.3926360659
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.175459573
Short name T651
Test name
Test status
Simulation time 609434270340 ps
CPU time 349.04 seconds
Started Mar 10 12:30:54 PM PDT 24
Finished Mar 10 12:36:45 PM PDT 24
Peak memory 201460 kb
Host smart-00a936ae-7995-4fbe-baa8-ab58150c07ff
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175459573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
adc_ctrl_filters_wakeup_fixed.175459573
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.1058328623
Short name T370
Test name
Test status
Simulation time 100686208928 ps
CPU time 375.48 seconds
Started Mar 10 12:31:01 PM PDT 24
Finished Mar 10 12:37:17 PM PDT 24
Peak memory 201572 kb
Host smart-864ad281-758b-4b82-9063-a7b1bc3af4c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058328623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.1058328623
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.2863770898
Short name T450
Test name
Test status
Simulation time 40910585878 ps
CPU time 27.02 seconds
Started Mar 10 12:30:56 PM PDT 24
Finished Mar 10 12:31:23 PM PDT 24
Peak memory 201316 kb
Host smart-d8bc3b02-e452-4a7b-a213-3b420c88175c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863770898 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.2863770898
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.1736574211
Short name T752
Test name
Test status
Simulation time 5187935561 ps
CPU time 3.8 seconds
Started Mar 10 12:30:56 PM PDT 24
Finished Mar 10 12:31:00 PM PDT 24
Peak memory 201376 kb
Host smart-e040527d-d05a-455e-a474-5101f9616342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736574211 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.1736574211
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.2206256952
Short name T632
Test name
Test status
Simulation time 5639566444 ps
CPU time 4.11 seconds
Started Mar 10 12:30:58 PM PDT 24
Finished Mar 10 12:31:02 PM PDT 24
Peak memory 201244 kb
Host smart-a89b5c82-6941-445d-a79f-44087a4986a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206256952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.2206256952
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.1018218211
Short name T41
Test name
Test status
Simulation time 271868256943 ps
CPU time 618.93 seconds
Started Mar 10 12:31:02 PM PDT 24
Finished Mar 10 12:41:21 PM PDT 24
Peak memory 201732 kb
Host smart-5f18499b-503e-407a-846f-9ba408320b2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018218211 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all
.1018218211
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.3768064285
Short name T636
Test name
Test status
Simulation time 397446835231 ps
CPU time 125.45 seconds
Started Mar 10 12:31:05 PM PDT 24
Finished Mar 10 12:33:11 PM PDT 24
Peak memory 201360 kb
Host smart-a50eef61-f4fc-4755-bc2a-0b5830244aac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768064285 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.3768064285
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.2775259392
Short name T200
Test name
Test status
Simulation time 358132690 ps
CPU time 0.82 seconds
Started Mar 10 12:31:04 PM PDT 24
Finished Mar 10 12:31:05 PM PDT 24
Peak memory 201260 kb
Host smart-a7a3db6e-815d-405b-b010-385e6d9353a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775259392 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.2775259392
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.3097915645
Short name T296
Test name
Test status
Simulation time 511190756535 ps
CPU time 147.04 seconds
Started Mar 10 12:31:01 PM PDT 24
Finished Mar 10 12:33:28 PM PDT 24
Peak memory 201396 kb
Host smart-ce834812-61e1-473b-8c6e-bc35e5955f88
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097915645 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gat
ing.3097915645
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.1326661881
Short name T573
Test name
Test status
Simulation time 248521020477 ps
CPU time 113.47 seconds
Started Mar 10 12:31:01 PM PDT 24
Finished Mar 10 12:32:55 PM PDT 24
Peak memory 201412 kb
Host smart-fd28697d-4547-4e78-8789-d3714d37927e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326661881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.1326661881
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.2741230173
Short name T561
Test name
Test status
Simulation time 485241349760 ps
CPU time 315.45 seconds
Started Mar 10 12:31:01 PM PDT 24
Finished Mar 10 12:36:17 PM PDT 24
Peak memory 201408 kb
Host smart-60c0513a-efc9-400b-8893-615f827a358b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741230173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.2741230173
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.2785361950
Short name T383
Test name
Test status
Simulation time 483156662302 ps
CPU time 1176.2 seconds
Started Mar 10 12:31:04 PM PDT 24
Finished Mar 10 12:50:40 PM PDT 24
Peak memory 201460 kb
Host smart-f3849973-75a5-4326-9768-476c3575007d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785361950 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interru
pt_fixed.2785361950
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.233330966
Short name T454
Test name
Test status
Simulation time 164136885586 ps
CPU time 403.72 seconds
Started Mar 10 12:31:02 PM PDT 24
Finished Mar 10 12:37:46 PM PDT 24
Peak memory 201536 kb
Host smart-5f759902-dbe4-48a6-b5b2-ab4cd0b201eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233330966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.233330966
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.2419772740
Short name T417
Test name
Test status
Simulation time 325395263376 ps
CPU time 403.76 seconds
Started Mar 10 12:31:02 PM PDT 24
Finished Mar 10 12:37:46 PM PDT 24
Peak memory 201352 kb
Host smart-c62b48dc-05a2-4bd6-82ce-ba33b13f4f3d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419772740 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fix
ed.2419772740
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.2158699065
Short name T295
Test name
Test status
Simulation time 346854438068 ps
CPU time 755.57 seconds
Started Mar 10 12:31:05 PM PDT 24
Finished Mar 10 12:43:41 PM PDT 24
Peak memory 201180 kb
Host smart-cd31b7fd-3a9a-46da-957d-575f29ff13ec
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158699065 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters
_wakeup.2158699065
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.3445547570
Short name T458
Test name
Test status
Simulation time 391711329202 ps
CPU time 875.53 seconds
Started Mar 10 12:31:05 PM PDT 24
Finished Mar 10 12:45:41 PM PDT 24
Peak memory 201476 kb
Host smart-0eb43a57-4004-4f2c-b3af-0d605ad241c9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445547570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43
.adc_ctrl_filters_wakeup_fixed.3445547570
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.988040860
Short name T487
Test name
Test status
Simulation time 105512103910 ps
CPU time 444.6 seconds
Started Mar 10 12:31:01 PM PDT 24
Finished Mar 10 12:38:26 PM PDT 24
Peak memory 201644 kb
Host smart-7e8ed644-53f3-4186-89ca-041df1624f4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988040860 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.988040860
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.3463603880
Short name T516
Test name
Test status
Simulation time 35243426866 ps
CPU time 81.67 seconds
Started Mar 10 12:31:01 PM PDT 24
Finished Mar 10 12:32:23 PM PDT 24
Peak memory 201312 kb
Host smart-c76bebea-ac3a-42c3-b242-a4965721e93c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463603880 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.3463603880
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.3621034168
Short name T33
Test name
Test status
Simulation time 3590543005 ps
CPU time 2.63 seconds
Started Mar 10 12:31:04 PM PDT 24
Finished Mar 10 12:31:07 PM PDT 24
Peak memory 201372 kb
Host smart-c538f573-0986-4a63-8530-0cc970fbef3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621034168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.3621034168
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.1103839887
Short name T532
Test name
Test status
Simulation time 5975870737 ps
CPU time 4.26 seconds
Started Mar 10 12:31:09 PM PDT 24
Finished Mar 10 12:31:13 PM PDT 24
Peak memory 201260 kb
Host smart-68c1218f-4527-4563-b919-992d89579d4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103839887 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.1103839887
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.1292078189
Short name T208
Test name
Test status
Simulation time 209883107187 ps
CPU time 251.83 seconds
Started Mar 10 12:31:03 PM PDT 24
Finished Mar 10 12:35:15 PM PDT 24
Peak memory 201376 kb
Host smart-0003b4ce-80d0-4a0a-9eda-651bd4f8612d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292078189 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all
.1292078189
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.4273828921
Short name T53
Test name
Test status
Simulation time 115359668413 ps
CPU time 264.48 seconds
Started Mar 10 12:31:05 PM PDT 24
Finished Mar 10 12:35:29 PM PDT 24
Peak memory 209692 kb
Host smart-7678ea06-fa8f-4933-8a18-c4567dfdf92e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273828921 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.4273828921
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.3078822948
Short name T111
Test name
Test status
Simulation time 412387796 ps
CPU time 1.5 seconds
Started Mar 10 12:31:10 PM PDT 24
Finished Mar 10 12:31:12 PM PDT 24
Peak memory 201196 kb
Host smart-dddaffec-5b60-4658-a413-9bfda2c80a2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078822948 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.3078822948
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.1589766171
Short name T313
Test name
Test status
Simulation time 322549380111 ps
CPU time 728.17 seconds
Started Mar 10 12:31:17 PM PDT 24
Finished Mar 10 12:43:25 PM PDT 24
Peak memory 201388 kb
Host smart-09541fa8-bf6a-4db4-9cc5-c175df7c83ce
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589766171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gat
ing.1589766171
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.2772207674
Short name T718
Test name
Test status
Simulation time 494165899538 ps
CPU time 543.39 seconds
Started Mar 10 12:31:07 PM PDT 24
Finished Mar 10 12:40:10 PM PDT 24
Peak memory 201500 kb
Host smart-daf4e706-99cb-4d50-a7af-cbfccabeaba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772207674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.2772207674
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.3588905121
Short name T188
Test name
Test status
Simulation time 323998311324 ps
CPU time 476.35 seconds
Started Mar 10 12:31:12 PM PDT 24
Finished Mar 10 12:39:08 PM PDT 24
Peak memory 201352 kb
Host smart-03710ca1-be3f-4f86-9cfd-5101d5e57898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588905121 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.3588905121
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.1976452433
Short name T496
Test name
Test status
Simulation time 162398681259 ps
CPU time 106.9 seconds
Started Mar 10 12:31:08 PM PDT 24
Finished Mar 10 12:32:55 PM PDT 24
Peak memory 201452 kb
Host smart-674e1237-9597-4a34-ab56-9cc277589190
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976452433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interru
pt_fixed.1976452433
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.698626338
Short name T658
Test name
Test status
Simulation time 163380612298 ps
CPU time 398.66 seconds
Started Mar 10 12:31:15 PM PDT 24
Finished Mar 10 12:37:53 PM PDT 24
Peak memory 201336 kb
Host smart-ec0aefa0-7c2e-4721-8953-f4df4d5c6450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698626338 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.698626338
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.1376395155
Short name T491
Test name
Test status
Simulation time 158646171199 ps
CPU time 165.62 seconds
Started Mar 10 12:31:02 PM PDT 24
Finished Mar 10 12:33:48 PM PDT 24
Peak memory 201352 kb
Host smart-6a127186-7363-41ca-b9d8-97a137f1235a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376395155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fix
ed.1376395155
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.270773419
Short name T268
Test name
Test status
Simulation time 569481187320 ps
CPU time 1341.78 seconds
Started Mar 10 12:31:08 PM PDT 24
Finished Mar 10 12:53:29 PM PDT 24
Peak memory 201376 kb
Host smart-f0933bf1-8725-4cb7-a9a3-a3f9f4b1c011
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270773419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_
wakeup.270773419
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.612997449
Short name T700
Test name
Test status
Simulation time 200567102995 ps
CPU time 115.36 seconds
Started Mar 10 12:31:09 PM PDT 24
Finished Mar 10 12:33:04 PM PDT 24
Peak memory 201352 kb
Host smart-6802eae5-faa0-4bc8-be3a-b5922a938633
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612997449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
adc_ctrl_filters_wakeup_fixed.612997449
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.3453928886
Short name T242
Test name
Test status
Simulation time 97523356715 ps
CPU time 326.29 seconds
Started Mar 10 12:31:07 PM PDT 24
Finished Mar 10 12:36:33 PM PDT 24
Peak memory 201692 kb
Host smart-18124fee-fd3d-49b0-a4bf-4d5a2021eb81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453928886 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.3453928886
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.1324679151
Short name T5
Test name
Test status
Simulation time 32655264210 ps
CPU time 21.55 seconds
Started Mar 10 12:31:07 PM PDT 24
Finished Mar 10 12:31:28 PM PDT 24
Peak memory 201400 kb
Host smart-e0406138-9b1f-43bd-9e70-359cd7a3d7b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324679151 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.1324679151
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.2206696078
Short name T782
Test name
Test status
Simulation time 4045867116 ps
CPU time 8.85 seconds
Started Mar 10 12:31:05 PM PDT 24
Finished Mar 10 12:31:14 PM PDT 24
Peak memory 201288 kb
Host smart-1b4bda7c-1203-47c7-818d-ae282878193e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206696078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.2206696078
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.2391178931
Short name T225
Test name
Test status
Simulation time 6108319154 ps
CPU time 13.78 seconds
Started Mar 10 12:31:03 PM PDT 24
Finished Mar 10 12:31:17 PM PDT 24
Peak memory 201280 kb
Host smart-96b2620a-cf2f-4770-b6a2-21e73a8ddc95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391178931 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.2391178931
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.1285246112
Short name T777
Test name
Test status
Simulation time 519374375047 ps
CPU time 608.9 seconds
Started Mar 10 12:31:14 PM PDT 24
Finished Mar 10 12:41:23 PM PDT 24
Peak memory 201420 kb
Host smart-5b73efb3-8ae3-4ff8-8df4-d013fe605fdf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285246112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all
.1285246112
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.3853644778
Short name T67
Test name
Test status
Simulation time 71208447205 ps
CPU time 152.1 seconds
Started Mar 10 12:31:05 PM PDT 24
Finished Mar 10 12:33:38 PM PDT 24
Peak memory 209816 kb
Host smart-d5b9aa05-70f3-4ca2-8eb7-69fdd5f2547e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853644778 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.3853644778
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.2765290828
Short name T764
Test name
Test status
Simulation time 307372171 ps
CPU time 0.94 seconds
Started Mar 10 12:31:17 PM PDT 24
Finished Mar 10 12:31:18 PM PDT 24
Peak memory 201220 kb
Host smart-3bf31c47-9020-4350-8cc8-9cf8ece0b9ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765290828 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.2765290828
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.685217335
Short name T129
Test name
Test status
Simulation time 521576837773 ps
CPU time 126.67 seconds
Started Mar 10 12:31:20 PM PDT 24
Finished Mar 10 12:33:27 PM PDT 24
Peak memory 201436 kb
Host smart-12f3e30b-99bb-4109-a875-07e1bf19ed1a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685217335 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gati
ng.685217335
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.791342038
Short name T273
Test name
Test status
Simulation time 165618314152 ps
CPU time 260.18 seconds
Started Mar 10 12:31:14 PM PDT 24
Finished Mar 10 12:35:34 PM PDT 24
Peak memory 201392 kb
Host smart-ac38e3da-7117-4ca7-8305-c56f08afcb55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791342038 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.791342038
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.1650265685
Short name T693
Test name
Test status
Simulation time 171243580530 ps
CPU time 403.45 seconds
Started Mar 10 12:31:11 PM PDT 24
Finished Mar 10 12:37:55 PM PDT 24
Peak memory 201368 kb
Host smart-d01382e6-3635-40c3-9f10-a79715fd86d5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650265685 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interru
pt_fixed.1650265685
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.1288626268
Short name T671
Test name
Test status
Simulation time 345011805489 ps
CPU time 160.68 seconds
Started Mar 10 12:31:12 PM PDT 24
Finished Mar 10 12:33:53 PM PDT 24
Peak memory 201520 kb
Host smart-49bee34b-8a0f-4253-9a1d-a7587acb9cb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288626268 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.1288626268
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.600867585
Short name T571
Test name
Test status
Simulation time 160237628581 ps
CPU time 188.36 seconds
Started Mar 10 12:31:10 PM PDT 24
Finished Mar 10 12:34:18 PM PDT 24
Peak memory 201420 kb
Host smart-3281546c-6619-4bbd-a06d-4582233877e9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=600867585 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fixe
d.600867585
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.1854585841
Short name T270
Test name
Test status
Simulation time 384687796783 ps
CPU time 930.31 seconds
Started Mar 10 12:31:11 PM PDT 24
Finished Mar 10 12:46:42 PM PDT 24
Peak memory 201368 kb
Host smart-f80820c3-9900-4ade-a152-8f4094e25b73
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854585841 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters
_wakeup.1854585841
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.2432985915
Short name T619
Test name
Test status
Simulation time 592027907268 ps
CPU time 1408.6 seconds
Started Mar 10 12:31:20 PM PDT 24
Finished Mar 10 12:54:49 PM PDT 24
Peak memory 201444 kb
Host smart-908a6878-3378-4b15-a9a0-4feb90638921
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432985915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.adc_ctrl_filters_wakeup_fixed.2432985915
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.2653398973
Short name T369
Test name
Test status
Simulation time 125884619730 ps
CPU time 647.35 seconds
Started Mar 10 12:31:17 PM PDT 24
Finished Mar 10 12:42:05 PM PDT 24
Peak memory 201676 kb
Host smart-e77a2246-6609-4753-9e85-b29828f88f2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653398973 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.2653398973
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.2317920568
Short name T104
Test name
Test status
Simulation time 40893197262 ps
CPU time 92.22 seconds
Started Mar 10 12:31:18 PM PDT 24
Finished Mar 10 12:32:50 PM PDT 24
Peak memory 201324 kb
Host smart-31c96126-3245-404a-9a15-b4d584d9ba1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317920568 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.2317920568
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.2728472269
Short name T389
Test name
Test status
Simulation time 4008330094 ps
CPU time 2.5 seconds
Started Mar 10 12:31:16 PM PDT 24
Finished Mar 10 12:31:18 PM PDT 24
Peak memory 201416 kb
Host smart-c4a2e2e5-16f0-4675-b037-f6f4b6ad4201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728472269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.2728472269
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.1438010467
Short name T574
Test name
Test status
Simulation time 5904746733 ps
CPU time 15 seconds
Started Mar 10 12:31:11 PM PDT 24
Finished Mar 10 12:31:26 PM PDT 24
Peak memory 201324 kb
Host smart-afcb0900-3cab-4ccc-9647-d4158e6d80fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438010467 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.1438010467
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.2348100758
Short name T334
Test name
Test status
Simulation time 329829542635 ps
CPU time 49.72 seconds
Started Mar 10 12:31:17 PM PDT 24
Finished Mar 10 12:32:07 PM PDT 24
Peak memory 201504 kb
Host smart-80071133-5215-4b29-8a12-3c1dc6eb1f21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348100758 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all
.2348100758
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.922558060
Short name T471
Test name
Test status
Simulation time 207530351581 ps
CPU time 130.95 seconds
Started Mar 10 12:31:17 PM PDT 24
Finished Mar 10 12:33:29 PM PDT 24
Peak memory 209980 kb
Host smart-fd7f1e2a-0335-46b7-b754-970e48eb6d25
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922558060 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.922558060
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.1538091889
Short name T534
Test name
Test status
Simulation time 327702068 ps
CPU time 0.8 seconds
Started Mar 10 12:39:16 PM PDT 24
Finished Mar 10 12:39:17 PM PDT 24
Peak memory 201312 kb
Host smart-f6e78edb-1c1e-4d21-9b1c-0ccf325cfc89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538091889 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.1538091889
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.390018355
Short name T739
Test name
Test status
Simulation time 167731379194 ps
CPU time 396.14 seconds
Started Mar 10 12:31:28 PM PDT 24
Finished Mar 10 12:38:05 PM PDT 24
Peak memory 201392 kb
Host smart-f203b2db-0ac9-4934-b5a5-2516ee27d2d6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390018355 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gati
ng.390018355
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.4247754369
Short name T720
Test name
Test status
Simulation time 293209539808 ps
CPU time 125.97 seconds
Started Mar 10 12:31:23 PM PDT 24
Finished Mar 10 12:33:29 PM PDT 24
Peak memory 201432 kb
Host smart-27086366-1523-4d11-af0c-7efaed458f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247754369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.4247754369
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.147474124
Short name T184
Test name
Test status
Simulation time 322602314698 ps
CPU time 670.93 seconds
Started Mar 10 12:31:17 PM PDT 24
Finished Mar 10 12:42:28 PM PDT 24
Peak memory 201388 kb
Host smart-515fa681-1041-44ee-89ed-0ede134d6c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147474124 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.147474124
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.3213588221
Short name T204
Test name
Test status
Simulation time 496344089033 ps
CPU time 1064.65 seconds
Started Mar 10 12:31:23 PM PDT 24
Finished Mar 10 12:49:08 PM PDT 24
Peak memory 201408 kb
Host smart-860359af-0105-497d-9105-5daa0f9fce82
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213588221 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interru
pt_fixed.3213588221
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.2159543221
Short name T692
Test name
Test status
Simulation time 329063671903 ps
CPU time 393.51 seconds
Started Mar 10 12:31:16 PM PDT 24
Finished Mar 10 12:37:50 PM PDT 24
Peak memory 201428 kb
Host smart-316b4b2c-193a-41c3-9713-e3ff004fab2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159543221 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.2159543221
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.2519781624
Short name T742
Test name
Test status
Simulation time 163416228187 ps
CPU time 363.92 seconds
Started Mar 10 12:31:20 PM PDT 24
Finished Mar 10 12:37:24 PM PDT 24
Peak memory 201404 kb
Host smart-62b52fe9-0ecb-4c55-bb4c-0b04998c530c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519781624 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fix
ed.2519781624
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.1466391780
Short name T294
Test name
Test status
Simulation time 559083597196 ps
CPU time 710.47 seconds
Started Mar 10 12:31:23 PM PDT 24
Finished Mar 10 12:43:14 PM PDT 24
Peak memory 201368 kb
Host smart-588469ef-8d4d-4e73-85e1-d4ce81fc5a58
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466391780 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters
_wakeup.1466391780
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.2636884543
Short name T621
Test name
Test status
Simulation time 196476873443 ps
CPU time 236.84 seconds
Started Mar 10 12:31:22 PM PDT 24
Finished Mar 10 12:35:19 PM PDT 24
Peak memory 201412 kb
Host smart-d3ece24c-7536-404e-a09e-3ac57eee5096
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636884543 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.adc_ctrl_filters_wakeup_fixed.2636884543
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.3904452261
Short name T240
Test name
Test status
Simulation time 97686967119 ps
CPU time 519.21 seconds
Started Mar 10 12:31:23 PM PDT 24
Finished Mar 10 12:40:02 PM PDT 24
Peak memory 201740 kb
Host smart-40b16836-cd5f-4ab4-8b03-45ec1a959138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904452261 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.3904452261
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.3815300888
Short name T502
Test name
Test status
Simulation time 26587038956 ps
CPU time 27.68 seconds
Started Mar 10 12:31:24 PM PDT 24
Finished Mar 10 12:31:52 PM PDT 24
Peak memory 201308 kb
Host smart-b461ef63-d2ab-41d2-a888-ecf143a88a5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815300888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.3815300888
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.2022079155
Short name T106
Test name
Test status
Simulation time 4716072950 ps
CPU time 7.38 seconds
Started Mar 10 12:31:29 PM PDT 24
Finished Mar 10 12:31:37 PM PDT 24
Peak memory 201216 kb
Host smart-62164f12-5953-4bd7-875e-b0e5738fe6fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022079155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.2022079155
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.2744107965
Short name T633
Test name
Test status
Simulation time 5925718929 ps
CPU time 15.11 seconds
Started Mar 10 12:31:20 PM PDT 24
Finished Mar 10 12:31:36 PM PDT 24
Peak memory 201388 kb
Host smart-560c07bf-06c3-40c5-84b1-0aa98f48816d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744107965 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.2744107965
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.93160586
Short name T749
Test name
Test status
Simulation time 165308298916 ps
CPU time 470.14 seconds
Started Mar 10 12:31:25 PM PDT 24
Finished Mar 10 12:39:16 PM PDT 24
Peak memory 211904 kb
Host smart-9b9d37c2-bec0-434b-8bc9-ee8e049436db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93160586 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all.93160586
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.2057042384
Short name T107
Test name
Test status
Simulation time 50844681344 ps
CPU time 200.27 seconds
Started Mar 10 12:31:32 PM PDT 24
Finished Mar 10 12:34:53 PM PDT 24
Peak memory 210004 kb
Host smart-eec26b6a-4414-4757-88f5-f79312dfb9b1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057042384 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.2057042384
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.2958661445
Short name T769
Test name
Test status
Simulation time 488686087 ps
CPU time 1.75 seconds
Started Mar 10 12:31:36 PM PDT 24
Finished Mar 10 12:31:38 PM PDT 24
Peak memory 201264 kb
Host smart-06eb1845-4617-46ea-ac0b-b535e2f4071a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958661445 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.2958661445
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.878965756
Short name T603
Test name
Test status
Simulation time 378213265266 ps
CPU time 454.52 seconds
Started Mar 10 12:31:36 PM PDT 24
Finished Mar 10 12:39:11 PM PDT 24
Peak memory 201448 kb
Host smart-1298b73a-742f-4b6a-82c5-63264a148242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878965756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.878965756
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.2809188396
Short name T747
Test name
Test status
Simulation time 328810936103 ps
CPU time 94.06 seconds
Started Mar 10 12:31:29 PM PDT 24
Finished Mar 10 12:33:03 PM PDT 24
Peak memory 201312 kb
Host smart-d6932e2c-74fa-43ff-8021-64c9d7f78c67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809188396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.2809188396
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.2994980045
Short name T488
Test name
Test status
Simulation time 489246872671 ps
CPU time 1006.83 seconds
Started Mar 10 12:31:23 PM PDT 24
Finished Mar 10 12:48:10 PM PDT 24
Peak memory 201460 kb
Host smart-13aba932-482a-40a3-a6fd-8e2d07ed3af4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994980045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interru
pt_fixed.2994980045
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.2354537035
Short name T609
Test name
Test status
Simulation time 161679172668 ps
CPU time 355.52 seconds
Started Mar 10 12:31:24 PM PDT 24
Finished Mar 10 12:37:19 PM PDT 24
Peak memory 201376 kb
Host smart-a61d14b5-7df7-4bfc-9c8d-caecbc2b2318
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354537035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fix
ed.2354537035
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.3535682193
Short name T283
Test name
Test status
Simulation time 595735140427 ps
CPU time 367.1 seconds
Started Mar 10 12:31:23 PM PDT 24
Finished Mar 10 12:37:30 PM PDT 24
Peak memory 201420 kb
Host smart-71c23bea-6751-4963-bf2f-a4a63dbc2057
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535682193 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters
_wakeup.3535682193
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.646083306
Short name T428
Test name
Test status
Simulation time 206254951850 ps
CPU time 468.95 seconds
Started Mar 10 12:31:28 PM PDT 24
Finished Mar 10 12:39:17 PM PDT 24
Peak memory 201388 kb
Host smart-d5c5ab64-797c-4b0f-b3b5-51bba1374b7e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646083306 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
adc_ctrl_filters_wakeup_fixed.646083306
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.726040731
Short name T530
Test name
Test status
Simulation time 116911532639 ps
CPU time 635.03 seconds
Started Mar 10 12:31:28 PM PDT 24
Finished Mar 10 12:42:03 PM PDT 24
Peak memory 201764 kb
Host smart-fdf7b4fc-28ce-4a6b-b9c4-cea1d7756e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726040731 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.726040731
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.815509776
Short name T587
Test name
Test status
Simulation time 22282353383 ps
CPU time 24.89 seconds
Started Mar 10 12:31:32 PM PDT 24
Finished Mar 10 12:31:57 PM PDT 24
Peak memory 201252 kb
Host smart-77430dca-403c-4e5c-9df4-bb047485735b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815509776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.815509776
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.534939825
Short name T707
Test name
Test status
Simulation time 4537192428 ps
CPU time 10.61 seconds
Started Mar 10 12:31:32 PM PDT 24
Finished Mar 10 12:31:43 PM PDT 24
Peak memory 201212 kb
Host smart-f7240632-2075-427c-949a-05fc7c763576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534939825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.534939825
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.2984785798
Short name T551
Test name
Test status
Simulation time 5950617491 ps
CPU time 3.64 seconds
Started Mar 10 12:31:22 PM PDT 24
Finished Mar 10 12:31:26 PM PDT 24
Peak memory 201276 kb
Host smart-f16fa6d4-f1b7-4855-98b3-64fb8f9c9134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984785798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.2984785798
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.31351534
Short name T788
Test name
Test status
Simulation time 987727419306 ps
CPU time 664.89 seconds
Started Mar 10 12:31:36 PM PDT 24
Finished Mar 10 12:42:41 PM PDT 24
Peak memory 212304 kb
Host smart-4cf70af1-c145-44e2-b861-9954e1f36989
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31351534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all.31351534
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.3328105312
Short name T22
Test name
Test status
Simulation time 107504951828 ps
CPU time 93.5 seconds
Started Mar 10 12:31:29 PM PDT 24
Finished Mar 10 12:33:03 PM PDT 24
Peak memory 210060 kb
Host smart-5fe07ef5-1a58-4a7a-982c-b13f220ec9ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328105312 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.3328105312
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.401367172
Short name T197
Test name
Test status
Simulation time 335011033 ps
CPU time 1.37 seconds
Started Mar 10 12:31:36 PM PDT 24
Finished Mar 10 12:31:38 PM PDT 24
Peak memory 201200 kb
Host smart-2e8cf6cb-23dd-4610-85c8-7e53c4e19348
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401367172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.401367172
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.2243494861
Short name T101
Test name
Test status
Simulation time 478900814926 ps
CPU time 824.21 seconds
Started Mar 10 12:31:33 PM PDT 24
Finished Mar 10 12:45:17 PM PDT 24
Peak memory 201476 kb
Host smart-cfea203f-9b43-4c2a-b6cd-1bce67d35a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243494861 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.2243494861
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.3398775097
Short name T631
Test name
Test status
Simulation time 490967145101 ps
CPU time 571.4 seconds
Started Mar 10 12:31:28 PM PDT 24
Finished Mar 10 12:41:00 PM PDT 24
Peak memory 201528 kb
Host smart-016f8db2-4754-4aa0-a18e-35733eef5f54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398775097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.3398775097
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.1653059212
Short name T646
Test name
Test status
Simulation time 324445070235 ps
CPU time 150.29 seconds
Started Mar 10 12:31:28 PM PDT 24
Finished Mar 10 12:33:59 PM PDT 24
Peak memory 201476 kb
Host smart-ec209b60-971e-44bd-a4e9-062b14f135f6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653059212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interru
pt_fixed.1653059212
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.3293899942
Short name T493
Test name
Test status
Simulation time 160114680380 ps
CPU time 101.1 seconds
Started Mar 10 12:31:31 PM PDT 24
Finished Mar 10 12:33:13 PM PDT 24
Peak memory 201304 kb
Host smart-55844638-00a5-4730-9cf0-12f1ab25fc74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293899942 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.3293899942
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.292841413
Short name T433
Test name
Test status
Simulation time 324076120210 ps
CPU time 731.1 seconds
Started Mar 10 12:31:28 PM PDT 24
Finished Mar 10 12:43:40 PM PDT 24
Peak memory 201404 kb
Host smart-3227d54c-9b48-4d25-bfc8-7e1c8ba49e96
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=292841413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fixe
d.292841413
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.2895350440
Short name T90
Test name
Test status
Simulation time 646337089811 ps
CPU time 1594.25 seconds
Started Mar 10 12:31:32 PM PDT 24
Finished Mar 10 12:58:06 PM PDT 24
Peak memory 201580 kb
Host smart-837ee8ce-00d5-4de3-99de-512fdc1ecffc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895350440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters
_wakeup.2895350440
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.2017084046
Short name T520
Test name
Test status
Simulation time 192250945111 ps
CPU time 113.81 seconds
Started Mar 10 12:31:36 PM PDT 24
Finished Mar 10 12:33:30 PM PDT 24
Peak memory 201328 kb
Host smart-f3fee88a-6cae-4d66-b6cc-8b58815a9140
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017084046 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.adc_ctrl_filters_wakeup_fixed.2017084046
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.2998241261
Short name T119
Test name
Test status
Simulation time 76551817014 ps
CPU time 328.15 seconds
Started Mar 10 12:31:32 PM PDT 24
Finished Mar 10 12:37:01 PM PDT 24
Peak memory 201684 kb
Host smart-51f0ef14-6292-4913-aa5e-804826119c22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998241261 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.2998241261
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.2735952860
Short name T455
Test name
Test status
Simulation time 28660854668 ps
CPU time 8.98 seconds
Started Mar 10 12:31:35 PM PDT 24
Finished Mar 10 12:31:44 PM PDT 24
Peak memory 201232 kb
Host smart-fca77acc-91c4-477e-aa43-c9e76d9d4001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735952860 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.2735952860
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.537207105
Short name T612
Test name
Test status
Simulation time 4487780786 ps
CPU time 3.39 seconds
Started Mar 10 12:31:31 PM PDT 24
Finished Mar 10 12:31:35 PM PDT 24
Peak memory 201348 kb
Host smart-df4010dd-b359-4c03-95cf-39ce5ff851c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537207105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.537207105
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.571560025
Short name T519
Test name
Test status
Simulation time 5703929695 ps
CPU time 4.22 seconds
Started Mar 10 12:31:30 PM PDT 24
Finished Mar 10 12:31:34 PM PDT 24
Peak memory 201264 kb
Host smart-24012ea2-fcf6-4cab-99bd-337825b8e4a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571560025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.571560025
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.240962421
Short name T762
Test name
Test status
Simulation time 213885707082 ps
CPU time 511.94 seconds
Started Mar 10 12:31:35 PM PDT 24
Finished Mar 10 12:40:07 PM PDT 24
Peak memory 201348 kb
Host smart-52ed905b-78e6-4daf-8afb-6e16952467ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240962421 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all.
240962421
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.3479770104
Short name T328
Test name
Test status
Simulation time 269874998820 ps
CPU time 540.58 seconds
Started Mar 10 12:31:32 PM PDT 24
Finished Mar 10 12:40:33 PM PDT 24
Peak memory 209884 kb
Host smart-8e1a5db7-9763-4821-b44f-0eb850fdf06d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479770104 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.3479770104
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.4232095371
Short name T604
Test name
Test status
Simulation time 519246184 ps
CPU time 0.93 seconds
Started Mar 10 12:31:52 PM PDT 24
Finished Mar 10 12:31:53 PM PDT 24
Peak memory 201268 kb
Host smart-923b35c9-692d-4c76-8b8b-86cfc2c7636a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232095371 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.4232095371
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.2151294224
Short name T262
Test name
Test status
Simulation time 365007980476 ps
CPU time 262.87 seconds
Started Mar 10 12:31:41 PM PDT 24
Finished Mar 10 12:36:05 PM PDT 24
Peak memory 201504 kb
Host smart-dc3f7fb8-fdd0-4c66-8f52-ab14d2d19f11
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151294224 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gat
ing.2151294224
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.4023915251
Short name T524
Test name
Test status
Simulation time 160315164663 ps
CPU time 75.88 seconds
Started Mar 10 12:31:40 PM PDT 24
Finished Mar 10 12:32:56 PM PDT 24
Peak memory 201384 kb
Host smart-e141286e-9ad1-4ab5-b716-805b8bd0eacf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023915251 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.4023915251
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.739168455
Short name T638
Test name
Test status
Simulation time 163735149548 ps
CPU time 375.18 seconds
Started Mar 10 12:31:41 PM PDT 24
Finished Mar 10 12:37:57 PM PDT 24
Peak memory 201388 kb
Host smart-b94d3f5f-d1cc-49c8-a307-69152e02d101
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=739168455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrup
t_fixed.739168455
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.1326882175
Short name T745
Test name
Test status
Simulation time 492307442383 ps
CPU time 1194.3 seconds
Started Mar 10 12:31:44 PM PDT 24
Finished Mar 10 12:51:39 PM PDT 24
Peak memory 201428 kb
Host smart-3d464322-d706-4488-9871-2500ca8c28df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326882175 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.1326882175
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.2743880576
Short name T565
Test name
Test status
Simulation time 327775626981 ps
CPU time 190.71 seconds
Started Mar 10 12:31:44 PM PDT 24
Finished Mar 10 12:34:55 PM PDT 24
Peak memory 201332 kb
Host smart-5464fc8e-7b80-446a-b286-f48e971a5b77
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743880576 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fix
ed.2743880576
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.128068727
Short name T549
Test name
Test status
Simulation time 589686873114 ps
CPU time 1255.68 seconds
Started Mar 10 12:31:40 PM PDT 24
Finished Mar 10 12:52:37 PM PDT 24
Peak memory 201432 kb
Host smart-8d1f9131-5058-459e-a210-bfa346b3a63c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128068727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
adc_ctrl_filters_wakeup_fixed.128068727
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.2445137099
Short name T243
Test name
Test status
Simulation time 123036993417 ps
CPU time 399.59 seconds
Started Mar 10 12:31:52 PM PDT 24
Finished Mar 10 12:38:32 PM PDT 24
Peak memory 201652 kb
Host smart-16935b23-adf7-41be-aaad-55137ad62a8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445137099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.2445137099
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.356594002
Short name T667
Test name
Test status
Simulation time 31259451094 ps
CPU time 9.83 seconds
Started Mar 10 12:31:44 PM PDT 24
Finished Mar 10 12:31:54 PM PDT 24
Peak memory 201324 kb
Host smart-c7fb4eeb-4141-486a-a762-0b844cd1fc37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356594002 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.356594002
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.1023342705
Short name T613
Test name
Test status
Simulation time 3325733291 ps
CPU time 5.15 seconds
Started Mar 10 12:31:40 PM PDT 24
Finished Mar 10 12:31:45 PM PDT 24
Peak memory 201356 kb
Host smart-86d37e7b-a069-471b-9a57-d500cf677079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023342705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.1023342705
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.3254195998
Short name T572
Test name
Test status
Simulation time 5825570366 ps
CPU time 4.74 seconds
Started Mar 10 12:31:44 PM PDT 24
Finished Mar 10 12:31:49 PM PDT 24
Peak memory 201316 kb
Host smart-38264e44-fcc9-4025-bf15-a7ec304a81ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254195998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.3254195998
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.3000861579
Short name T663
Test name
Test status
Simulation time 11864762684 ps
CPU time 27.22 seconds
Started Mar 10 12:31:47 PM PDT 24
Finished Mar 10 12:32:14 PM PDT 24
Peak memory 201316 kb
Host smart-5f370bf0-f908-4e25-8d65-2572c13da8c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000861579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all
.3000861579
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.3148631070
Short name T35
Test name
Test status
Simulation time 252668447367 ps
CPU time 107.56 seconds
Started Mar 10 12:31:45 PM PDT 24
Finished Mar 10 12:33:33 PM PDT 24
Peak memory 210132 kb
Host smart-d05d543b-2dd5-477d-9a49-6b49f3511024
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148631070 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.3148631070
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.4140987608
Short name T405
Test name
Test status
Simulation time 312160466 ps
CPU time 1.41 seconds
Started Mar 10 12:29:07 PM PDT 24
Finished Mar 10 12:29:08 PM PDT 24
Peak memory 201272 kb
Host smart-7e72658c-e503-4ee2-9f88-fbc13b973b49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140987608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.4140987608
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.2339753893
Short name T736
Test name
Test status
Simulation time 328582674372 ps
CPU time 823.37 seconds
Started Mar 10 12:29:11 PM PDT 24
Finished Mar 10 12:42:55 PM PDT 24
Peak memory 201412 kb
Host smart-294d05ab-467f-4eaf-ba11-1681500bbcd8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339753893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gati
ng.2339753893
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.1845360321
Short name T331
Test name
Test status
Simulation time 564801949665 ps
CPU time 1456.17 seconds
Started Mar 10 12:29:13 PM PDT 24
Finished Mar 10 12:53:29 PM PDT 24
Peak memory 201472 kb
Host smart-c8414c07-bcaf-4acf-80e8-cbae1493ad82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845360321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.1845360321
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.1928506156
Short name T363
Test name
Test status
Simulation time 495788790751 ps
CPU time 1119.32 seconds
Started Mar 10 12:29:13 PM PDT 24
Finished Mar 10 12:47:53 PM PDT 24
Peak memory 201428 kb
Host smart-5d07df92-3298-4b4c-b1ad-4ae5e1015620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928506156 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.1928506156
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.2091736779
Short name T702
Test name
Test status
Simulation time 328967461182 ps
CPU time 723.59 seconds
Started Mar 10 12:29:14 PM PDT 24
Finished Mar 10 12:41:17 PM PDT 24
Peak memory 201576 kb
Host smart-82a66f44-eabf-4d8d-b95a-4baf1a854bc4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091736779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrup
t_fixed.2091736779
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.2026449052
Short name T580
Test name
Test status
Simulation time 320363017299 ps
CPU time 375.03 seconds
Started Mar 10 12:29:06 PM PDT 24
Finished Mar 10 12:35:21 PM PDT 24
Peak memory 201380 kb
Host smart-d8e5006b-75ae-435c-9446-10003df9ea02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026449052 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.2026449052
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.1031188778
Short name T423
Test name
Test status
Simulation time 495065933602 ps
CPU time 402.8 seconds
Started Mar 10 12:29:11 PM PDT 24
Finished Mar 10 12:35:54 PM PDT 24
Peak memory 201392 kb
Host smart-00158d31-3465-498f-bd5f-71d22a6ecc54
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031188778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixe
d.1031188778
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.2035176365
Short name T303
Test name
Test status
Simulation time 367774109605 ps
CPU time 130.76 seconds
Started Mar 10 12:29:07 PM PDT 24
Finished Mar 10 12:31:18 PM PDT 24
Peak memory 201368 kb
Host smart-73d7b5f9-6fec-453e-80ae-7a053759e14f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035176365 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_
wakeup.2035176365
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.332559051
Short name T650
Test name
Test status
Simulation time 194895670610 ps
CPU time 236.6 seconds
Started Mar 10 12:29:07 PM PDT 24
Finished Mar 10 12:33:04 PM PDT 24
Peak memory 201420 kb
Host smart-9bae129d-c96f-4304-8f67-5b8fe39c777a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332559051 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.a
dc_ctrl_filters_wakeup_fixed.332559051
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.983506803
Short name T247
Test name
Test status
Simulation time 111057647500 ps
CPU time 547.9 seconds
Started Mar 10 12:29:05 PM PDT 24
Finished Mar 10 12:38:13 PM PDT 24
Peak memory 201708 kb
Host smart-255ce63e-bf27-42a2-af2c-f6ceee571c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983506803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.983506803
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.1049769521
Short name T199
Test name
Test status
Simulation time 39000831395 ps
CPU time 91.5 seconds
Started Mar 10 12:29:10 PM PDT 24
Finished Mar 10 12:30:42 PM PDT 24
Peak memory 201324 kb
Host smart-8e68ecf3-9ad2-4016-9a01-0dee0352e088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049769521 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.1049769521
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.1783647513
Short name T703
Test name
Test status
Simulation time 4680275313 ps
CPU time 3.48 seconds
Started Mar 10 12:29:06 PM PDT 24
Finished Mar 10 12:29:11 PM PDT 24
Peak memory 201316 kb
Host smart-f74c1713-c5c3-4b11-bd8e-1f91a86ad9cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783647513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.1783647513
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.1306558503
Short name T134
Test name
Test status
Simulation time 5899951439 ps
CPU time 4.28 seconds
Started Mar 10 12:29:07 PM PDT 24
Finished Mar 10 12:29:11 PM PDT 24
Peak memory 201356 kb
Host smart-949fbb64-90fc-4ca7-8014-2f5846f638eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306558503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.1306558503
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.3672700482
Short name T43
Test name
Test status
Simulation time 40249328819 ps
CPU time 22.77 seconds
Started Mar 10 12:29:10 PM PDT 24
Finished Mar 10 12:29:33 PM PDT 24
Peak memory 201340 kb
Host smart-9906f23d-b175-4fdf-acd7-7f812a83000a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672700482 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.
3672700482
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.4028972505
Short name T54
Test name
Test status
Simulation time 58957210197 ps
CPU time 130.3 seconds
Started Mar 10 12:29:12 PM PDT 24
Finished Mar 10 12:31:23 PM PDT 24
Peak memory 209804 kb
Host smart-51a30b10-c58b-4030-9d83-19b8606d0880
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028972505 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.4028972505
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.1383398395
Short name T518
Test name
Test status
Simulation time 315536974 ps
CPU time 0.77 seconds
Started Mar 10 12:29:11 PM PDT 24
Finished Mar 10 12:29:12 PM PDT 24
Peak memory 201148 kb
Host smart-0d2bd643-7090-4f54-bba0-d8ec70091351
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383398395 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.1383398395
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.1264083887
Short name T16
Test name
Test status
Simulation time 329100103805 ps
CPU time 126.96 seconds
Started Mar 10 12:29:11 PM PDT 24
Finished Mar 10 12:31:19 PM PDT 24
Peak memory 201368 kb
Host smart-52a37058-eaef-48de-8224-754575d850f7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264083887 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gati
ng.1264083887
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.3197935474
Short name T191
Test name
Test status
Simulation time 160410875504 ps
CPU time 203.08 seconds
Started Mar 10 12:29:06 PM PDT 24
Finished Mar 10 12:32:30 PM PDT 24
Peak memory 201568 kb
Host smart-e3388aaa-a8a2-4f8d-a3c1-02c909643efe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197935474 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.3197935474
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.1727135267
Short name T522
Test name
Test status
Simulation time 318530278583 ps
CPU time 217.12 seconds
Started Mar 10 12:29:04 PM PDT 24
Finished Mar 10 12:32:41 PM PDT 24
Peak memory 201412 kb
Host smart-c027e7bd-ca48-4f3e-8b46-f310f5cd7ee8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727135267 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrup
t_fixed.1727135267
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.377114633
Short name T206
Test name
Test status
Simulation time 492746478740 ps
CPU time 125.37 seconds
Started Mar 10 12:29:14 PM PDT 24
Finished Mar 10 12:31:19 PM PDT 24
Peak memory 201528 kb
Host smart-311dcaee-5763-4c82-accf-ed7e19497557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377114633 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.377114633
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.3339617062
Short name T709
Test name
Test status
Simulation time 166712819772 ps
CPU time 353.72 seconds
Started Mar 10 12:29:19 PM PDT 24
Finished Mar 10 12:35:13 PM PDT 24
Peak memory 201344 kb
Host smart-7793398e-be93-4fbc-bf9a-e74b4028c28d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339617062 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixe
d.3339617062
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.3823432252
Short name T553
Test name
Test status
Simulation time 177858268026 ps
CPU time 219.89 seconds
Started Mar 10 12:29:19 PM PDT 24
Finished Mar 10 12:33:00 PM PDT 24
Peak memory 201356 kb
Host smart-44d46852-e1e8-4bec-80a3-58ea61ef53ee
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823432252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_
wakeup.3823432252
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.2566370410
Short name T177
Test name
Test status
Simulation time 598916480126 ps
CPU time 149.1 seconds
Started Mar 10 12:29:10 PM PDT 24
Finished Mar 10 12:31:40 PM PDT 24
Peak memory 201464 kb
Host smart-bfa434f7-e467-45e8-9d77-237194226397
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566370410 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.
adc_ctrl_filters_wakeup_fixed.2566370410
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.369409843
Short name T415
Test name
Test status
Simulation time 93124335118 ps
CPU time 298.25 seconds
Started Mar 10 12:29:11 PM PDT 24
Finished Mar 10 12:34:11 PM PDT 24
Peak memory 201668 kb
Host smart-0f6d64b2-c0bf-4eeb-aad8-fa0e6b530f62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369409843 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.369409843
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.3432571449
Short name T625
Test name
Test status
Simulation time 41986834315 ps
CPU time 23.13 seconds
Started Mar 10 12:29:10 PM PDT 24
Finished Mar 10 12:29:33 PM PDT 24
Peak memory 201316 kb
Host smart-b380f543-6644-4a0a-8491-6240a1bac895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432571449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.3432571449
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.508540994
Short name T393
Test name
Test status
Simulation time 3074281642 ps
CPU time 7.8 seconds
Started Mar 10 12:29:13 PM PDT 24
Finished Mar 10 12:29:21 PM PDT 24
Peak memory 201248 kb
Host smart-5ace8521-4c0d-44d3-946b-75d7c4b5c573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508540994 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.508540994
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.1962690080
Short name T785
Test name
Test status
Simulation time 6091828072 ps
CPU time 8.9 seconds
Started Mar 10 12:29:05 PM PDT 24
Finished Mar 10 12:29:14 PM PDT 24
Peak memory 201276 kb
Host smart-6d60b683-94f7-45f2-a0c2-35e13741cce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962690080 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.1962690080
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.3308806235
Short name T308
Test name
Test status
Simulation time 354281856511 ps
CPU time 128.95 seconds
Started Mar 10 12:29:11 PM PDT 24
Finished Mar 10 12:31:21 PM PDT 24
Peak memory 201368 kb
Host smart-2917d668-af77-4336-8f1c-3e96f4222974
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308806235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.
3308806235
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.383104399
Short name T635
Test name
Test status
Simulation time 58409825829 ps
CPU time 237.91 seconds
Started Mar 10 12:29:13 PM PDT 24
Finished Mar 10 12:33:11 PM PDT 24
Peak memory 209956 kb
Host smart-4c21fa8b-bb8c-4afe-828c-dd47b6f95ac8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383104399 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.383104399
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.4195258706
Short name T543
Test name
Test status
Simulation time 422160794 ps
CPU time 0.85 seconds
Started Mar 10 12:29:20 PM PDT 24
Finished Mar 10 12:29:21 PM PDT 24
Peak memory 201252 kb
Host smart-5715540f-0610-470f-a5f4-77543759be12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195258706 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.4195258706
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.1833643288
Short name T523
Test name
Test status
Simulation time 165695388083 ps
CPU time 328.75 seconds
Started Mar 10 12:29:09 PM PDT 24
Finished Mar 10 12:34:38 PM PDT 24
Peak memory 201584 kb
Host smart-111bde21-2b9a-4aca-97bc-a08f334edf31
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833643288 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gati
ng.1833643288
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.1452147914
Short name T128
Test name
Test status
Simulation time 497207891339 ps
CPU time 271.42 seconds
Started Mar 10 12:29:13 PM PDT 24
Finished Mar 10 12:33:45 PM PDT 24
Peak memory 201432 kb
Host smart-d336f944-5cf4-4c89-b982-7b2cc6c08c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452147914 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.1452147914
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.3921113180
Short name T654
Test name
Test status
Simulation time 492241420078 ps
CPU time 1072.98 seconds
Started Mar 10 12:29:11 PM PDT 24
Finished Mar 10 12:47:06 PM PDT 24
Peak memory 201356 kb
Host smart-d7f8531d-5a78-445b-b779-9f214f3511cb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921113180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrup
t_fixed.3921113180
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.4065856601
Short name T220
Test name
Test status
Simulation time 327026440463 ps
CPU time 154.85 seconds
Started Mar 10 12:29:11 PM PDT 24
Finished Mar 10 12:31:47 PM PDT 24
Peak memory 201416 kb
Host smart-39c40669-0962-4e56-a4ab-80e87bd1fb6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065856601 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.4065856601
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.2838974482
Short name T576
Test name
Test status
Simulation time 487749300032 ps
CPU time 278.04 seconds
Started Mar 10 12:29:10 PM PDT 24
Finished Mar 10 12:33:48 PM PDT 24
Peak memory 201556 kb
Host smart-52c354a1-16fd-465c-8bbe-b6d959b89a1c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838974482 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixe
d.2838974482
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.4025851596
Short name T11
Test name
Test status
Simulation time 171851171115 ps
CPU time 45.84 seconds
Started Mar 10 12:29:09 PM PDT 24
Finished Mar 10 12:29:55 PM PDT 24
Peak memory 201492 kb
Host smart-babda8b8-7c49-401f-a60c-77838438b488
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025851596 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_
wakeup.4025851596
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.1391028062
Short name T122
Test name
Test status
Simulation time 392548671122 ps
CPU time 914.88 seconds
Started Mar 10 12:29:14 PM PDT 24
Finished Mar 10 12:44:29 PM PDT 24
Peak memory 201412 kb
Host smart-64d9efac-dc80-48a8-858f-700cbb5d5c5c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391028062 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
adc_ctrl_filters_wakeup_fixed.1391028062
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.1478281341
Short name T585
Test name
Test status
Simulation time 32365172842 ps
CPU time 5.68 seconds
Started Mar 10 12:29:14 PM PDT 24
Finished Mar 10 12:29:20 PM PDT 24
Peak memory 201368 kb
Host smart-6d60b802-c1fa-44b8-9416-d8da1d2792f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478281341 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.1478281341
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.1980640357
Short name T34
Test name
Test status
Simulation time 4743640407 ps
CPU time 3.84 seconds
Started Mar 10 12:29:10 PM PDT 24
Finished Mar 10 12:29:14 PM PDT 24
Peak memory 201324 kb
Host smart-f95aea0c-c9af-4774-abf6-f626a483737d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980640357 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.1980640357
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.3984208232
Short name T212
Test name
Test status
Simulation time 5859717151 ps
CPU time 14.57 seconds
Started Mar 10 12:29:20 PM PDT 24
Finished Mar 10 12:29:36 PM PDT 24
Peak memory 201272 kb
Host smart-1a105ae5-484d-4576-8c07-16577c69c6e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984208232 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.3984208232
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.1770987140
Short name T376
Test name
Test status
Simulation time 322247667737 ps
CPU time 499.13 seconds
Started Mar 10 12:29:12 PM PDT 24
Finished Mar 10 12:37:32 PM PDT 24
Peak memory 209892 kb
Host smart-1e17f59b-6fab-4c88-97e8-8b7e0b7352f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770987140 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.
1770987140
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.1056772678
Short name T215
Test name
Test status
Simulation time 454403238 ps
CPU time 1.67 seconds
Started Mar 10 12:29:17 PM PDT 24
Finished Mar 10 12:29:19 PM PDT 24
Peak memory 201392 kb
Host smart-8e11e8bc-c230-4246-b1f8-15f45fc36b00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056772678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.1056772678
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.1564016410
Short name T172
Test name
Test status
Simulation time 184425423954 ps
CPU time 195.21 seconds
Started Mar 10 12:29:17 PM PDT 24
Finished Mar 10 12:32:32 PM PDT 24
Peak memory 201384 kb
Host smart-1a2739d8-6496-48cd-a236-e521db7694e0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564016410 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gati
ng.1564016410
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.1677125375
Short name T350
Test name
Test status
Simulation time 162348403932 ps
CPU time 102.12 seconds
Started Mar 10 12:29:20 PM PDT 24
Finished Mar 10 12:31:02 PM PDT 24
Peak memory 201356 kb
Host smart-a86d0ea5-798f-4357-bd3f-c9a96571ea0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677125375 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.1677125375
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.162956863
Short name T18
Test name
Test status
Simulation time 168529071305 ps
CPU time 205.02 seconds
Started Mar 10 12:29:14 PM PDT 24
Finished Mar 10 12:32:39 PM PDT 24
Peak memory 201384 kb
Host smart-1b732ae5-b012-4b66-9465-2005f3121aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162956863 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.162956863
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.4256210507
Short name T540
Test name
Test status
Simulation time 498728424757 ps
CPU time 276.98 seconds
Started Mar 10 12:29:10 PM PDT 24
Finished Mar 10 12:33:47 PM PDT 24
Peak memory 201460 kb
Host smart-9bca83ad-00ed-4f7e-8f0e-4e240f46fb2d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256210507 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrup
t_fixed.4256210507
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.1191058805
Short name T588
Test name
Test status
Simulation time 161471731150 ps
CPU time 100.97 seconds
Started Mar 10 12:29:20 PM PDT 24
Finished Mar 10 12:31:01 PM PDT 24
Peak memory 201356 kb
Host smart-9a76f083-f285-4cc7-8f40-7ff70cca3cd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191058805 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.1191058805
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.2353975918
Short name T687
Test name
Test status
Simulation time 167826259831 ps
CPU time 205.05 seconds
Started Mar 10 12:29:19 PM PDT 24
Finished Mar 10 12:32:44 PM PDT 24
Peak memory 201384 kb
Host smart-1ef400eb-bd8b-4d8e-8167-0e9dab5ab25b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353975918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixe
d.2353975918
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.4103838552
Short name T333
Test name
Test status
Simulation time 212247614371 ps
CPU time 487.64 seconds
Started Mar 10 12:29:17 PM PDT 24
Finished Mar 10 12:37:25 PM PDT 24
Peak memory 201316 kb
Host smart-dd6def90-76a1-4b35-a71d-31a16791199a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103838552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_
wakeup.4103838552
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.1253447777
Short name T566
Test name
Test status
Simulation time 396423810690 ps
CPU time 884.4 seconds
Started Mar 10 12:29:11 PM PDT 24
Finished Mar 10 12:43:56 PM PDT 24
Peak memory 201408 kb
Host smart-c2fbd8e8-2903-4b11-baf9-a0bd29d70e3a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253447777 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.
adc_ctrl_filters_wakeup_fixed.1253447777
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.3206943709
Short name T372
Test name
Test status
Simulation time 109632053867 ps
CPU time 603.04 seconds
Started Mar 10 12:29:17 PM PDT 24
Finished Mar 10 12:39:20 PM PDT 24
Peak memory 201780 kb
Host smart-98af0292-6604-4225-97e3-e05d295f655f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206943709 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.3206943709
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.1132874487
Short name T123
Test name
Test status
Simulation time 41751165954 ps
CPU time 69.42 seconds
Started Mar 10 12:29:12 PM PDT 24
Finished Mar 10 12:30:22 PM PDT 24
Peak memory 201320 kb
Host smart-97e60d23-c764-428f-8825-a651d7488c8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132874487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.1132874487
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.2856397776
Short name T728
Test name
Test status
Simulation time 4356666265 ps
CPU time 5.79 seconds
Started Mar 10 12:29:15 PM PDT 24
Finished Mar 10 12:29:21 PM PDT 24
Peak memory 201256 kb
Host smart-2fdd9156-141e-4df9-87d4-f7dcc0f4aaca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856397776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.2856397776
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.2874286021
Short name T448
Test name
Test status
Simulation time 5881616241 ps
CPU time 3.82 seconds
Started Mar 10 12:29:20 PM PDT 24
Finished Mar 10 12:29:24 PM PDT 24
Peak memory 201316 kb
Host smart-7d2fde73-4c98-4f75-b5b6-a3c47ad783a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874286021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.2874286021
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.1487180972
Short name T377
Test name
Test status
Simulation time 276234658616 ps
CPU time 605.6 seconds
Started Mar 10 12:29:20 PM PDT 24
Finished Mar 10 12:39:26 PM PDT 24
Peak memory 201636 kb
Host smart-1a1d271e-7626-4d0c-8701-bac0d8b052c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487180972 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.
1487180972
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.2850095942
Short name T52
Test name
Test status
Simulation time 169607822696 ps
CPU time 153.7 seconds
Started Mar 10 12:29:18 PM PDT 24
Finished Mar 10 12:31:52 PM PDT 24
Peak memory 210080 kb
Host smart-563f182f-cd3d-49b2-b771-99659b4b2dd8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850095942 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.2850095942
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.3667094727
Short name T527
Test name
Test status
Simulation time 388507885 ps
CPU time 0.74 seconds
Started Mar 10 12:29:14 PM PDT 24
Finished Mar 10 12:29:15 PM PDT 24
Peak memory 201252 kb
Host smart-0c800d65-06dd-44b8-a842-b7201dc4bf99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667094727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.3667094727
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.454906281
Short name T163
Test name
Test status
Simulation time 371686027140 ps
CPU time 432.08 seconds
Started Mar 10 12:29:20 PM PDT 24
Finished Mar 10 12:36:32 PM PDT 24
Peak memory 201388 kb
Host smart-2cdd9ac6-9fae-454c-948b-5e1cc1538f1f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454906281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gatin
g.454906281
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.3022720395
Short name T760
Test name
Test status
Simulation time 174369098298 ps
CPU time 399.41 seconds
Started Mar 10 12:29:20 PM PDT 24
Finished Mar 10 12:36:00 PM PDT 24
Peak memory 201348 kb
Host smart-4747794f-aae5-4506-83fb-c2c5bbe2edf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022720395 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.3022720395
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.344509984
Short name T552
Test name
Test status
Simulation time 336382308091 ps
CPU time 379.66 seconds
Started Mar 10 12:29:20 PM PDT 24
Finished Mar 10 12:35:41 PM PDT 24
Peak memory 201388 kb
Host smart-fd364917-3232-4621-bec7-a276562e357a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344509984 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.344509984
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.572953369
Short name T595
Test name
Test status
Simulation time 330782864877 ps
CPU time 185.77 seconds
Started Mar 10 12:29:20 PM PDT 24
Finished Mar 10 12:32:26 PM PDT 24
Peak memory 201408 kb
Host smart-c061dab0-ac56-461c-9f18-3a182a9b5b06
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=572953369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt
_fixed.572953369
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.2495166544
Short name T682
Test name
Test status
Simulation time 481687466741 ps
CPU time 1005.1 seconds
Started Mar 10 12:29:08 PM PDT 24
Finished Mar 10 12:45:53 PM PDT 24
Peak memory 201732 kb
Host smart-d444b92e-89d6-463b-b7fe-7c50b196da79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495166544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.2495166544
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.3641561672
Short name T459
Test name
Test status
Simulation time 331342119160 ps
CPU time 67.05 seconds
Started Mar 10 12:29:12 PM PDT 24
Finished Mar 10 12:30:20 PM PDT 24
Peak memory 201404 kb
Host smart-14fb8c28-ce56-443a-bc4e-0cca67ac2088
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641561672 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixe
d.3641561672
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.923564669
Short name T602
Test name
Test status
Simulation time 204974886000 ps
CPU time 210.06 seconds
Started Mar 10 12:29:15 PM PDT 24
Finished Mar 10 12:32:46 PM PDT 24
Peak memory 201404 kb
Host smart-f4b41e16-f474-4000-9746-75e5d57a7674
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923564669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.a
dc_ctrl_filters_wakeup_fixed.923564669
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.1084807496
Short name T419
Test name
Test status
Simulation time 75569483016 ps
CPU time 236.83 seconds
Started Mar 10 12:29:18 PM PDT 24
Finished Mar 10 12:33:15 PM PDT 24
Peak memory 201648 kb
Host smart-fd7e19d5-0900-4459-a6b7-b042a9aca8b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084807496 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.1084807496
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.3639919963
Short name T645
Test name
Test status
Simulation time 31437261774 ps
CPU time 71.35 seconds
Started Mar 10 12:29:19 PM PDT 24
Finished Mar 10 12:30:31 PM PDT 24
Peak memory 201240 kb
Host smart-912e6b9f-5f3a-4a9a-a862-b1378352737f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639919963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.3639919963
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.1811274420
Short name T222
Test name
Test status
Simulation time 4189619717 ps
CPU time 11.3 seconds
Started Mar 10 12:29:18 PM PDT 24
Finished Mar 10 12:29:30 PM PDT 24
Peak memory 201296 kb
Host smart-fd5371de-f31f-4814-b457-4d2aef13ca71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811274420 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.1811274420
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.604875129
Short name T426
Test name
Test status
Simulation time 5937968716 ps
CPU time 6.97 seconds
Started Mar 10 12:29:17 PM PDT 24
Finished Mar 10 12:29:24 PM PDT 24
Peak memory 201452 kb
Host smart-4d9b4f22-7e56-4f06-8c67-1fe748bef9c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604875129 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.604875129
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.2983062398
Short name T665
Test name
Test status
Simulation time 6588567410 ps
CPU time 15.09 seconds
Started Mar 10 12:29:21 PM PDT 24
Finished Mar 10 12:29:38 PM PDT 24
Peak memory 201112 kb
Host smart-4e369494-96e0-478e-ae09-7d5b468bbeec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983062398 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.
2983062398
Directory /workspace/9.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.1200871422
Short name T108
Test name
Test status
Simulation time 114906202753 ps
CPU time 77.02 seconds
Started Mar 10 12:29:11 PM PDT 24
Finished Mar 10 12:30:29 PM PDT 24
Peak memory 209932 kb
Host smart-c9e4bc27-81e8-4f8a-a788-1326a6b8dc67
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200871422 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.1200871422
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest
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