Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1185939	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1155735

1

T1

64

T2

34

T3

3931

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2046938	1			T1	81		T3	6883		T4	2538
values[0x0]	146696	1			T1	36		T2	29		T3	579
values[0x1]	148040	1			T1	27		T2	29		T3	585

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	949597	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1392077

1

T1

76

T2

36

T3

4714

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	6310	1			T3	20		T4	2		T6	3
valid_sources[0x01]	6132	1			T3	54		T4	6		T6	1
valid_sources[0x02]	7307	1			T3	27		T4	1		T6	2
valid_sources[0x03]	7764	1			T3	33		T4	5		T6	8
valid_sources[0x04]	6589	1			T3	22		T4	3		T6	4
valid_sources[0x05]	8297	1			T3	40		T4	4		T6	5
valid_sources[0x06]	7597	1			T3	37		T4	3		T7	15
valid_sources[0x07]	6287	1			T3	37		T4	4		T6	2
valid_sources[0x08]	6680	1			T3	31		T4	5		T6	5
valid_sources[0x09]	6828	1			T3	32		T4	4		T6	3
valid_sources[0x0a]	7267	1			T3	42		T4	7		T6	3
valid_sources[0x0b]	11734	1			T3	32		T4	3		T6	2
valid_sources[0x0c]	6384	1			T3	52		T4	3		T6	2
valid_sources[0x0d]	6275	1			T3	46		T4	1		T6	7
valid_sources[0x0e]	7196	1			T3	15		T6	6		T7	10
valid_sources[0x0f]	7353	1			T3	25		T4	4		T6	1
valid_sources[0x10]	5803	1			T3	30		T4	2		T8	21
valid_sources[0x11]	6513	1			T3	53		T4	1		T7	7
valid_sources[0x12]	11779	1			T3	43		T4	959		T6	4
valid_sources[0x13]	7311	1			T3	31		T4	4		T6	6
valid_sources[0x14]	6650	1			T3	25		T4	5		T6	4
valid_sources[0x15]	6457	1			T3	30		T4	1		T6	1
valid_sources[0x16]	6430	1			T3	36		T4	1		T6	3
valid_sources[0x17]	9240	1			T3	27		T4	2		T6	3
valid_sources[0x18]	11280	1			T3	3		T4	6		T6	7
valid_sources[0x19]	7160	1			T3	26		T4	3		T6	5
valid_sources[0x1a]	6678	1			T3	37		T4	5		T6	5
valid_sources[0x1b]	6671	1			T3	29		T4	7		T6	9
valid_sources[0x1c]	20168	1			T3	13		T4	6		T6	4
valid_sources[0x1d]	9333	1			T3	46		T6	1		T7	2
valid_sources[0x1e]	16914	1			T3	29		T4	3		T6	10
valid_sources[0x1f]	6586	1			T3	28		T4	3		T6	5
valid_sources[0x20]	6704	1			T3	37		T4	2		T6	2
valid_sources[0x21]	15283	1			T3	45		T4	3		T6	4
valid_sources[0x22]	8048	1			T3	25		T4	3		T6	6
valid_sources[0x23]	6635	1			T3	26		T4	3		T6	8
valid_sources[0x24]	8304	1			T3	62		T4	5		T6	1
valid_sources[0x25]	9101	1			T3	31		T4	2		T6	5
valid_sources[0x26]	10576	1			T3	30		T4	7		T6	1
valid_sources[0x27]	6241	1			T3	35		T4	6		T6	12
valid_sources[0x28]	6313	1			T3	35		T4	5		T6	2
valid_sources[0x29]	6613	1			T3	45		T4	8		T6	2
valid_sources[0x2a]	7725	1			T3	44		T4	5		T6	5
valid_sources[0x2b]	6794	1			T3	28		T4	5		T6	8
valid_sources[0x2c]	6756	1			T3	67		T4	4		T7	13
valid_sources[0x2d]	6738	1			T3	26		T4	1		T8	5
valid_sources[0x2e]	7430	1			T3	42		T4	4		T6	1
valid_sources[0x2f]	9406	1			T3	21		T4	4		T6	7
valid_sources[0x30]	9047	1			T3	30		T4	4		T6	4
valid_sources[0x31]	6613	1			T3	48		T4	3		T6	3
valid_sources[0x32]	6497	1			T3	25		T4	2		T6	2
valid_sources[0x33]	6026	1			T3	66		T4	3		T6	2
valid_sources[0x34]	15043	1			T3	34		T4	3		T6	4
valid_sources[0x35]	10752	1			T3	27		T4	3		T6	4
valid_sources[0x36]	10372	1			T3	22		T4	1		T6	2
valid_sources[0x37]	6671	1			T3	20		T4	4		T6	2
valid_sources[0x38]	6349	1			T3	30		T4	4		T6	6
valid_sources[0x39]	10458	1			T3	33		T4	3		T6	5
valid_sources[0x3a]	7795	1			T3	43		T4	5		T6	1
valid_sources[0x3b]	10626	1			T3	30		T4	3		T6	3
valid_sources[0x3c]	11183	1			T3	42		T4	5		T6	4
valid_sources[0x3d]	11002	1			T3	42		T4	2		T6	7
valid_sources[0x3e]	6201	1			T3	16		T4	2		T6	1
valid_sources[0x3f]	10224	1			T3	40		T4	5		T6	5
valid_sources[0x40]	6623	1			T3	27		T4	6		T6	5
valid_sources[0x41]	8129	1			T3	38		T4	1		T6	2
valid_sources[0x42]	6358	1			T3	21		T4	9		T6	6
valid_sources[0x43]	18346	1			T3	44		T4	2		T6	2
valid_sources[0x44]	6537	1			T3	27		T4	5		T6	1
valid_sources[0x45]	10768	1			T3	24		T4	4		T6	2
valid_sources[0x46]	6316	1			T3	25		T6	4		T7	7
valid_sources[0x47]	7007	1			T3	35		T4	3		T6	5
valid_sources[0x48]	11663	1			T3	30		T4	3		T6	5
valid_sources[0x49]	11372	1			T3	22		T4	6		T6	7
valid_sources[0x4a]	6777	1			T3	17		T4	7		T6	7
valid_sources[0x4b]	9151	1			T3	35		T4	1		T6	4
valid_sources[0x4c]	12162	1			T3	11		T4	1		T6	8
valid_sources[0x4d]	6173	1			T3	24		T4	6		T6	2
valid_sources[0x4e]	10329	1			T3	27		T4	2		T6	3
valid_sources[0x4f]	6235	1			T3	48		T4	4		T6	6
valid_sources[0x50]	6515	1			T3	22		T4	6		T6	2
valid_sources[0x51]	6765	1			T3	18		T4	4		T6	3
valid_sources[0x52]	6484	1			T3	35		T4	8		T6	5
valid_sources[0x53]	6030	1			T3	15		T4	6		T6	5
valid_sources[0x54]	10552	1			T3	55		T4	5		T7	10
valid_sources[0x55]	11657	1			T3	35		T4	5		T6	4
valid_sources[0x56]	6606	1			T3	20		T4	6		T6	3
valid_sources[0x57]	20329	1			T3	39		T4	4		T6	2
valid_sources[0x58]	8588	1			T3	30		T4	4		T6	5
valid_sources[0x59]	7422	1			T3	28		T4	3		T7	7
valid_sources[0x5a]	9727	1			T3	16		T4	4		T6	2
valid_sources[0x5b]	7500	1			T3	19		T4	1		T5	1
valid_sources[0x5c]	6293	1			T3	32		T4	9		T6	3
valid_sources[0x5d]	6650	1			T3	24		T4	4		T6	8
valid_sources[0x5e]	19404	1			T3	41		T4	3		T6	1
valid_sources[0x5f]	8119	1			T3	37		T4	3		T6	4
valid_sources[0x60]	6366	1			T3	42		T4	2		T6	6
valid_sources[0x61]	6060	1			T3	48		T4	4		T6	11
valid_sources[0x62]	9541	1			T3	33		T4	1		T7	18
valid_sources[0x63]	8207	1			T3	24		T4	928		T6	6
valid_sources[0x64]	6444	1			T3	24		T4	4		T6	2
valid_sources[0x65]	13785	1			T3	13		T4	1		T6	11
valid_sources[0x66]	6764	1			T1	144		T3	18		T4	3
valid_sources[0x67]	6784	1			T3	58		T4	2		T6	6
valid_sources[0x68]	6492	1			T3	31		T4	4		T6	1
valid_sources[0x69]	7590	1			T3	32		T4	3		T6	3
valid_sources[0x6a]	6613	1			T3	39		T4	3		T6	3
valid_sources[0x6b]	10764	1			T3	23		T4	5		T7	4
valid_sources[0x6c]	10875	1			T3	13		T4	6		T6	8
valid_sources[0x6d]	8674	1			T3	32		T4	2		T6	4
valid_sources[0x6e]	6585	1			T3	32		T4	4		T6	3
valid_sources[0x6f]	15091	1			T3	36		T4	3		T6	1
valid_sources[0x70]	9440	1			T3	29		T4	3		T6	4
valid_sources[0x71]	19043	1			T3	29		T4	5		T6	3
valid_sources[0x72]	9407	1			T3	39		T4	2		T5	924
valid_sources[0x73]	6258	1			T3	38		T4	3		T6	3
valid_sources[0x74]	13369	1			T3	8		T4	6		T6	1
valid_sources[0x75]	6676	1			T3	19		T4	3		T6	2
valid_sources[0x76]	6307	1			T3	47		T4	4		T6	2
valid_sources[0x77]	6496	1			T3	19		T4	2		T6	5
valid_sources[0x78]	10568	1			T3	30		T4	1		T6	1
valid_sources[0x79]	7077	1			T3	26		T4	3		T6	1
valid_sources[0x7a]	8872	1			T3	39		T4	7		T6	7
valid_sources[0x7b]	6618	1			T3	36		T4	3		T6	7
valid_sources[0x7c]	11387	1			T3	25		T4	2		T6	2
valid_sources[0x7d]	9003	1			T3	29		T4	5		T6	1
valid_sources[0x7e]	7625	1			T3	25		T4	4		T6	6
valid_sources[0x7f]	6488	1			T3	32		T4	4		T6	6
valid_sources[0x80]	6274	1			T3	39		T4	2		T7	16

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1018670

1

T1

44

T3

3418

T4

1269

values[0x0]

all_enables

biggest_size

79816

1

T1

13

T2

19

T3

298

values[0x1]

all_enables

biggest_size

57249

1

T1

7

T2

15

T3

215