Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
93.33	93.33	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	93.33	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.33	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	3	42	93.33

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	0	17	100.00	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	3	13	81.25	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	0	17	100.00

Automatically Generated Bins for fsm_state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	31019	1			T3	53		T4	26		T5	7
auto[PWRUP]	114	1			T39	2		T31	1		T40	1
auto[ONEST_0]	73	1			T8	1		T31	1		T40	1
auto[ONEST_021]	16	1			T39	1		T306	1		T36	1
auto[ONEST_1]	88	1			T8	3		T40	1		T32	2
auto[ONEST_DONE]	6	1			T42	1		T307	1		T308	1
auto[LP_0]	121	1			T39	4		T32	1		T44	3
auto[LP_021]	33	1			T8	2		T32	1		T44	2
auto[LP_1]	137	1			T39	1		T44	4		T41	2
auto[LP_EVAL]	75	1			T3	1		T39	3		T32	1
auto[LP_SLP]	574	1			T3	2		T8	2		T39	8
auto[LP_PWRUP]	36	1			T39	1		T41	1		T42	3
auto[NP_0]	156	1			T3	2		T39	1		T32	2
auto[NP_021]	39	1			T309	2		T43	1		T153	2
auto[NP_1]	170	1			T3	1		T39	2		T40	2
auto[NP_EVAL]	43	1			T39	1		T40	1		T32	1
auto[NP_DONE]	1	1			T228	1		-	-		-	-

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

7

1

T39

1

T310

1

T311

2

min

30577

1

T3

54

T4

26

T5

7

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	30583	1			T3	54		T4	26		T5	7
pow[0x1]	8	1			T42	1		T153	1		T312	1
pow[0x2]	20	1			T42	2		T313	1		T17	1
pow[0x3]	30	1			T8	1		T306	1		T310	1
pow[0x4]	62	1			T8	1		T39	2		T32	2
pow[0x5]	125	1			T8	1		T39	2		T40	2
pow[0x6]	274	1			T8	1		T39	1		T31	1
pow[0x7]	534	1			T3	2		T8	2		T39	5

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

202

1

T8

2

T39

6

T31

1

min

30039

1

T3

52

T4

26

T5

7

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	3	13	81.25

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x2]	0	1	1
pow[0x4]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	30039	1			T3	52		T4	26		T5	7
pow[0x3]	1	1			T314	1		-	-		-	-
pow[0x5]	2	1			T306	1		T227	1		-	-
pow[0x6]	3	1			T42	1		T313	1		T188	1
pow[0x7]	2	1			T44	1		T315	1		-	-
pow[0x8]	9	1			T42	1		T14	1		T88	1
pow[0x9]	10	1			T310	1		T307	1		T316	1
pow[0xa]	26	1			T39	1		T42	1		T34	1
pow[0xb]	41	1			T39	2		T44	2		T41	1
pow[0xc]	70	1			T8	1		T32	1		T44	1
pow[0xd]	143	1			T39	1		T31	2		T40	2
pow[0xe]	297	1			T3	1		T8	1		T39	5
pow[0xf]	605	1			T3	1		T8	3		T39	6