Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.56	95.56	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	95.56	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.56	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	2	43	95.56

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	1	15	93.75	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2332	1			T3	23		T8	19		T37	4
auto[PWRUP]	139	1			T3	1		T8	2		T39	2
auto[ONEST_0]	93	1			T3	1		T8	1		T31	1
auto[ONEST_021]	28	1			T31	1		T44	1		T42	1
auto[ONEST_1]	99	1			T39	2		T40	1		T33	1
auto[ONEST_DONE]	1	1			T317	1		-	-		-	-
auto[LP_0]	142	1			T3	1		T8	1		T39	3
auto[LP_021]	27	1			T3	1		T41	1		T42	2
auto[LP_1]	141	1			T8	1		T39	2		T40	1
auto[LP_EVAL]	54	1			T3	1		T8	1		T31	1
auto[LP_SLP]	547	1			T3	4		T8	3		T39	9
auto[LP_PWRUP]	24	1			T41	2		T309	1		T36	1
auto[NP_0]	220	1			T3	2		T8	5		T39	4
auto[NP_021]	57	1			T3	2		T30	1		T40	1
auto[NP_1]	227	1			T3	3		T8	1		T30	1
auto[NP_EVAL]	35	1			T32	2		T44	1		T310	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

8

1

T3

1

T318

1

T227

1

min

1962

1

T3

28

T8

20

T37

4

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1984	1			T3	28		T8	20		T37	4
pow[0x1]	16	1			T8	1		T39	1		T84	1
pow[0x2]	25	1			T32	1		T44	2		T310	1
pow[0x3]	31	1			T40	1		T306	1		T310	1
pow[0x4]	64	1			T3	1		T31	1		T32	2
pow[0x5]	120	1			T3	1		T8	1		T40	2
pow[0x6]	301	1			T3	3		T8	4		T39	3
pow[0x7]	525	1			T8	3		T39	7		T31	3

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

178

1

T39

1

T31

1

T40

1

min

1381

1

T3

20

T8

16

T37

4

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	1	15	93.75

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x5]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1387	1			T3	20		T8	16		T37	4
pow[0x1]	10	1			T8	1		T154	1		T271	1
pow[0x2]	13	1			T30	1		T31	1		T32	2
pow[0x3]	31	1			T3	2		T33	2		T34	1
pow[0x4]	70	1			T3	2		T8	4		T30	1
pow[0x6]	1	1			T308	1		-	-		-	-
pow[0x7]	1	1			T309	1		-	-		-	-
pow[0x8]	5	1			T306	1		T310	1		T36	1
pow[0x9]	10	1			T43	1		T314	1		T319	1
pow[0xa]	25	1			T44	1		T42	2		T320	2
pow[0xb]	22	1			T3	1		T306	1		T309	2
pow[0xc]	77	1			T8	1		T39	1		T32	1
pow[0xd]	161	1			T3	2		T8	1		T39	4
pow[0xe]	320	1			T3	2		T8	1		T39	4
pow[0xf]	626	1			T3	1		T8	1		T39	11