Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1147798	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1116908

1

T1

474

T2

890

T3

16

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1979682	1			T1	845		T2	1645		T4	4007
values[0x0]	142211	1			T1	48		T2	97		T3	19
values[0x1]	142813	1			T1	48		T2	111		T3	18

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	919882	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1344824

1

T1

554

T2

1085

T3

20

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	6951	1			T1	3		T2	11		T4	18
valid_sources[0x01]	9294	1			T1	4		T2	11		T4	14
valid_sources[0x02]	6835	1			T1	5		T2	15		T4	10
valid_sources[0x03]	7652	1			T1	4		T2	6		T4	10
valid_sources[0x04]	15452	1			T1	4		T2	1		T4	11
valid_sources[0x05]	6439	1			T1	3		T2	13		T4	23
valid_sources[0x06]	7530	1			T1	6		T2	9		T4	16
valid_sources[0x07]	6628	1			T1	4		T2	8		T4	16
valid_sources[0x08]	7754	1			T1	4		T2	5		T4	14
valid_sources[0x09]	8779	1			T1	3		T2	7		T4	17
valid_sources[0x0a]	6666	1			T1	6		T2	4		T4	17
valid_sources[0x0b]	7701	1			T1	5		T2	7		T4	20
valid_sources[0x0c]	11624	1			T1	1		T2	3		T4	14
valid_sources[0x0d]	8815	1			T1	1		T2	13		T4	20
valid_sources[0x0e]	6593	1			T1	3		T2	7		T4	16
valid_sources[0x0f]	6809	1			T2	16		T4	18		T6	35
valid_sources[0x10]	11201	1			T1	3		T2	5		T4	16
valid_sources[0x11]	6595	1			T1	3		T2	7		T4	14
valid_sources[0x12]	6744	1			T1	7		T2	3		T4	18
valid_sources[0x13]	11126	1			T1	2		T2	5		T4	13
valid_sources[0x14]	10806	1			T2	11		T4	18		T6	7
valid_sources[0x15]	9989	1			T1	4		T2	2		T4	15
valid_sources[0x16]	10640	1			T1	5		T2	4		T4	14
valid_sources[0x17]	6522	1			T1	3		T2	7		T4	20
valid_sources[0x18]	7078	1			T1	5		T2	9		T4	13
valid_sources[0x19]	6797	1			T1	3		T2	8		T4	18
valid_sources[0x1a]	6974	1			T1	7		T2	11		T4	22
valid_sources[0x1b]	7520	1			T1	4		T2	7		T4	18
valid_sources[0x1c]	6720	1			T1	2		T2	2		T4	12
valid_sources[0x1d]	6850	1			T1	7		T2	4		T4	18
valid_sources[0x1e]	8572	1			T1	7		T2	4		T4	18
valid_sources[0x1f]	16290	1			T1	6		T2	9		T4	9
valid_sources[0x20]	6975	1			T1	5		T2	2		T4	13
valid_sources[0x21]	6700	1			T1	5		T2	3		T4	25
valid_sources[0x22]	16297	1			T1	5		T2	7		T4	19
valid_sources[0x23]	6647	1			T1	5		T2	3		T4	12
valid_sources[0x24]	13268	1			T1	4		T2	6		T4	26
valid_sources[0x25]	11558	1			T1	7		T2	12		T4	16
valid_sources[0x26]	6615	1			T1	5		T2	4		T4	13
valid_sources[0x27]	7841	1			T1	3		T2	16		T4	14
valid_sources[0x28]	7344	1			T1	6		T2	11		T4	24
valid_sources[0x29]	17195	1			T1	3		T2	12		T4	13
valid_sources[0x2a]	11279	1			T1	3		T2	7		T4	13
valid_sources[0x2b]	6605	1			T1	3		T2	6		T4	17
valid_sources[0x2c]	8840	1			T1	4		T2	6		T4	13
valid_sources[0x2d]	13227	1			T1	5		T2	18		T4	17
valid_sources[0x2e]	9610	1			T1	3		T2	8		T4	13
valid_sources[0x2f]	6700	1			T1	8		T2	6		T4	17
valid_sources[0x30]	9939	1			T1	3		T2	10		T4	9
valid_sources[0x31]	6694	1			T1	10		T2	11		T4	15
valid_sources[0x32]	6907	1			T1	4		T2	7		T4	18
valid_sources[0x33]	11109	1			T1	8		T2	5		T4	13
valid_sources[0x34]	7042	1			T1	6		T2	8		T4	17
valid_sources[0x35]	9669	1			T1	3		T2	9		T4	14
valid_sources[0x36]	6909	1			T1	1		T2	5		T4	20
valid_sources[0x37]	6949	1			T1	3		T2	8		T4	12
valid_sources[0x38]	8126	1			T1	3		T2	6		T4	19
valid_sources[0x39]	6809	1			T1	4		T2	8		T4	14
valid_sources[0x3a]	6977	1			T1	1		T2	8		T4	15
valid_sources[0x3b]	7708	1			T1	4		T2	5		T4	17
valid_sources[0x3c]	9448	1			T1	6		T2	5		T3	37
valid_sources[0x3d]	6548	1			T1	1		T2	7		T4	14
valid_sources[0x3e]	7356	1			T1	3		T2	11		T4	17
valid_sources[0x3f]	6622	1			T1	3		T2	7		T4	23
valid_sources[0x40]	7427	1			T1	7		T2	7		T4	21
valid_sources[0x41]	7659	1			T1	5		T2	9		T4	16
valid_sources[0x42]	8016	1			T1	2		T2	11		T4	14
valid_sources[0x43]	6552	1			T1	3		T2	11		T4	16
valid_sources[0x44]	7039	1			T2	3		T4	19		T6	8
valid_sources[0x45]	8126	1			T1	7		T2	7		T4	15
valid_sources[0x46]	6477	1			T1	2		T2	8		T4	22
valid_sources[0x47]	8022	1			T1	1		T2	6		T4	9
valid_sources[0x48]	12035	1			T1	1		T2	8		T4	17
valid_sources[0x49]	6693	1			T1	3		T2	10		T4	18
valid_sources[0x4a]	6771	1			T1	6		T2	11		T4	16
valid_sources[0x4b]	9585	1			T1	2		T2	6		T4	13
valid_sources[0x4c]	11527	1			T1	2		T2	7		T4	14
valid_sources[0x4d]	11733	1			T1	2		T2	7		T4	23
valid_sources[0x4e]	6738	1			T1	2		T2	7		T4	15
valid_sources[0x4f]	7013	1			T1	2		T2	3		T4	12
valid_sources[0x50]	6443	1			T1	2		T2	7		T4	17
valid_sources[0x51]	11202	1			T1	2		T2	11		T4	11
valid_sources[0x52]	6600	1			T1	2		T2	12		T4	13
valid_sources[0x53]	7601	1			T1	3		T2	6		T4	16
valid_sources[0x54]	15554	1			T1	4		T2	8		T4	23
valid_sources[0x55]	9654	1			T1	3		T2	5		T4	16
valid_sources[0x56]	10814	1			T1	3		T2	4		T4	15
valid_sources[0x57]	9035	1			T1	3		T2	10		T4	7
valid_sources[0x58]	6870	1			T1	2		T2	4		T4	16
valid_sources[0x59]	9797	1			T1	5		T2	9		T4	23
valid_sources[0x5a]	10758	1			T1	2		T2	6		T4	19
valid_sources[0x5b]	7070	1			T1	7		T2	4		T4	16
valid_sources[0x5c]	19700	1			T1	2		T2	10		T4	30
valid_sources[0x5d]	7153	1			T1	1		T2	4		T4	19
valid_sources[0x5e]	10768	1			T1	3		T2	3		T4	21
valid_sources[0x5f]	6564	1			T1	5		T2	7		T4	16
valid_sources[0x60]	6970	1			T1	1		T2	9		T4	18
valid_sources[0x61]	7248	1			T1	1		T2	6		T4	19
valid_sources[0x62]	10922	1			T1	4		T2	2		T4	23
valid_sources[0x63]	12741	1			T1	1		T2	4		T4	17
valid_sources[0x64]	13808	1			T1	3		T2	5		T4	15
valid_sources[0x65]	12421	1			T1	6		T2	8		T4	14
valid_sources[0x66]	14905	1			T1	2		T2	15		T4	18
valid_sources[0x67]	6924	1			T1	3		T2	4		T4	18
valid_sources[0x68]	11808	1			T1	4		T2	6		T4	25
valid_sources[0x69]	7135	1			T1	2		T2	6		T4	18
valid_sources[0x6a]	6800	1			T1	3		T2	12		T4	22
valid_sources[0x6b]	7544	1			T1	5		T2	5		T4	29
valid_sources[0x6c]	11174	1			T1	2		T2	10		T4	19
valid_sources[0x6d]	7951	1			T1	9		T2	6		T4	18
valid_sources[0x6e]	7888	1			T1	4		T2	4		T4	16
valid_sources[0x6f]	7920	1			T1	5		T2	11		T4	16
valid_sources[0x70]	7054	1			T1	5		T2	11		T4	9
valid_sources[0x71]	11214	1			T1	4		T2	6		T4	19
valid_sources[0x72]	7246	1			T1	1		T2	3		T4	15
valid_sources[0x73]	9158	1			T1	5		T2	5		T4	14
valid_sources[0x74]	13966	1			T1	8		T2	7		T4	24
valid_sources[0x75]	6855	1			T1	2		T2	6		T4	14
valid_sources[0x76]	6742	1			T1	2		T2	10		T4	13
valid_sources[0x77]	6738	1			T1	1		T2	3		T4	9
valid_sources[0x78]	9627	1			T1	1		T2	5		T4	26
valid_sources[0x79]	7558	1			T1	1		T2	7		T4	14
valid_sources[0x7a]	7081	1			T1	2		T2	2		T4	17
valid_sources[0x7b]	10018	1			T1	5		T2	5		T4	19
valid_sources[0x7c]	11276	1			T1	5		T2	11		T4	17
valid_sources[0x7d]	7285	1			T1	3		T2	10		T4	23
valid_sources[0x7e]	6507	1			T1	6		T2	12		T4	18
valid_sources[0x7f]	10005	1			T1	3		T2	15		T4	14
valid_sources[0x80]	12878	1			T1	5		T2	8		T4	18

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

985026

1

T1

428

T2

795

T4

2018

values[0x0]

all_enables

biggest_size

76851

1

T1

26

T2

58

T3

10

values[0x1]

all_enables

biggest_size

55031

1

T1

20

T2

37

T3

6