Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
91.11	91.11	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	91.11	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.11	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	4	41	91.11

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	3	13	81.25	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	27769	1			T1	9		T2	14		T4	11
auto[PWRUP]	129	1			T8	2		T9	1		T13	1
auto[ONEST_0]	80	1			T52	2		T16	1		T53	3
auto[ONEST_021]	15	1			T203	1		T204	1		T186	1
auto[ONEST_1]	83	1			T8	3		T15	1		T52	3
auto[ONEST_DONE]	6	1			T54	1		T205	1		T116	1
auto[LP_0]	119	1			T9	1		T52	2		T16	1
auto[LP_021]	31	1			T9	2		T52	1		T53	1
auto[LP_1]	128	1			T8	2		T53	2		T206	2
auto[LP_EVAL]	66	1			T52	1		T206	3		T207	1
auto[LP_SLP]	521	1			T8	6		T9	5		T13	1
auto[LP_PWRUP]	16	1			T9	1		T204	1		T55	1
auto[NP_0]	158	1			T9	3		T52	2		T16	3
auto[NP_021]	31	1			T52	1		T53	1		T145	1
auto[NP_1]	169	1			T8	1		T9	4		T52	4
auto[NP_EVAL]	42	1			T8	1		T52	1		T16	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

7

1

T206

1

T207

1

T145

1

min

27243

1

T1

9

T2

14

T4

11

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	27257	1			T1	9		T2	14		T4	11
pow[0x1]	9	1			T145	2		T55	2		T208	1
pow[0x2]	23	1			T145	1		T153	1		T209	1
pow[0x3]	21	1			T9	1		T209	1		T54	1
pow[0x4]	72	1			T9	2		T53	2		T207	1
pow[0x5]	138	1			T9	2		T52	2		T53	3
pow[0x6]	270	1			T8	1		T9	1		T52	6
pow[0x7]	547	1			T8	8		T9	6		T15	1

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

216

1

T8

2

T9

2

T52

1

min

26769

1

T1

9

T2

14

T4

11

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	3	13	81.25

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x2]	0	1	1
pow[0x3]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	26769	1			T1	9		T2	14		T4	11
pow[0x4]	3	1			T145	1		T210	1		T211	1
pow[0x5]	2	1			T145	1		T212	1		-	-
pow[0x6]	3	1			T213	1		T214	1		T215	1
pow[0x7]	3	1			T206	1		T216	1		T217	1
pow[0x8]	3	1			T218	1		T219	1		T220	1
pow[0x9]	11	1			T221	1		T209	1		T222	1
pow[0xa]	17	1			T206	1		T209	1		T213	1
pow[0xb]	38	1			T15	1		T207	2		T153	1
pow[0xc]	66	1			T52	2		T206	3		T207	1
pow[0xd]	154	1			T8	3		T9	2		T15	1
pow[0xe]	299	1			T8	5		T9	3		T15	1
pow[0xf]	600	1			T8	5		T9	13		T13	1