Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.56	95.56	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	95.56	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.56	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	2	43	95.56

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	1	15	93.75	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2310	1			T8	15		T9	9		T10	5
auto[PWRUP]	148	1			T8	2		T52	1		T16	3
auto[ONEST_0]	78	1			T8	2		T9	1		T53	2
auto[ONEST_021]	32	1			T8	1		T9	2		T52	1
auto[ONEST_1]	87	1			T8	4		T9	1		T11	1
auto[ONEST_DONE]	6	1			T207	1		T145	1		T351	1
auto[LP_0]	119	1			T9	5		T15	1		T52	1
auto[LP_021]	23	1			T8	1		T53	1		T207	1
auto[LP_1]	137	1			T9	2		T52	3		T16	1
auto[LP_EVAL]	73	1			T52	3		T16	1		T40	1
auto[LP_SLP]	523	1			T8	8		T9	8		T15	1
auto[LP_PWRUP]	24	1			T8	1		T52	1		T16	1
auto[NP_0]	231	1			T8	3		T11	3		T13	1
auto[NP_021]	46	1			T52	1		T16	1		T53	2
auto[NP_1]	250	1			T8	1		T9	4		T11	1
auto[NP_EVAL]	34	1			T52	1		T53	1		T206	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

8

1

T9

1

T207

1

T216

1

min

1912

1

T8

9

T9

10

T10

5

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1932	1			T8	9		T9	10		T10	5
pow[0x1]	12	1			T9	1		T206	1		T145	1
pow[0x2]	28	1			T8	1		T9	1		T53	1
pow[0x3]	43	1			T40	1		T53	1		T43	1
pow[0x4]	69	1			T8	1		T52	1		T16	2
pow[0x5]	123	1			T8	3		T9	1		T13	1
pow[0x6]	274	1			T8	2		T9	1		T52	3
pow[0x7]	532	1			T8	5		T9	7		T13	2

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

178

1

T8

4

T9

1

T13

1

min

1358

1

T8

1

T9

3

T10

5

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	1	15	93.75

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x6]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1368	1			T8	1		T9	3		T10	5
pow[0x1]	15	1			T18	4		T246	1		T55	1
pow[0x2]	14	1			T11	3		T43	3		T286	1
pow[0x3]	48	1			T15	3		T40	1		T41	2
pow[0x4]	50	1			T11	1		T13	1		T16	4
pow[0x5]	1	1			T217	1		-	-		-	-
pow[0x7]	3	1			T352	1		T330	1		T215	1
pow[0x8]	2	1			T205	1		T208	1		-	-
pow[0x9]	6	1			T52	1		T55	1		T353	1
pow[0xa]	17	1			T55	1		T187	1		T56	1
pow[0xb]	35	1			T8	1		T53	1		T203	1
pow[0xc]	96	1			T8	2		T9	1		T13	1
pow[0xd]	144	1			T8	1		T9	2		T52	1
pow[0xe]	296	1			T8	4		T9	4		T13	2
pow[0xf]	617	1			T8	9		T9	7		T15	2