Unified Coverage Report :: Module :: adc_ctrl_core

Module : adc_ctrl_core

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_adc_ctrl_core	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_adc_ctrl_core

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.83	100.00	99.76		100.00	99.37	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_adc_ctrl_fsm	99.75	100.00	100.00		100.00	98.73	100.00
u_adc_ctrl_intr	99.00	100.00	96.00			100.00	100.00
u_oneshot_done_sync	100.00	100.00	100.00			100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : adc_ctrl_core

	Line No.	Total	Covered	Percent
TOTAL		63	63	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	73	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	83	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	137	1	1	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	213	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv' or '../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	8	8
63	8	8
72	1	1
73	1	1
74	1	1
75	1	1
83	1	1
86	1	1
87	1	1
88	1	1
89	1	1
104	8	8
107	8	8
117	8	8
121	8	8
137	1	1
138	1	1
140	1	1
141	1	1
145	1	1
213	1	1

---

Cond Coverage for Module : adc_ctrl_core

	Total	Covered	Percent
Conditions	293	293	100.00
Logical	293	293	100.00
Non-Logical	0	0
Event	0	0

 LINE       83
 EXPRESSION (reg2hw_i.adc_en_ctl.oneshot_mode.q ? oneshot_done : (reg2hw_i.adc_en_ctl.adc_enable.q ? ((|match_pulse)) : '0))
             -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T8,T9,T10

 LINE       83
 SUB-EXPRESSION (reg2hw_i.adc_en_ctl.adc_enable.q ? ((|match_pulse)) : '0)
                 ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][0].cond)) ? ((aon_filter_ctl[0][0].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][0].max_v)) : ((aon_filter_ctl[0][0].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][0].max_v)))

-1-	Status	Tests
0	Covered	T1,T5,T6
1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][0].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][0].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T7
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][0].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][0].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T6
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T6

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][1].cond)) ? ((aon_filter_ctl[0][1].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][1].max_v)) : ((aon_filter_ctl[0][1].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][1].max_v)))

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][1].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][1].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][1].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][1].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][2].cond)) ? ((aon_filter_ctl[0][2].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][2].max_v)) : ((aon_filter_ctl[0][2].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][2].max_v)))

-1-	Status	Tests
0	Covered	T4,T6,T10
1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][2].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][2].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][2].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][2].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T10
0	1	Covered	T4,T6,T10
1	0	Covered	T4,T6,T10

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][3].cond)) ? ((aon_filter_ctl[0][3].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][3].max_v)) : ((aon_filter_ctl[0][3].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][3].max_v)))

-1-	Status	Tests
0	Covered	T6,T10,T11
1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][3].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][3].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][3].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][3].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T10,T47
0	1	Covered	T6,T10,T47
1	0	Covered	T6,T10,T11

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][4].cond)) ? ((aon_filter_ctl[0][4].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][4].max_v)) : ((aon_filter_ctl[0][4].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][4].max_v)))

-1-	Status	Tests
0	Covered	T6,T10,T13
1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][4].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][4].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][4].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][4].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T10,T47
0	1	Covered	T6,T10,T47
1	0	Covered	T6,T10,T13

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][5].cond)) ? ((aon_filter_ctl[0][5].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][5].max_v)) : ((aon_filter_ctl[0][5].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][5].max_v)))

-1-	Status	Tests
0	Covered	T1,T13,T48
1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][5].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][5].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T3,T5
1	1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][5].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][5].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T48,T119
0	1	Covered	T1,T48,T119
1	0	Covered	T1,T13,T48

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][6].cond)) ? ((aon_filter_ctl[0][6].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][6].max_v)) : ((aon_filter_ctl[0][6].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][6].max_v)))

-1-	Status	Tests
0	Covered	T6,T10,T11
1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][6].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][6].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][6].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][6].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T10,T12
0	1	Covered	T6,T10,T12
1	0	Covered	T6,T10,T11

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][7].cond)) ? ((aon_filter_ctl[0][7].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][7].max_v)) : ((aon_filter_ctl[0][7].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][7].max_v)))

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][7].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][7].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T11
1	0	Covered	T3,T4,T6
1	1	Covered	T1,T2,T3

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][7].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][7].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T5
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T5

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][0].cond)) ? ((aon_filter_ctl[1][0].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][0].max_v)) : ((aon_filter_ctl[1][0].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][0].max_v)))

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][0].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][0].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T10
1	0	Covered	T2,T3,T7
1	1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][0].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][0].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][1].cond)) ? ((aon_filter_ctl[1][1].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][1].max_v)) : ((aon_filter_ctl[1][1].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][1].max_v)))

-1-	Status	Tests
0	Covered	T4,T6,T10
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][1].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][1].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][1].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][1].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T10
0	1	Covered	T4,T6,T10
1	0	Covered	T4,T6,T10

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][2].cond)) ? ((aon_filter_ctl[1][2].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][2].max_v)) : ((aon_filter_ctl[1][2].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][2].max_v)))

-1-	Status	Tests
0	Covered	T4,T6,T10
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][2].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][2].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][2].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][2].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T10
0	1	Covered	T4,T6,T10
1	0	Covered	T4,T6,T10

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][3].cond)) ? ((aon_filter_ctl[1][3].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][3].max_v)) : ((aon_filter_ctl[1][3].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][3].max_v)))

-1-	Status	Tests
0	Covered	T6,T10,T11
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][3].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][3].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][3].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][3].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T10,T11
0	1	Covered	T6,T10,T47
1	0	Covered	T6,T10,T11

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][4].cond)) ? ((aon_filter_ctl[1][4].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][4].max_v)) : ((aon_filter_ctl[1][4].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][4].max_v)))

-1-	Status	Tests
0	Covered	T6,T10,T13
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][4].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][4].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][4].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][4].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T10,T47
0	1	Covered	T6,T10,T47
1	0	Covered	T6,T10,T13

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][5].cond)) ? ((aon_filter_ctl[1][5].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][5].max_v)) : ((aon_filter_ctl[1][5].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][5].max_v)))

-1-	Status	Tests
0	Covered	T1,T13,T48
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][5].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][5].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T3,T5
1	1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][5].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][5].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T48,T119
0	1	Covered	T1,T48,T119
1	0	Covered	T1,T13,T48

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][6].cond)) ? ((aon_filter_ctl[1][6].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][6].max_v)) : ((aon_filter_ctl[1][6].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][6].max_v)))

-1-	Status	Tests
0	Covered	T6,T10,T11
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][6].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][6].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][6].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][6].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T10,T12
0	1	Covered	T6,T10,T12
1	0	Covered	T6,T10,T11

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][7].cond)) ? ((aon_filter_ctl[1][7].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][7].max_v)) : ((aon_filter_ctl[1][7].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][7].max_v)))

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][7].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][7].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T11
1	0	Covered	T3,T4,T6
1	1	Covered	T1,T2,T3

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][7].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][7].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T5
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T5

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][0].en, aon_filter_ctl[1][0].en})) & 
      2  (((!aon_filter_ctl[0][0].en)) | (chn0_match[0] & aon_filter_ctl[0][0].en)) & 
      3  (((!aon_filter_ctl[1][0].en)) | (chn1_match[0] & aon_filter_ctl[1][0].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T5
1	1	0	Covered	T1,T2,T4
1	1	1	Covered	T1,T2,T4

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][0].en)) | (chn0_match[0] & aon_filter_ctl[0][0].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T5
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn0_match[0] & aon_filter_ctl[0][0].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T5

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][0].en)) | (chn1_match[0] & aon_filter_ctl[1][0].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn1_match[0] & aon_filter_ctl[1][0].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][1].en, aon_filter_ctl[1][1].en})) & 
      2  (((!aon_filter_ctl[0][1].en)) | (chn0_match[1] & aon_filter_ctl[0][1].en)) & 
      3  (((!aon_filter_ctl[1][1].en)) | (chn1_match[1] & aon_filter_ctl[1][1].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T1,T2,T4
1	1	1	Covered	T1,T2,T4

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][1].en)) | (chn0_match[1] & aon_filter_ctl[0][1].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn0_match[1] & aon_filter_ctl[0][1].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][1].en)) | (chn1_match[1] & aon_filter_ctl[1][1].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn1_match[1] & aon_filter_ctl[1][1].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][2].en, aon_filter_ctl[1][2].en})) & 
      2  (((!aon_filter_ctl[0][2].en)) | (chn0_match[2] & aon_filter_ctl[0][2].en)) & 
      3  (((!aon_filter_ctl[1][2].en)) | (chn1_match[2] & aon_filter_ctl[1][2].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T1,T2,T4
1	1	1	Covered	T1,T2,T4

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][2].en)) | (chn0_match[2] & aon_filter_ctl[0][2].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn0_match[2] & aon_filter_ctl[0][2].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][2].en)) | (chn1_match[2] & aon_filter_ctl[1][2].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn1_match[2] & aon_filter_ctl[1][2].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][3].en, aon_filter_ctl[1][3].en})) & 
      2  (((!aon_filter_ctl[0][3].en)) | (chn0_match[3] & aon_filter_ctl[0][3].en)) & 
      3  (((!aon_filter_ctl[1][3].en)) | (chn1_match[3] & aon_filter_ctl[1][3].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T5
1	1	0	Covered	T1,T2,T5
1	1	1	Covered	T1,T2,T5

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][3].en)) | (chn0_match[3] & aon_filter_ctl[0][3].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T5
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn0_match[3] & aon_filter_ctl[0][3].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T5

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][3].en)) | (chn1_match[3] & aon_filter_ctl[1][3].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T5
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn1_match[3] & aon_filter_ctl[1][3].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T5

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][4].en, aon_filter_ctl[1][4].en})) & 
      2  (((!aon_filter_ctl[0][4].en)) | (chn0_match[4] & aon_filter_ctl[0][4].en)) & 
      3  (((!aon_filter_ctl[1][4].en)) | (chn1_match[4] & aon_filter_ctl[1][4].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T6,T7
1	1	0	Covered	T2,T4,T5
1	1	1	Covered	T2,T4,T5

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][4].en)) | (chn0_match[4] & aon_filter_ctl[0][4].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T5
0	1	Covered	T2,T4,T5
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn0_match[4] & aon_filter_ctl[0][4].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T5

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][4].en)) | (chn1_match[4] & aon_filter_ctl[1][4].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T5
0	1	Covered	T2,T4,T5
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn1_match[4] & aon_filter_ctl[1][4].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T5

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][5].en, aon_filter_ctl[1][5].en})) & 
      2  (((!aon_filter_ctl[0][5].en)) | (chn0_match[5] & aon_filter_ctl[0][5].en)) & 
      3  (((!aon_filter_ctl[1][5].en)) | (chn1_match[5] & aon_filter_ctl[1][5].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T4,T6
1	1	0	Covered	T2,T6,T7
1	1	1	Covered	T2,T4,T6

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][5].en)) | (chn0_match[5] & aon_filter_ctl[0][5].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T6
0	1	Covered	T2,T4,T6
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn0_match[5] & aon_filter_ctl[0][5].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T6

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][5].en)) | (chn1_match[5] & aon_filter_ctl[1][5].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T6
0	1	Covered	T2,T4,T6
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn1_match[5] & aon_filter_ctl[1][5].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T6

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][6].en, aon_filter_ctl[1][6].en})) & 
      2  (((!aon_filter_ctl[0][6].en)) | (chn0_match[6] & aon_filter_ctl[0][6].en)) & 
      3  (((!aon_filter_ctl[1][6].en)) | (chn1_match[6] & aon_filter_ctl[1][6].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T1,T2,T4
1	1	1	Covered	T1,T2,T4

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][6].en)) | (chn0_match[6] & aon_filter_ctl[0][6].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn0_match[6] & aon_filter_ctl[0][6].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][6].en)) | (chn1_match[6] & aon_filter_ctl[1][6].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn1_match[6] & aon_filter_ctl[1][6].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][7].en, aon_filter_ctl[1][7].en})) & 
      2  (((!aon_filter_ctl[0][7].en)) | (chn0_match[7] & aon_filter_ctl[0][7].en)) & 
      3  (((!aon_filter_ctl[1][7].en)) | (chn1_match[7] & aon_filter_ctl[1][7].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T5
1	1	0	Covered	T1,T2,T5
1	1	1	Covered	T1,T2,T5

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][7].en)) | (chn0_match[7] & aon_filter_ctl[0][7].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T5
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn0_match[7] & aon_filter_ctl[0][7].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T5

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][7].en)) | (chn1_match[7] & aon_filter_ctl[1][7].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T5
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (chn1_match[7] & aon_filter_ctl[1][7].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T5

 LINE       121
 EXPRESSION (adc_ctrl_done && match[0])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       121
 EXPRESSION (adc_ctrl_done && match[1])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       121
 EXPRESSION (adc_ctrl_done && match[2])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       121
 EXPRESSION (adc_ctrl_done && match[3])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T5

 LINE       121
 EXPRESSION (adc_ctrl_done && match[4])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T4,T5

 LINE       121
 EXPRESSION (adc_ctrl_done && match[5])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T6
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T4,T6

 LINE       121
 EXPRESSION (adc_ctrl_done && match[6])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       121
 EXPRESSION (adc_ctrl_done && match[7])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T5

 LINE       140
 EXPRESSION (aon_fsm_trans | reg2hw_i.filter_status.trans.q)
             ------1------   ---------------2--------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T7,T47
1	0	Covered	T2,T7,T47

 LINE       145
 EXPRESSION (((|(reg2hw_i.filter_status.match.q & reg2hw_i.adc_wakeup_ctl.match_en.q))) || (reg2hw_i.filter_status.trans.q & reg2hw_i.adc_wakeup_ctl.trans_en.q))
             -------------------------------------1------------------------------------    ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T47,T49
1	0	Covered	T2,T4,T7

 LINE       145
 SUB-EXPRESSION (reg2hw_i.filter_status.trans.q & reg2hw_i.adc_wakeup_ctl.trans_en.q)
                 ---------------1--------------   -----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T11,T47
1	0	Covered	T2,T7,T26
1	1	Covered	T7,T47,T49

---

Branch Coverage for Module : adc_ctrl_core

	Line No.	Total	Covered	Percent
Branches		35	35	100.00
TERNARY	83	3	3	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv' or '../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	83	(reg2hw_i.adc_en_ctl.oneshot_mode.q) ? 
-2-:	83	(reg2hw_i.adc_en_ctl.adc_enable.q) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T8,T9,T10
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][0].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][0].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][1].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][1].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T6,T10

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][2].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T6,T10

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][2].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T6,T10

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][3].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T6,T10,T11

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][3].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T6,T10,T11

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][4].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T6,T10,T13

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][4].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T6,T10,T13

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][5].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T13,T48

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][5].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T13,T48

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][6].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T6,T10,T11

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][6].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T6,T10,T11

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][7].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][7].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T5

---

Assert Coverage for Module : adc_ctrl_core

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	33	33	100.00	33	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	33	33	100.00	33	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
MaxFilters_A	33589078	33272711	0	0
gen_filter_match[0].MatchCheck00_A	33589078	11231639	0	0
gen_filter_match[0].MatchCheck01_A	33589078	1972008	0	0
gen_filter_match[0].MatchCheck10_A	33589078	3063322	0	0
gen_filter_match[0].MatchCheck11_A	33589078	17005742	0	0
gen_filter_match[1].MatchCheck00_A	33589078	10730464	0	0
gen_filter_match[1].MatchCheck01_A	33589078	1291746	0	0
gen_filter_match[1].MatchCheck10_A	33589078	1498890	0	0
gen_filter_match[1].MatchCheck11_A	33589078	19751611	0	0
gen_filter_match[2].MatchCheck00_A	33589078	11631530	0	0
gen_filter_match[2].MatchCheck01_A	33589078	842263	0	0
gen_filter_match[2].MatchCheck10_A	33589078	639280	0	0
gen_filter_match[2].MatchCheck11_A	33589078	20159638	0	0
gen_filter_match[3].MatchCheck00_A	33589078	12494348	0	0
gen_filter_match[3].MatchCheck01_A	33589078	280369	0	0
gen_filter_match[3].MatchCheck10_A	33589078	306541	0	0
gen_filter_match[3].MatchCheck11_A	33589078	20191453	0	0
gen_filter_match[4].MatchCheck00_A	33589078	12522086	0	0
gen_filter_match[4].MatchCheck01_A	33589078	88793	0	0
gen_filter_match[4].MatchCheck10_A	33589078	102576	0	0
gen_filter_match[4].MatchCheck11_A	33589078	20559256	0	0
gen_filter_match[5].MatchCheck00_A	33589078	13682955	0	0
gen_filter_match[5].MatchCheck01_A	33589078	15	0	0
gen_filter_match[5].MatchCheck10_A	33589078	85	0	0
gen_filter_match[5].MatchCheck11_A	33589078	19589656	0	0
gen_filter_match[6].MatchCheck00_A	33589078	12781281	0	0
gen_filter_match[6].MatchCheck01_A	33589078	10	0	0
gen_filter_match[6].MatchCheck10_A	33589078	34142	0	0
gen_filter_match[6].MatchCheck11_A	33589078	20457278	0	0
gen_filter_match[7].MatchCheck00_A	33589078	12636783	0	0
gen_filter_match[7].MatchCheck01_A	33589078	379516	0	0
gen_filter_match[7].MatchCheck10_A	33589078	134986	0	0
gen_filter_match[7].MatchCheck11_A	33589078	20121426	0	0

MaxFilters_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33589078	33272711	0	0
T1	33101	33020	0	0
T2	77438	77343	0	0
T3	5405	5320	0	0
T4	32607	32512	0	0
T5	33249	33166	0	0
T6	98992	98905	0	0
T7	77892	77823	0	0
T8	19217	16316	0	0
T9	19972	17526	0	0
T14	90	8	0	0

gen_filter_match[0].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33589078	11231639	0	0
T1	33101	3	0	0
T2	77438	3	0	0
T3	5405	5320	0	0
T4	32607	3	0	0
T5	33249	3	0	0
T6	98992	64847	0	0
T7	77892	3	0	0
T8	19217	16247	0	0
T9	19972	17243	0	0
T14	90	8	0	0

gen_filter_match[0].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33589078	1972008	0	0
T4	32607	32509	0	0
T5	33249	0	0	0
T6	98992	0	0	0
T7	77892	0	0	0
T8	19217	0	0	0
T9	19972	0	0	0
T10	82435	0	0	0
T11	13514	0	0	0
T13	0	6555	0	0
T14	90	0	0	0
T30	0	44502	0	0
T39	0	33956	0	0
T40	0	32094	0	0
T41	0	17541	0	0
T45	1221	0	0	0
T119	0	33389	0	0
T146	0	33208	0	0
T147	0	32608	0	0
T148	0	64955	0	0

gen_filter_match[0].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33589078	3063322	0	0
T15	13011	0	0	0
T16	0	33627	0	0
T18	0	1693	0	0
T25	67665	0	0	0
T34	36988	0	0	0
T35	0	32570	0	0
T38	123424	0	0	0
T39	100550	0	0	0
T48	97639	32185	0	0
T49	35157	0	0	0
T50	64608	0	0	0
T51	34518	0	0	0
T53	0	2	0	0
T119	65873	0	0	0
T149	0	65356	0	0
T150	0	32056	0	0
T151	0	1	0	0
T152	0	38958	0	0
T153	0	3	0	0

gen_filter_match[0].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33589078	17005742	0	0
T1	33101	33017	0	0
T2	77438	77340	0	0
T3	5405	0	0	0
T4	32607	0	0	0
T5	33249	33163	0	0
T6	98992	34058	0	0
T7	77892	77820	0	0
T8	19217	69	0	0
T9	19972	283	0	0
T11	0	4307	0	0
T13	0	52	0	0
T14	90	0	0	0
T47	0	32784	0	0

gen_filter_match[1].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33589078	10730464	0	0
T1	33101	3	0	0
T2	77438	3	0	0
T3	5405	5320	0	0
T4	32607	3	0	0
T5	33249	33166	0	0
T6	98992	66826	0	0
T7	77892	3	0	0
T8	19217	16316	0	0
T9	19972	17526	0	0
T14	90	8	0	0

gen_filter_match[1].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33589078	1291746	0	0
T15	13011	0	0	0
T17	0	21337	0	0
T25	67665	0	0	0
T34	36988	34318	0	0
T38	123424	38401	0	0
T39	100550	0	0	0
T44	0	12136	0	0
T48	97639	32586	0	0
T49	35157	0	0	0
T50	64608	0	0	0
T51	34518	0	0	0
T119	65873	0	0	0
T146	0	1	0	0
T152	0	1	0	0
T154	0	36338	0	0
T155	0	34460	0	0
T156	0	36833	0	0

gen_filter_match[1].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33589078	1498890	0	0
T15	13011	0	0	0
T16	0	3	0	0
T25	67665	0	0	0
T26	72937	0	0	0
T27	80981	0	0	0
T28	65567	0	0	0
T29	36373	0	0	0
T34	36988	0	0	0
T38	123424	0	0	0
T39	100550	0	0	0
T41	0	1	0	0
T53	0	1	0	0
T119	65873	32393	0	0
T151	0	1	0	0
T157	0	1	0	0
T158	0	32725	0	0
T159	0	32707	0	0
T160	0	1	0	0
T161	0	32951	0	0

gen_filter_match[1].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33589078	19751611	0	0
T1	33101	33017	0	0
T2	77438	77340	0	0
T3	5405	0	0	0
T4	32607	32509	0	0
T5	33249	0	0	0
T6	98992	32079	0	0
T7	77892	77820	0	0
T8	19217	0	0	0
T9	19972	0	0	0
T11	0	6701	0	0
T12	0	32720	0	0
T14	90	0	0	0
T47	0	74478	0	0
T50	0	64509	0	0
T51	0	34427	0	0

gen_filter_match[2].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33589078	11631530	0	0
T1	33101	3	0	0
T2	77438	3	0	0
T3	5405	5320	0	0
T4	32607	3	0	0
T5	33249	33166	0	0
T6	98992	32768	0	0
T7	77892	3	0	0
T8	19217	16316	0	0
T9	19972	17526	0	0
T14	90	8	0	0

gen_filter_match[2].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33589078	842263	0	0
T6	98992	34058	0	0
T7	77892	0	0	0
T8	19217	0	0	0
T9	19972	0	0	0
T10	82435	0	0	0
T11	13514	0	0	0
T12	32803	0	0	0
T13	8642	0	0	0
T14	90	0	0	0
T45	1221	0	0	0
T145	0	7278	0	0
T152	0	1	0	0
T162	0	32282	0	0
T163	0	33683	0	0
T164	0	33652	0	0
T165	0	33264	0	0
T166	0	32331	0	0
T167	0	32244	0	0
T168	0	34043	0	0

gen_filter_match[2].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33589078	639280	0	0
T10	82435	33354	0	0
T11	13514	0	0	0
T12	32803	0	0	0
T13	8642	0	0	0
T26	0	36154	0	0
T41	0	5	0	0
T43	0	78	0	0
T45	1221	0	0	0
T46	1200	0	0	0
T47	74574	41694	0	0
T48	97639	0	0	0
T49	35157	0	0	0
T50	64608	0	0	0
T146	0	1	0	0
T157	0	1	0	0
T160	0	1	0	0
T162	0	38436	0	0
T169	0	32670	0	0

gen_filter_match[2].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33589078	20159638	0	0
T1	33101	33017	0	0
T2	77438	77340	0	0
T3	5405	0	0	0
T4	32607	32509	0	0
T5	33249	0	0	0
T6	98992	32079	0	0
T7	77892	77820	0	0
T8	19217	0	0	0
T9	19972	0	0	0
T11	0	6701	0	0
T12	0	32720	0	0
T13	0	6555	0	0
T14	90	0	0	0
T47	0	32784	0	0
T49	0	35081	0	0

gen_filter_match[3].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33589078	12494348	0	0
T1	33101	3	0	0
T2	77438	3	0	0
T3	5405	5320	0	0
T4	32607	32512	0	0
T5	33249	3	0	0
T6	98992	34060	0	0
T7	77892	3	0	0
T8	19217	16316	0	0
T9	19972	17526	0	0
T14	90	8	0	0

gen_filter_match[3].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33589078	280369	0	0
T6	98992	1	0	0
T7	77892	0	0	0
T8	19217	0	0	0
T9	19972	0	0	0
T10	82435	33436	0	0
T11	13514	3997	0	0
T12	32803	0	0	0
T13	8642	0	0	0
T14	90	0	0	0
T39	0	1	0	0
T45	1221	0	0	0
T67	0	2359	0	0
T146	0	1	0	0
T152	0	1	0	0
T170	0	32444	0	0
T171	0	1	0	0
T172	0	38146	0	0

gen_filter_match[3].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33589078	306541	0	0
T6	98992	1	0	0
T7	77892	0	0	0
T8	19217	0	0	0
T9	19972	0	0	0
T10	82435	0	0	0
T11	13514	0	0	0
T12	32803	0	0	0
T13	8642	0	0	0
T14	90	0	0	0
T18	0	4	0	0
T41	0	1	0	0
T45	1221	0	0	0
T151	0	2	0	0
T152	0	1	0	0
T153	0	3	0	0
T157	0	1	0	0
T160	0	1	0	0
T173	0	33167	0	0
T174	0	2	0	0

gen_filter_match[3].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33589078	20191453	0	0
T1	33101	33017	0	0
T2	77438	77340	0	0
T3	5405	0	0	0
T4	32607	0	0	0
T5	33249	33163	0	0
T6	98992	64843	0	0
T7	77892	77820	0	0
T8	19217	0	0	0
T9	19972	0	0	0
T11	0	2394	0	0
T13	0	6555	0	0
T14	90	0	0	0
T47	0	41694	0	0
T48	0	64999	0	0
T49	0	35081	0	0

gen_filter_match[4].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33589078	12522086	0	0
T1	33101	33020	0	0
T2	77438	3	0	0
T3	5405	5320	0	0
T4	32607	3	0	0
T5	33249	3	0	0
T6	98992	32082	0	0
T7	77892	3	0	0
T8	19217	16316	0	0
T9	19972	17526	0	0
T14	90	8	0	0

gen_filter_match[4].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33589078	88793	0	0
T168	0	1	0	0
T171	107061	35433	0	0
T175	0	1	0	0
T176	0	53351	0	0
T177	0	1	0	0
T178	0	2	0	0
T179	0	1	0	0
T180	0	2	0	0
T181	0	1	0	0
T182	104	0	0	0
T183	32516	0	0	0
T184	32960	0	0	0
T185	903	0	0	0
T186	18504	0	0	0
T187	86427	0	0	0
T188	96569	0	0	0
T189	70939	0	0	0
T190	5903	0	0	0

gen_filter_match[4].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33589078	102576	0	0
T6	98992	2	0	0
T7	77892	0	0	0
T8	19217	0	0	0
T9	19972	0	0	0
T10	82435	0	0	0
T11	13514	0	0	0
T12	32803	0	0	0
T13	8642	0	0	0
T14	90	0	0	0
T16	0	5	0	0
T39	0	1	0	0
T45	1221	0	0	0
T53	0	2	0	0
T146	0	1	0	0
T157	0	1	0	0
T160	0	1	0	0
T191	0	1	0	0
T192	0	1	0	0
T193	0	1	0	0

gen_filter_match[4].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33589078	20559256	0	0
T2	77438	77340	0	0
T3	5405	0	0	0
T4	32607	32509	0	0
T5	33249	33163	0	0
T6	98992	66821	0	0
T7	77892	77820	0	0
T8	19217	0	0	0
T9	19972	0	0	0
T10	82435	66790	0	0
T11	0	8304	0	0
T12	0	32720	0	0
T14	90	0	0	0
T48	0	32814	0	0
T50	0	64509	0	0

gen_filter_match[5].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33589078	13682955	0	0
T1	33101	33020	0	0
T2	77438	3	0	0
T3	5405	5320	0	0
T4	32607	3	0	0
T5	33249	33166	0	0
T6	98992	32768	0	0
T7	77892	3	0	0
T8	19217	16316	0	0
T9	19972	17526	0	0
T14	90	8	0	0

gen_filter_match[5].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33589078	15	0	0
T15	13011	0	0	0
T25	67665	0	0	0
T26	72937	0	0	0
T27	80981	0	0	0
T28	65567	0	0	0
T29	36373	0	0	0
T30	77325	0	0	0
T31	77664	0	0	0
T32	32891	0	0	0
T39	100550	1	0	0
T93	0	1	0	0
T105	0	1	0	0
T152	0	2	0	0
T168	0	1	0	0
T175	0	1	0	0
T193	0	1	0	0
T194	0	1	0	0
T195	0	3	0	0
T196	0	2	0	0

gen_filter_match[5].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33589078	85	0	0
T15	13011	0	0	0
T18	0	3	0	0
T25	67665	0	0	0
T26	72937	0	0	0
T27	80981	0	0	0
T28	65567	0	0	0
T29	36373	0	0	0
T30	77325	0	0	0
T31	77664	0	0	0
T32	32891	0	0	0
T39	100550	1	0	0
T41	0	2	0	0
T146	0	1	0	0
T152	0	2	0	0
T157	0	1	0	0
T160	0	1	0	0
T191	0	1	0	0
T192	0	1	0	0
T193	0	1	0	0

gen_filter_match[5].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33589078	19589656	0	0
T2	77438	77340	0	0
T3	5405	0	0	0
T4	32607	32509	0	0
T5	33249	0	0	0
T6	98992	66137	0	0
T7	77892	77820	0	0
T8	19217	0	0	0
T9	19972	0	0	0
T10	82435	33436	0	0
T11	0	6701	0	0
T13	0	6555	0	0
T14	90	0	0	0
T47	0	74478	0	0
T48	0	65400	0	0
T49	0	35081	0	0

gen_filter_match[6].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33589078	12781281	0	0
T1	33101	3	0	0
T2	77438	3	0	0
T3	5405	5320	0	0
T4	32607	3	0	0
T5	33249	33166	0	0
T6	98992	64847	0	0
T7	77892	3	0	0
T8	19217	16316	0	0
T9	19972	17526	0	0
T14	90	8	0	0

gen_filter_match[6].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33589078	10	0	0
T15	13011	0	0	0
T25	67665	0	0	0
T26	72937	0	0	0
T27	80981	0	0	0
T28	65567	0	0	0
T29	36373	0	0	0
T34	36988	0	0	0
T38	123424	0	0	0
T39	100550	0	0	0
T119	65873	1	0	0
T146	0	1	0	0
T152	0	1	0	0
T168	0	1	0	0
T175	0	1	0	0
T178	0	1	0	0
T179	0	1	0	0
T193	0	1	0	0
T197	0	1	0	0
T198	0	1	0	0

gen_filter_match[6].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33589078	34142	0	0
T6	98992	1	0	0
T7	77892	0	0	0
T8	19217	0	0	0
T9	19972	0	0	0
T10	82435	0	0	0
T11	13514	0	0	0
T12	32803	0	0	0
T13	8642	0	0	0
T14	90	0	0	0
T16	0	5	0	0
T38	0	1	0	0
T39	0	1	0	0
T45	1221	0	0	0
T53	0	2	0	0
T119	0	1	0	0
T146	0	1	0	0
T157	0	1	0	0
T191	0	1	0	0
T192	0	1	0	0

gen_filter_match[6].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33589078	20457278	0	0
T1	33101	33017	0	0
T2	77438	77340	0	0
T3	5405	0	0	0
T4	32607	32509	0	0
T5	33249	0	0	0
T6	98992	34057	0	0
T7	77892	77820	0	0
T8	19217	0	0	0
T9	19972	0	0	0
T11	0	3997	0	0
T13	0	6555	0	0
T14	90	0	0	0
T47	0	74478	0	0
T48	0	65400	0	0
T50	0	64509	0	0

gen_filter_match[7].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33589078	12636783	0	0
T1	33101	3	0	0
T2	77438	3	0	0
T3	5405	5320	0	0
T4	32607	32512	0	0
T5	33249	3	0	0
T6	98992	66139	0	0
T7	77892	3	0	0
T8	19217	16316	0	0
T9	19972	17526	0	0
T14	90	8	0	0

gen_filter_match[7].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33589078	379516	0	0
T6	98992	1	0	0
T7	77892	0	0	0
T8	19217	0	0	0
T9	19972	0	0	0
T10	82435	0	0	0
T11	13514	0	0	0
T12	32803	0	0	0
T13	8642	0	0	0
T14	90	0	0	0
T41	0	32790	0	0
T45	1221	0	0	0
T152	0	1	0	0
T164	0	38066	0	0
T167	0	1	0	0
T193	0	1	0	0
T194	0	34936	0	0
T199	0	37737	0	0
T200	0	1	0	0
T201	0	36124	0	0

gen_filter_match[7].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33589078	134986	0	0
T6	98992	1	0	0
T7	77892	0	0	0
T8	19217	0	0	0
T9	19972	0	0	0
T10	82435	0	0	0
T11	13514	0	0	0
T12	32803	0	0	0
T13	8642	0	0	0
T14	90	0	0	0
T16	0	5	0	0
T38	0	2	0	0
T39	0	1	0	0
T45	1221	0	0	0
T119	0	1	0	0
T146	0	1	0	0
T157	0	1	0	0
T160	0	1	0	0
T191	0	1	0	0
T192	0	1	0	0

gen_filter_match[7].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33589078	20121426	0	0
T1	33101	33017	0	0
T2	77438	77340	0	0
T3	5405	0	0	0
T4	32607	0	0	0
T5	33249	33163	0	0
T6	98992	32764	0	0
T7	77892	77820	0	0
T8	19217	0	0	0
T9	19972	0	0	0
T12	0	32720	0	0
T14	90	0	0	0
T47	0	74478	0	0
T48	0	64999	0	0
T49	0	35081	0	0
T50	0	64509	0	0