Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	96.00						96.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	24	96.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	24	96.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	0	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	1975	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	1915	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	1734	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	1877	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	1868	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	1870	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	1950	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	1992	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	1886	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	1862	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	1975	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	1927	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	1915	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	1739	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	1900	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	1855	0	0
adc_en_ctl_rd_A	2147483647	1703	0	0
adc_fsm_rst_rd_A	2147483647	1531	0	0
adc_intr_ctl_rd_A	2147483647	2018	0	0
adc_lp_sample_ctl_rd_A	2147483647	1561	0	0
adc_pd_ctl_rd_A	2147483647	1755	0	0
adc_sample_ctl_rd_A	2147483647	1565	0	0
adc_wakeup_ctl_rd_A	2147483647	1655	0	0
intr_enable_rd_A	2147483647	2221	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1975	0	0
T15	306328	41	0	0
T16	0	20	0	0
T17	0	49	0	0
T18	0	14	0	0
T19	0	21	0	0
T20	0	12	0	0
T21	0	35	0	0
T22	0	51	0	0
T23	0	33	0	0
T24	0	9	0	0
T25	321424	0	0	0
T26	178701	0	0	0
T27	371840	0	0	0
T28	245890	0	0	0
T29	436488	0	0	0
T30	378903	0	0	0
T31	372786	0	0	0
T32	822305	0	0	0
T33	301042	0	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1915	0	0
T15	306328	57	0	0
T16	0	46	0	0
T17	0	49	0	0
T18	0	16	0	0
T19	0	35	0	0
T20	0	13	0	0
T21	0	26	0	0
T22	0	22	0	0
T23	0	21	0	0
T24	0	11	0	0
T25	321424	0	0	0
T26	178701	0	0	0
T27	371840	0	0	0
T28	245890	0	0	0
T29	436488	0	0	0
T30	378903	0	0	0
T31	372786	0	0	0
T32	822305	0	0	0
T33	301042	0	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1734	0	0
T15	306328	32	0	0
T16	0	23	0	0
T17	0	28	0	0
T18	0	25	0	0
T19	0	23	0	0
T20	0	33	0	0
T21	0	31	0	0
T22	0	37	0	0
T23	0	30	0	0
T24	0	10	0	0
T25	321424	0	0	0
T26	178701	0	0	0
T27	371840	0	0	0
T28	245890	0	0	0
T29	436488	0	0	0
T30	378903	0	0	0
T31	372786	0	0	0
T32	822305	0	0	0
T33	301042	0	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1877	0	0
T15	306328	21	0	0
T16	0	46	0	0
T17	0	31	0	0
T18	0	28	0	0
T19	0	28	0	0
T20	0	26	0	0
T21	0	27	0	0
T22	0	49	0	0
T23	0	38	0	0
T24	0	17	0	0
T25	321424	0	0	0
T26	178701	0	0	0
T27	371840	0	0	0
T28	245890	0	0	0
T29	436488	0	0	0
T30	378903	0	0	0
T31	372786	0	0	0
T32	822305	0	0	0
T33	301042	0	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1868	0	0
T15	306328	40	0	0
T16	0	50	0	0
T17	0	42	0	0
T18	0	22	0	0
T19	0	19	0	0
T20	0	21	0	0
T21	0	27	0	0
T22	0	38	0	0
T23	0	32	0	0
T24	0	15	0	0
T25	321424	0	0	0
T26	178701	0	0	0
T27	371840	0	0	0
T28	245890	0	0	0
T29	436488	0	0	0
T30	378903	0	0	0
T31	372786	0	0	0
T32	822305	0	0	0
T33	301042	0	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1870	0	0
T15	306328	30	0	0
T16	0	29	0	0
T17	0	45	0	0
T18	0	29	0	0
T19	0	19	0	0
T20	0	27	0	0
T21	0	16	0	0
T22	0	33	0	0
T23	0	28	0	0
T24	0	9	0	0
T25	321424	0	0	0
T26	178701	0	0	0
T27	371840	0	0	0
T28	245890	0	0	0
T29	436488	0	0	0
T30	378903	0	0	0
T31	372786	0	0	0
T32	822305	0	0	0
T33	301042	0	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1950	0	0
T15	306328	41	0	0
T16	0	28	0	0
T17	0	41	0	0
T18	0	15	0	0
T19	0	30	0	0
T20	0	28	0	0
T21	0	46	0	0
T22	0	36	0	0
T23	0	30	0	0
T24	0	26	0	0
T25	321424	0	0	0
T26	178701	0	0	0
T27	371840	0	0	0
T28	245890	0	0	0
T29	436488	0	0	0
T30	378903	0	0	0
T31	372786	0	0	0
T32	822305	0	0	0
T33	301042	0	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1992	0	0
T15	306328	22	0	0
T16	0	30	0	0
T17	0	56	0	0
T18	0	24	0	0
T19	0	17	0	0
T20	0	15	0	0
T21	0	29	0	0
T22	0	52	0	0
T23	0	43	0	0
T24	0	22	0	0
T25	321424	0	0	0
T26	178701	0	0	0
T27	371840	0	0	0
T28	245890	0	0	0
T29	436488	0	0	0
T30	378903	0	0	0
T31	372786	0	0	0
T32	822305	0	0	0
T33	301042	0	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1886	0	0
T15	306328	47	0	0
T16	0	40	0	0
T17	0	24	0	0
T18	0	25	0	0
T19	0	28	0	0
T20	0	15	0	0
T21	0	30	0	0
T22	0	32	0	0
T23	0	24	0	0
T24	0	25	0	0
T25	321424	0	0	0
T26	178701	0	0	0
T27	371840	0	0	0
T28	245890	0	0	0
T29	436488	0	0	0
T30	378903	0	0	0
T31	372786	0	0	0
T32	822305	0	0	0
T33	301042	0	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1862	0	0
T15	306328	43	0	0
T16	0	42	0	0
T17	0	22	0	0
T18	0	30	0	0
T19	0	9	0	0
T20	0	17	0	0
T21	0	35	0	0
T22	0	49	0	0
T23	0	51	0	0
T24	0	24	0	0
T25	321424	0	0	0
T26	178701	0	0	0
T27	371840	0	0	0
T28	245890	0	0	0
T29	436488	0	0	0
T30	378903	0	0	0
T31	372786	0	0	0
T32	822305	0	0	0
T33	301042	0	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1975	0	0
T15	306328	37	0	0
T16	0	35	0	0
T17	0	41	0	0
T18	0	31	0	0
T19	0	26	0	0
T20	0	14	0	0
T21	0	39	0	0
T22	0	36	0	0
T23	0	26	0	0
T24	0	19	0	0
T25	321424	0	0	0
T26	178701	0	0	0
T27	371840	0	0	0
T28	245890	0	0	0
T29	436488	0	0	0
T30	378903	0	0	0
T31	372786	0	0	0
T32	822305	0	0	0
T33	301042	0	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1927	0	0
T15	306328	42	0	0
T16	0	46	0	0
T17	0	24	0	0
T18	0	23	0	0
T19	0	14	0	0
T20	0	34	0	0
T21	0	25	0	0
T22	0	45	0	0
T23	0	35	0	0
T24	0	9	0	0
T25	321424	0	0	0
T26	178701	0	0	0
T27	371840	0	0	0
T28	245890	0	0	0
T29	436488	0	0	0
T30	378903	0	0	0
T31	372786	0	0	0
T32	822305	0	0	0
T33	301042	0	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1915	0	0
T15	306328	44	0	0
T16	0	36	0	0
T17	0	32	0	0
T18	0	25	0	0
T19	0	27	0	0
T20	0	24	0	0
T21	0	31	0	0
T22	0	47	0	0
T23	0	30	0	0
T24	0	27	0	0
T25	321424	0	0	0
T26	178701	0	0	0
T27	371840	0	0	0
T28	245890	0	0	0
T29	436488	0	0	0
T30	378903	0	0	0
T31	372786	0	0	0
T32	822305	0	0	0
T33	301042	0	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1739	0	0
T15	306328	15	0	0
T16	0	38	0	0
T17	0	47	0	0
T18	0	17	0	0
T19	0	9	0	0
T20	0	24	0	0
T21	0	34	0	0
T22	0	48	0	0
T23	0	51	0	0
T24	0	14	0	0
T25	321424	0	0	0
T26	178701	0	0	0
T27	371840	0	0	0
T28	245890	0	0	0
T29	436488	0	0	0
T30	378903	0	0	0
T31	372786	0	0	0
T32	822305	0	0	0
T33	301042	0	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1900	0	0
T15	306328	43	0	0
T16	0	33	0	0
T17	0	46	0	0
T18	0	18	0	0
T19	0	13	0	0
T20	0	8	0	0
T21	0	31	0	0
T22	0	38	0	0
T23	0	25	0	0
T24	0	20	0	0
T25	321424	0	0	0
T26	178701	0	0	0
T27	371840	0	0	0
T28	245890	0	0	0
T29	436488	0	0	0
T30	378903	0	0	0
T31	372786	0	0	0
T32	822305	0	0	0
T33	301042	0	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1855	0	0
T15	306328	22	0	0
T16	0	41	0	0
T17	0	22	0	0
T18	0	29	0	0
T19	0	24	0	0
T20	0	23	0	0
T21	0	31	0	0
T22	0	28	0	0
T23	0	48	0	0
T24	0	16	0	0
T25	321424	0	0	0
T26	178701	0	0	0
T27	371840	0	0	0
T28	245890	0	0	0
T29	436488	0	0	0
T30	378903	0	0	0
T31	372786	0	0	0
T32	822305	0	0	0
T33	301042	0	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1703	0	0
T15	306328	52	0	0
T16	0	48	0	0
T17	0	35	0	0
T18	0	8	0	0
T19	0	13	0	0
T20	0	22	0	0
T21	0	30	0	0
T22	0	51	0	0
T23	0	35	0	0
T24	0	15	0	0
T25	321424	0	0	0
T26	178701	0	0	0
T27	371840	0	0	0
T28	245890	0	0	0
T29	436488	0	0	0
T30	378903	0	0	0
T31	372786	0	0	0
T32	822305	0	0	0
T33	301042	0	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1531	0	0
T15	306328	32	0	0
T16	0	40	0	0
T17	0	43	0	0
T18	0	13	0	0
T19	0	29	0	0
T20	0	21	0	0
T21	0	28	0	0
T22	0	51	0	0
T23	0	27	0	0
T24	0	34	0	0
T25	321424	0	0	0
T26	178701	0	0	0
T27	371840	0	0	0
T28	245890	0	0	0
T29	436488	0	0	0
T30	378903	0	0	0
T31	372786	0	0	0
T32	822305	0	0	0
T33	301042	0	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2018	0	0
T15	306328	35	0	0
T16	0	43	0	0
T17	0	48	0	0
T18	0	13	0	0
T19	0	29	0	0
T20	0	27	0	0
T21	0	23	0	0
T22	0	26	0	0
T23	0	41	0	0
T24	0	17	0	0
T25	321424	0	0	0
T26	178701	0	0	0
T27	371840	0	0	0
T28	245890	0	0	0
T29	436488	0	0	0
T30	378903	0	0	0
T31	372786	0	0	0
T32	822305	0	0	0
T33	301042	0	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1561	0	0
T15	306328	17	0	0
T16	0	39	0	0
T17	0	47	0	0
T18	0	18	0	0
T19	0	10	0	0
T20	0	12	0	0
T21	0	44	0	0
T22	0	25	0	0
T23	0	33	0	0
T24	0	15	0	0
T25	321424	0	0	0
T26	178701	0	0	0
T27	371840	0	0	0
T28	245890	0	0	0
T29	436488	0	0	0
T30	378903	0	0	0
T31	372786	0	0	0
T32	822305	0	0	0
T33	301042	0	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1755	0	0
T15	306328	42	0	0
T16	0	43	0	0
T17	0	21	0	0
T18	0	23	0	0
T19	0	22	0	0
T20	0	9	0	0
T21	0	35	0	0
T22	0	46	0	0
T23	0	38	0	0
T24	0	9	0	0
T25	321424	0	0	0
T26	178701	0	0	0
T27	371840	0	0	0
T28	245890	0	0	0
T29	436488	0	0	0
T30	378903	0	0	0
T31	372786	0	0	0
T32	822305	0	0	0
T33	301042	0	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1565	0	0
T15	306328	37	0	0
T16	0	42	0	0
T17	0	44	0	0
T18	0	7	0	0
T19	0	4	0	0
T20	0	20	0	0
T21	0	44	0	0
T22	0	36	0	0
T23	0	39	0	0
T24	0	17	0	0
T25	321424	0	0	0
T26	178701	0	0	0
T27	371840	0	0	0
T28	245890	0	0	0
T29	436488	0	0	0
T30	378903	0	0	0
T31	372786	0	0	0
T32	822305	0	0	0
T33	301042	0	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1655	0	0
T15	306328	39	0	0
T16	0	29	0	0
T17	0	37	0	0
T18	0	16	0	0
T19	0	16	0	0
T20	0	8	0	0
T21	0	37	0	0
T22	0	46	0	0
T23	0	43	0	0
T24	0	25	0	0
T25	321424	0	0	0
T26	178701	0	0	0
T27	371840	0	0	0
T28	245890	0	0	0
T29	436488	0	0	0
T30	378903	0	0	0
T31	372786	0	0	0
T32	822305	0	0	0
T33	301042	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2221	0	0
T15	306328	55	0	0
T16	0	40	0	0
T17	0	54	0	0
T18	0	26	0	0
T19	0	39	0	0
T20	0	20	0	0
T25	321424	0	0	0
T26	178701	0	0	0
T27	371840	0	0	0
T28	245890	0	0	0
T29	436488	0	0	0
T30	378903	0	0	0
T34	924716	33	0	0
T35	0	10	0	0
T36	0	16	0	0
T37	0	12	0	0
T38	148109	0	0	0
T39	120661	0	0	0