Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1171122	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1144457

1

T1

472

T2

4059

T3

6415

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2024540	1			T2	7837		T3	12183		T4	8040
values[0x0]	145463	1			T1	611		T2	272		T3	403
values[0x1]	145576	1			T1	577		T2	258		T3	425

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	938325	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1377254

1

T1

574

T2

4945

T3

7732

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	8417	1			T2	13		T3	41		T4	41
valid_sources[0x01]	8169	1			T2	11		T3	11		T4	39
valid_sources[0x02]	7709	1			T2	25		T3	57		T4	25
valid_sources[0x03]	7920	1			T2	16		T3	77		T4	38
valid_sources[0x04]	11274	1			T2	17		T4	35		T5	3
valid_sources[0x05]	7343	1			T2	15		T4	44		T5	6
valid_sources[0x06]	8964	1			T2	25		T3	92		T4	27
valid_sources[0x07]	7314	1			T2	18		T3	324		T4	44
valid_sources[0x08]	7037	1			T2	16		T3	7		T4	16
valid_sources[0x09]	7256	1			T2	22		T3	39		T4	31
valid_sources[0x0a]	8190	1			T2	11		T3	16		T4	37
valid_sources[0x0b]	7294	1			T2	10		T3	12		T4	55
valid_sources[0x0c]	11083	1			T2	16		T3	16		T4	32
valid_sources[0x0d]	7141	1			T2	14		T3	36		T4	46
valid_sources[0x0e]	7767	1			T2	19		T3	49		T4	43
valid_sources[0x0f]	19970	1			T2	14		T3	99		T4	10
valid_sources[0x10]	7140	1			T2	17		T3	33		T4	45
valid_sources[0x11]	6840	1			T2	6		T4	30		T6	13
valid_sources[0x12]	7146	1			T2	16		T3	1		T4	28
valid_sources[0x13]	11061	1			T2	19		T3	53		T4	47
valid_sources[0x14]	7921	1			T2	15		T3	14		T4	42
valid_sources[0x15]	8333	1			T2	12		T3	137		T4	40
valid_sources[0x16]	12019	1			T2	16		T3	34		T4	28
valid_sources[0x17]	9924	1			T2	10		T3	63		T4	22
valid_sources[0x18]	9984	1			T2	17		T3	93		T4	29
valid_sources[0x19]	7085	1			T2	11		T3	62		T4	34
valid_sources[0x1a]	14238	1			T2	21		T3	4		T4	38
valid_sources[0x1b]	11678	1			T2	17		T4	23		T5	3
valid_sources[0x1c]	6723	1			T2	16		T3	2		T4	27
valid_sources[0x1d]	6941	1			T2	13		T3	12		T4	17
valid_sources[0x1e]	7094	1			T2	21		T3	29		T4	38
valid_sources[0x1f]	7058	1			T2	21		T4	43		T5	9
valid_sources[0x20]	10712	1			T2	17		T3	85		T4	33
valid_sources[0x21]	11207	1			T2	15		T3	28		T4	30
valid_sources[0x22]	7659	1			T2	12		T3	15		T4	29
valid_sources[0x23]	20661	1			T2	16		T3	51		T4	23
valid_sources[0x24]	11209	1			T2	16		T3	13		T4	41
valid_sources[0x25]	6908	1			T2	18		T3	5		T4	37
valid_sources[0x26]	12509	1			T2	22		T3	45		T4	28
valid_sources[0x27]	9137	1			T2	13		T3	25		T4	46
valid_sources[0x28]	7670	1			T2	16		T3	23		T4	21
valid_sources[0x29]	7167	1			T2	20		T3	41		T4	40
valid_sources[0x2a]	9682	1			T2	15		T3	22		T4	38
valid_sources[0x2b]	7263	1			T2	11		T3	94		T4	42
valid_sources[0x2c]	9365	1			T2	21		T3	42		T4	41
valid_sources[0x2d]	9024	1			T2	24		T3	32		T4	32
valid_sources[0x2e]	7149	1			T2	19		T3	141		T4	35
valid_sources[0x2f]	9794	1			T2	13		T3	135		T4	58
valid_sources[0x30]	7211	1			T2	28		T3	12		T4	38
valid_sources[0x31]	7150	1			T2	19		T4	31		T5	10
valid_sources[0x32]	7010	1			T2	20		T3	152		T4	31
valid_sources[0x33]	8808	1			T2	19		T4	42		T5	1
valid_sources[0x34]	16695	1			T2	18		T3	286		T4	33
valid_sources[0x35]	7294	1			T2	20		T3	39		T4	22
valid_sources[0x36]	7153	1			T2	17		T3	53		T4	26
valid_sources[0x37]	7304	1			T2	20		T3	26		T4	20
valid_sources[0x38]	11299	1			T2	14		T3	42		T4	31
valid_sources[0x39]	9234	1			T2	12		T3	32		T4	31
valid_sources[0x3a]	7344	1			T2	13		T3	23		T4	32
valid_sources[0x3b]	6969	1			T2	26		T4	41		T5	3
valid_sources[0x3c]	7399	1			T2	10		T4	27		T5	5
valid_sources[0x3d]	8065	1			T2	13		T3	17		T4	16
valid_sources[0x3e]	6838	1			T2	9		T3	36		T4	36
valid_sources[0x3f]	6993	1			T2	17		T3	79		T4	16
valid_sources[0x40]	6784	1			T2	11		T3	72		T4	17
valid_sources[0x41]	7939	1			T2	17		T3	50		T4	19
valid_sources[0x42]	7061	1			T2	14		T3	35		T4	49
valid_sources[0x43]	7033	1			T2	13		T3	110		T4	13
valid_sources[0x44]	6982	1			T2	19		T4	41		T5	4
valid_sources[0x45]	7531	1			T2	21		T3	7		T4	60
valid_sources[0x46]	14959	1			T2	13		T3	95		T4	27
valid_sources[0x47]	7202	1			T2	7		T3	11		T4	30
valid_sources[0x48]	7430	1			T2	18		T3	134		T4	25
valid_sources[0x49]	11514	1			T2	15		T3	15		T4	21
valid_sources[0x4a]	9361	1			T2	13		T3	29		T4	26
valid_sources[0x4b]	11313	1			T2	11		T3	107		T4	32
valid_sources[0x4c]	7135	1			T2	18		T3	27		T4	36
valid_sources[0x4d]	7427	1			T2	16		T3	45		T4	27
valid_sources[0x4e]	20268	1			T2	17		T3	19		T4	30
valid_sources[0x4f]	7387	1			T2	15		T3	35		T4	15
valid_sources[0x50]	7809	1			T2	15		T3	35		T4	58
valid_sources[0x51]	7115	1			T2	13		T3	17		T4	27
valid_sources[0x52]	11322	1			T2	16		T3	22		T4	36
valid_sources[0x53]	12136	1			T2	18		T3	35		T4	15
valid_sources[0x54]	11304	1			T2	14		T3	16		T4	41
valid_sources[0x55]	11468	1			T2	23		T3	63		T4	31
valid_sources[0x56]	9325	1			T2	12		T3	60		T4	26
valid_sources[0x57]	10005	1			T2	14		T3	85		T4	28
valid_sources[0x58]	12059	1			T2	13		T3	35		T4	37
valid_sources[0x59]	7355	1			T2	14		T3	67		T4	11
valid_sources[0x5a]	7174	1			T2	15		T3	12		T4	21
valid_sources[0x5b]	7222	1			T2	19		T3	52		T4	34
valid_sources[0x5c]	10067	1			T2	10		T3	22		T4	35
valid_sources[0x5d]	6720	1			T2	14		T3	8		T4	47
valid_sources[0x5e]	9737	1			T2	15		T3	113		T4	29
valid_sources[0x5f]	7263	1			T2	18		T3	16		T4	30
valid_sources[0x60]	7496	1			T2	19		T3	53		T4	21
valid_sources[0x61]	11354	1			T2	4296		T3	7		T4	33
valid_sources[0x62]	7214	1			T2	19		T3	39		T4	47
valid_sources[0x63]	9108	1			T2	13		T3	65		T4	20
valid_sources[0x64]	11326	1			T2	14		T3	99		T4	47
valid_sources[0x65]	11723	1			T2	12		T3	7		T4	24
valid_sources[0x66]	7928	1			T2	12		T3	48		T4	39
valid_sources[0x67]	20226	1			T2	15		T3	51		T4	23
valid_sources[0x68]	11222	1			T2	17		T3	18		T4	36
valid_sources[0x69]	7245	1			T2	15		T3	52		T4	31
valid_sources[0x6a]	8827	1			T2	11		T3	14		T4	29
valid_sources[0x6b]	10984	1			T2	11		T3	106		T4	22
valid_sources[0x6c]	9852	1			T2	16		T3	48		T4	25
valid_sources[0x6d]	6894	1			T2	13		T3	19		T4	35
valid_sources[0x6e]	13630	1			T2	12		T3	97		T4	29
valid_sources[0x6f]	7502	1			T2	10		T3	127		T4	41
valid_sources[0x70]	7527	1			T2	13		T3	21		T4	26
valid_sources[0x71]	7170	1			T2	14		T3	65		T4	44
valid_sources[0x72]	9697	1			T2	18		T3	4		T4	28
valid_sources[0x73]	10797	1			T2	25		T3	15		T4	23
valid_sources[0x74]	7213	1			T2	17		T3	7		T4	30
valid_sources[0x75]	7345	1			T2	16		T3	9		T4	52
valid_sources[0x76]	11114	1			T2	12		T3	62		T4	31
valid_sources[0x77]	7249	1			T2	9		T3	103		T4	44
valid_sources[0x78]	8413	1			T2	14		T3	90		T4	29
valid_sources[0x79]	7161	1			T2	17		T3	141		T4	32
valid_sources[0x7a]	7870	1			T2	17		T3	18		T4	27
valid_sources[0x7b]	7641	1			T2	22		T3	104		T4	49
valid_sources[0x7c]	7335	1			T2	18		T3	20		T4	47
valid_sources[0x7d]	8230	1			T2	14		T3	11		T4	23
valid_sources[0x7e]	8000	1			T2	18		T3	3		T4	30
valid_sources[0x7f]	7074	1			T2	17		T3	50		T4	22
valid_sources[0x80]	6877	1			T2	19		T3	40		T4	43

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1008220

1

T2

3863

T3

6108

T4

3938

values[0x0]

all_enables

biggest_size

79363

1

T1

283

T2

124

T3

190

values[0x1]

all_enables

biggest_size

56874

1

T1

189

T2

72

T3

117