Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
93.33	93.33	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	93.33	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.33	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	3	42	93.33

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	2	14	87.50	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2240	1			T1	9		T8	11		T43	10
auto[PWRUP]	85	1			T48	1		T49	2		T50	1
auto[ONEST_0]	72	1			T1	1		T27	3		T49	2
auto[ONEST_021]	22	1			T35	1		T27	1		T180	2
auto[ONEST_1]	88	1			T1	3		T8	1		T35	2
auto[ONEST_DONE]	2	1			T52	1		T322	1		-	-
auto[LP_0]	112	1			T1	3		T35	1		T12	1
auto[LP_021]	22	1			T50	1		T174	1		T173	1
auto[LP_1]	169	1			T1	2		T35	3		T34	1
auto[LP_EVAL]	72	1			T35	1		T34	1		T12	1
auto[LP_SLP]	530	1			T1	8		T35	6		T34	3
auto[LP_PWRUP]	25	1			T1	1		T12	1		T49	1
auto[NP_0]	229	1			T8	1		T35	3		T34	1
auto[NP_021]	45	1			T8	1		T12	1		T49	1
auto[NP_1]	237	1			T8	3		T35	1		T34	2
auto[NP_EVAL]	30	1			T12	1		T50	1		T173	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

17

1

T27

1

T174

1

T52

2

min

1919

1

T1

9

T8

17

T43

10

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1933	1			T1	9		T8	17		T43	10
pow[0x1]	9	1			T36	1		T180	1		T323	2
pow[0x2]	18	1			T35	1		T48	1		T50	1
pow[0x3]	36	1			T34	1		T12	1		T27	1
pow[0x4]	72	1			T1	1		T35	2		T27	1
pow[0x5]	113	1			T1	1		T12	1		T27	2
pow[0x6]	254	1			T1	2		T35	3		T34	1
pow[0x7]	504	1			T1	9		T35	5		T34	2

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

189

1

T34

1

T27

2

T48

2

min

1313

1

T8

12

T43

10

T35

8

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	2	14	87.50

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x5]	0	1	1
pow[0x6]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1319	1			T8	12		T43	10		T35	8
pow[0x1]	13	1			T12	5		T37	3		T38	1
pow[0x2]	17	1			T13	1		T215	1		T160	2
pow[0x3]	42	1			T12	1		T36	1		T37	1
pow[0x4]	75	1			T8	5		T34	1		T36	1
pow[0x7]	1	1			T324	1		-	-		-	-
pow[0x8]	6	1			T51	1		T294	1		T17	1
pow[0x9]	6	1			T51	1		T178	2		T325	1
pow[0xa]	13	1			T180	1		T326	1		T290	1
pow[0xb]	35	1			T35	1		T34	1		T12	4
pow[0xc]	70	1			T1	1		T174	1		T173	1
pow[0xd]	145	1			T1	2		T35	3		T34	1
pow[0xe]	294	1			T1	6		T35	3		T34	3
pow[0xf]	593	1			T1	7		T35	8		T34	1