Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	96.00						96.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	24	96.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	24	96.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	0	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	1760	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	2027	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	2027	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	1888	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	2053	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	2036	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	2044	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	1845	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	1964	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	1873	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	2117	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	1870	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	1853	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	1943	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	1930	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	2055	0	0
adc_en_ctl_rd_A	2147483647	1454	0	0
adc_fsm_rst_rd_A	2147483647	1341	0	0
adc_intr_ctl_rd_A	2147483647	1751	0	0
adc_lp_sample_ctl_rd_A	2147483647	1335	0	0
adc_pd_ctl_rd_A	2147483647	1654	0	0
adc_sample_ctl_rd_A	2147483647	1308	0	0
adc_wakeup_ctl_rd_A	2147483647	1368	0	0
intr_enable_rd_A	2147483647	1803	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1760	0	0
T12	406890	31	0	0
T13	0	29	0	0
T14	0	12	0	0
T15	0	30	0	0
T16	0	20	0	0
T17	0	17	0	0
T18	0	19	0	0
T19	0	23	0	0
T20	0	24	0	0
T21	0	16	0	0
T22	824051	0	0	0
T23	30051	0	0	0
T24	336294	0	0	0
T25	83403	0	0	0
T26	330247	0	0	0
T27	976824	0	0	0
T28	305347	0	0	0
T29	119686	0	0	0
T30	838158	0	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2027	0	0
T12	406890	24	0	0
T13	0	44	0	0
T14	0	10	0	0
T15	0	35	0	0
T16	0	18	0	0
T17	0	16	0	0
T18	0	12	0	0
T19	0	39	0	0
T20	0	25	0	0
T21	0	22	0	0
T22	824051	0	0	0
T23	30051	0	0	0
T24	336294	0	0	0
T25	83403	0	0	0
T26	330247	0	0	0
T27	976824	0	0	0
T28	305347	0	0	0
T29	119686	0	0	0
T30	838158	0	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2027	0	0
T12	406890	21	0	0
T13	0	45	0	0
T14	0	16	0	0
T15	0	54	0	0
T16	0	12	0	0
T17	0	16	0	0
T18	0	15	0	0
T19	0	40	0	0
T20	0	29	0	0
T22	824051	0	0	0
T23	30051	0	0	0
T24	336294	0	0	0
T25	83403	0	0	0
T26	330247	0	0	0
T27	976824	0	0	0
T28	305347	0	0	0
T29	119686	0	0	0
T30	838158	0	0	0
T31	0	4	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1888	0	0
T12	406890	11	0	0
T13	0	46	0	0
T14	0	13	0	0
T15	0	27	0	0
T16	0	10	0	0
T17	0	26	0	0
T18	0	6	0	0
T19	0	35	0	0
T20	0	15	0	0
T22	824051	0	0	0
T23	30051	0	0	0
T24	336294	0	0	0
T25	83403	0	0	0
T26	330247	0	0	0
T27	976824	0	0	0
T28	305347	0	0	0
T29	119686	0	0	0
T30	838158	0	0	0
T31	0	2	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2053	0	0
T12	406890	33	0	0
T13	0	28	0	0
T14	0	17	0	0
T15	0	17	0	0
T16	0	30	0	0
T17	0	21	0	0
T18	0	41	0	0
T19	0	31	0	0
T20	0	21	0	0
T22	824051	0	0	0
T23	30051	0	0	0
T24	336294	0	0	0
T25	83403	0	0	0
T26	330247	0	0	0
T27	976824	0	0	0
T28	305347	0	0	0
T29	119686	0	0	0
T30	838158	0	0	0
T31	0	7	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2036	0	0
T12	406890	31	0	0
T13	0	20	0	0
T14	0	21	0	0
T15	0	33	0	0
T16	0	19	0	0
T17	0	23	0	0
T18	0	16	0	0
T19	0	47	0	0
T20	0	22	0	0
T22	824051	0	0	0
T23	30051	0	0	0
T24	336294	0	0	0
T25	83403	0	0	0
T26	330247	0	0	0
T27	976824	0	0	0
T28	305347	0	0	0
T29	119686	0	0	0
T30	838158	0	0	0
T31	0	5	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2044	0	0
T12	406890	17	0	0
T13	0	33	0	0
T14	0	22	0	0
T15	0	32	0	0
T16	0	18	0	0
T17	0	33	0	0
T18	0	11	0	0
T19	0	24	0	0
T20	0	22	0	0
T21	0	37	0	0
T22	824051	0	0	0
T23	30051	0	0	0
T24	336294	0	0	0
T25	83403	0	0	0
T26	330247	0	0	0
T27	976824	0	0	0
T28	305347	0	0	0
T29	119686	0	0	0
T30	838158	0	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1845	0	0
T12	406890	24	0	0
T13	0	33	0	0
T14	0	13	0	0
T15	0	34	0	0
T16	0	20	0	0
T17	0	27	0	0
T18	0	13	0	0
T19	0	38	0	0
T20	0	12	0	0
T22	824051	0	0	0
T23	30051	0	0	0
T24	336294	0	0	0
T25	83403	0	0	0
T26	330247	0	0	0
T27	976824	0	0	0
T28	305347	0	0	0
T29	119686	0	0	0
T30	838158	0	0	0
T31	0	1	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1964	0	0
T12	406890	22	0	0
T13	0	33	0	0
T14	0	7	0	0
T15	0	25	0	0
T16	0	17	0	0
T17	0	25	0	0
T18	0	15	0	0
T19	0	30	0	0
T20	0	13	0	0
T22	824051	0	0	0
T23	30051	0	0	0
T24	336294	0	0	0
T25	83403	0	0	0
T26	330247	0	0	0
T27	976824	0	0	0
T28	305347	0	0	0
T29	119686	0	0	0
T30	838158	0	0	0
T31	0	5	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1873	0	0
T12	406890	19	0	0
T13	0	31	0	0
T14	0	14	0	0
T15	0	22	0	0
T16	0	30	0	0
T17	0	30	0	0
T18	0	24	0	0
T19	0	33	0	0
T20	0	20	0	0
T21	0	42	0	0
T22	824051	0	0	0
T23	30051	0	0	0
T24	336294	0	0	0
T25	83403	0	0	0
T26	330247	0	0	0
T27	976824	0	0	0
T28	305347	0	0	0
T29	119686	0	0	0
T30	838158	0	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2117	0	0
T12	406890	12	0	0
T13	0	42	0	0
T14	0	2	0	0
T15	0	44	0	0
T16	0	30	0	0
T17	0	21	0	0
T18	0	34	0	0
T19	0	42	0	0
T20	0	12	0	0
T21	0	22	0	0
T22	824051	0	0	0
T23	30051	0	0	0
T24	336294	0	0	0
T25	83403	0	0	0
T26	330247	0	0	0
T27	976824	0	0	0
T28	305347	0	0	0
T29	119686	0	0	0
T30	838158	0	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1870	0	0
T12	406890	8	0	0
T13	0	54	0	0
T14	0	7	0	0
T15	0	43	0	0
T16	0	29	0	0
T17	0	30	0	0
T18	0	5	0	0
T19	0	32	0	0
T20	0	31	0	0
T22	824051	0	0	0
T23	30051	0	0	0
T24	336294	0	0	0
T25	83403	0	0	0
T26	330247	0	0	0
T27	976824	0	0	0
T28	305347	0	0	0
T29	119686	0	0	0
T30	838158	0	0	0
T31	0	6	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1853	0	0
T12	406890	21	0	0
T13	0	28	0	0
T14	0	17	0	0
T15	0	42	0	0
T16	0	17	0	0
T17	0	23	0	0
T18	0	29	0	0
T19	0	29	0	0
T20	0	17	0	0
T22	824051	0	0	0
T23	30051	0	0	0
T24	336294	0	0	0
T25	83403	0	0	0
T26	330247	0	0	0
T27	976824	0	0	0
T28	305347	0	0	0
T29	119686	0	0	0
T30	838158	0	0	0
T31	0	9	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1943	0	0
T12	406890	10	0	0
T13	0	21	0	0
T14	0	15	0	0
T15	0	25	0	0
T16	0	46	0	0
T17	0	22	0	0
T18	0	18	0	0
T19	0	38	0	0
T20	0	19	0	0
T21	0	25	0	0
T22	824051	0	0	0
T23	30051	0	0	0
T24	336294	0	0	0
T25	83403	0	0	0
T26	330247	0	0	0
T27	976824	0	0	0
T28	305347	0	0	0
T29	119686	0	0	0
T30	838158	0	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1930	0	0
T12	406890	21	0	0
T13	0	29	0	0
T14	0	20	0	0
T15	0	26	0	0
T16	0	29	0	0
T17	0	25	0	0
T18	0	42	0	0
T19	0	32	0	0
T20	0	35	0	0
T21	0	22	0	0
T22	824051	0	0	0
T23	30051	0	0	0
T24	336294	0	0	0
T25	83403	0	0	0
T26	330247	0	0	0
T27	976824	0	0	0
T28	305347	0	0	0
T29	119686	0	0	0
T30	838158	0	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2055	0	0
T12	406890	16	0	0
T13	0	40	0	0
T14	0	2	0	0
T15	0	29	0	0
T16	0	26	0	0
T17	0	12	0	0
T18	0	30	0	0
T19	0	27	0	0
T20	0	24	0	0
T21	0	6	0	0
T22	824051	0	0	0
T23	30051	0	0	0
T24	336294	0	0	0
T25	83403	0	0	0
T26	330247	0	0	0
T27	976824	0	0	0
T28	305347	0	0	0
T29	119686	0	0	0
T30	838158	0	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1454	0	0
T12	406890	12	0	0
T13	0	42	0	0
T14	0	16	0	0
T15	0	22	0	0
T16	0	28	0	0
T17	0	37	0	0
T18	0	15	0	0
T19	0	24	0	0
T20	0	22	0	0
T21	0	22	0	0
T22	824051	0	0	0
T23	30051	0	0	0
T24	336294	0	0	0
T25	83403	0	0	0
T26	330247	0	0	0
T27	976824	0	0	0
T28	305347	0	0	0
T29	119686	0	0	0
T30	838158	0	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1341	0	0
T12	406890	16	0	0
T13	0	33	0	0
T14	0	10	0	0
T15	0	33	0	0
T16	0	27	0	0
T17	0	29	0	0
T18	0	44	0	0
T19	0	44	0	0
T20	0	16	0	0
T21	0	7	0	0
T22	824051	0	0	0
T23	30051	0	0	0
T24	336294	0	0	0
T25	83403	0	0	0
T26	330247	0	0	0
T27	976824	0	0	0
T28	305347	0	0	0
T29	119686	0	0	0
T30	838158	0	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1751	0	0
T12	406890	15	0	0
T13	0	19	0	0
T14	0	20	0	0
T15	0	19	0	0
T16	0	22	0	0
T17	0	20	0	0
T18	0	18	0	0
T19	0	32	0	0
T20	0	10	0	0
T22	824051	0	0	0
T23	30051	0	0	0
T24	336294	0	0	0
T25	83403	0	0	0
T26	330247	0	0	0
T27	976824	0	0	0
T28	305347	0	0	0
T29	119686	0	0	0
T30	838158	0	0	0
T31	0	8	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1335	0	0
T12	406890	20	0	0
T13	0	30	0	0
T14	0	24	0	0
T15	0	19	0	0
T16	0	29	0	0
T17	0	24	0	0
T18	0	19	0	0
T19	0	24	0	0
T20	0	40	0	0
T21	0	21	0	0
T22	824051	0	0	0
T23	30051	0	0	0
T24	336294	0	0	0
T25	83403	0	0	0
T26	330247	0	0	0
T27	976824	0	0	0
T28	305347	0	0	0
T29	119686	0	0	0
T30	838158	0	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1654	0	0
T12	406890	14	0	0
T13	0	33	0	0
T14	0	6	0	0
T15	0	36	0	0
T16	0	12	0	0
T17	0	36	0	0
T18	0	11	0	0
T19	0	48	0	0
T20	0	20	0	0
T21	0	16	0	0
T22	824051	0	0	0
T23	30051	0	0	0
T24	336294	0	0	0
T25	83403	0	0	0
T26	330247	0	0	0
T27	976824	0	0	0
T28	305347	0	0	0
T29	119686	0	0	0
T30	838158	0	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1308	0	0
T12	406890	18	0	0
T13	0	18	0	0
T14	0	17	0	0
T15	0	36	0	0
T16	0	32	0	0
T17	0	17	0	0
T18	0	24	0	0
T19	0	23	0	0
T20	0	15	0	0
T21	0	12	0	0
T22	824051	0	0	0
T23	30051	0	0	0
T24	336294	0	0	0
T25	83403	0	0	0
T26	330247	0	0	0
T27	976824	0	0	0
T28	305347	0	0	0
T29	119686	0	0	0
T30	838158	0	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1368	0	0
T12	406890	32	0	0
T13	0	49	0	0
T14	0	5	0	0
T15	0	40	0	0
T16	0	39	0	0
T17	0	14	0	0
T18	0	20	0	0
T19	0	46	0	0
T20	0	15	0	0
T22	824051	0	0	0
T23	30051	0	0	0
T24	336294	0	0	0
T25	83403	0	0	0
T26	330247	0	0	0
T27	976824	0	0	0
T28	305347	0	0	0
T29	119686	0	0	0
T30	838158	0	0	0
T31	0	3	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1803	0	0
T12	406890	27	0	0
T13	0	48	0	0
T14	0	37	0	0
T15	0	71	0	0
T16	0	31	0	0
T17	0	34	0	0
T18	0	19	0	0
T19	0	68	0	0
T22	824051	0	0	0
T23	30051	0	0	0
T24	336294	0	0	0
T25	83403	0	0	0
T26	330247	0	0	0
T27	976824	0	0	0
T28	305347	0	0	0
T29	119686	0	0	0
T30	838158	0	0	0
T32	0	4	0	0
T33	0	10	0	0