Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1124469	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1103995

1

T1

40

T4

6

T2

470

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1946011	1			T4	1		T2	837		T6	7996
values[0x0]	140923	1			T1	29		T4	9		T2	50
values[0x1]	141530	1			T1	32		T4	5		T2	51

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	899766	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1328698

1

T1

43

T4

7

T2

566

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	6609	1			T6	58		T7	3		T8	2
valid_sources[0x01]	7152	1			T6	22		T7	7		T8	1
valid_sources[0x02]	6688	1			T6	25		T7	14		T11	4
valid_sources[0x03]	6430	1			T5	2		T6	32		T7	7
valid_sources[0x04]	6525	1			T5	2		T6	17		T7	33
valid_sources[0x05]	6701	1			T6	32		T7	7		T8	7
valid_sources[0x06]	6288	1			T6	45		T7	13		T8	4
valid_sources[0x07]	10766	1			T6	48		T7	16		T8	9
valid_sources[0x08]	6355	1			T6	13		T7	16		T8	7
valid_sources[0x09]	7267	1			T6	16		T7	1		T8	6
valid_sources[0x0a]	10967	1			T6	27		T7	8		T8	2
valid_sources[0x0b]	6648	1			T6	17		T7	6		T8	2
valid_sources[0x0c]	8452	1			T6	38		T7	16		T8	3
valid_sources[0x0d]	7357	1			T3	1		T6	27		T7	2
valid_sources[0x0e]	19534	1			T3	2		T5	1		T6	20
valid_sources[0x0f]	6157	1			T6	15		T7	2		T8	3
valid_sources[0x10]	6652	1			T6	52		T7	5		T8	2
valid_sources[0x11]	6343	1			T6	41		T7	2		T8	4
valid_sources[0x12]	7096	1			T4	1		T6	25		T7	13
valid_sources[0x13]	6516	1			T6	62		T7	10		T8	6
valid_sources[0x14]	6389	1			T3	1		T6	19		T7	16
valid_sources[0x15]	12121	1			T6	40		T7	13		T8	6
valid_sources[0x16]	8602	1			T5	2		T6	32		T7	3
valid_sources[0x17]	6864	1			T6	24		T7	5		T8	6
valid_sources[0x18]	6377	1			T6	39		T7	7		T8	3
valid_sources[0x19]	9449	1			T6	27		T7	4		T8	3
valid_sources[0x1a]	6259	1			T6	59		T7	7		T8	6
valid_sources[0x1b]	6659	1			T6	34		T7	7		T8	2
valid_sources[0x1c]	22324	1			T6	39		T7	4		T8	1
valid_sources[0x1d]	6427	1			T6	37		T7	13		T8	1
valid_sources[0x1e]	6972	1			T5	2		T6	34		T7	6
valid_sources[0x1f]	7160	1			T4	4		T6	46		T7	24
valid_sources[0x20]	10009	1			T6	30		T7	9		T8	7
valid_sources[0x21]	16279	1			T6	52		T7	1		T8	6
valid_sources[0x22]	6381	1			T6	35		T7	3		T8	8
valid_sources[0x23]	13769	1			T6	40		T7	6		T8	3
valid_sources[0x24]	6809	1			T6	34		T7	2		T8	3
valid_sources[0x25]	15523	1			T6	37		T7	9		T8	4
valid_sources[0x26]	6385	1			T6	26		T7	9		T8	7
valid_sources[0x27]	6755	1			T6	28		T7	7		T8	3
valid_sources[0x28]	6425	1			T6	37		T7	9		T8	1
valid_sources[0x29]	7263	1			T6	18		T7	22		T8	3
valid_sources[0x2a]	6926	1			T6	25		T7	16		T8	6
valid_sources[0x2b]	7469	1			T6	98		T7	6		T8	1
valid_sources[0x2c]	7101	1			T6	27		T7	5		T8	3
valid_sources[0x2d]	11823	1			T6	61		T7	9		T8	2
valid_sources[0x2e]	6679	1			T5	1		T6	37		T7	7
valid_sources[0x2f]	13166	1			T3	1		T6	36		T7	9
valid_sources[0x30]	6893	1			T5	1		T6	31		T7	4
valid_sources[0x31]	9379	1			T6	30		T7	10		T8	4
valid_sources[0x32]	7161	1			T6	14		T7	7		T8	5
valid_sources[0x33]	7062	1			T6	20		T7	3		T11	3
valid_sources[0x34]	7491	1			T6	14		T7	1		T8	5
valid_sources[0x35]	11040	1			T6	21		T7	3		T8	16
valid_sources[0x36]	11606	1			T5	1		T6	13		T7	5
valid_sources[0x37]	6165	1			T6	34		T7	2		T8	2
valid_sources[0x38]	6346	1			T5	1		T6	31		T7	2
valid_sources[0x39]	6524	1			T6	36		T7	11		T8	3
valid_sources[0x3a]	8271	1			T6	25		T7	3		T8	12
valid_sources[0x3b]	13914	1			T6	27		T7	24		T8	2
valid_sources[0x3c]	6378	1			T6	19		T7	7		T8	5
valid_sources[0x3d]	7372	1			T6	36		T7	10		T8	7
valid_sources[0x3e]	10843	1			T6	22		T7	5		T8	11
valid_sources[0x3f]	7590	1			T6	61		T7	5		T8	3
valid_sources[0x40]	6469	1			T6	29		T7	5		T8	7
valid_sources[0x41]	6430	1			T5	1		T6	25		T7	26
valid_sources[0x42]	9261	1			T6	26		T7	2		T8	7
valid_sources[0x43]	6762	1			T6	16		T7	11		T8	6
valid_sources[0x44]	7569	1			T6	43		T7	2		T8	3
valid_sources[0x45]	23650	1			T5	1		T6	38		T7	4
valid_sources[0x46]	6479	1			T6	24		T7	4		T8	6
valid_sources[0x47]	9503	1			T3	1		T5	2		T6	67
valid_sources[0x48]	8189	1			T6	22		T7	11		T8	6
valid_sources[0x49]	6651	1			T6	37		T7	15		T8	7
valid_sources[0x4a]	13578	1			T6	22		T7	5		T8	1
valid_sources[0x4b]	11367	1			T6	30		T7	3		T8	5
valid_sources[0x4c]	6538	1			T6	62		T7	18		T12	9
valid_sources[0x4d]	6250	1			T6	21		T7	1		T8	3
valid_sources[0x4e]	14136	1			T6	48		T7	13		T8	2
valid_sources[0x4f]	9266	1			T3	4		T6	41		T7	7
valid_sources[0x50]	8537	1			T6	19		T7	6		T8	5
valid_sources[0x51]	6918	1			T6	19		T7	3		T8	4
valid_sources[0x52]	6517	1			T6	42		T7	5		T8	3
valid_sources[0x53]	6509	1			T6	56		T7	2		T8	6
valid_sources[0x54]	12526	1			T6	38		T7	18		T8	6
valid_sources[0x55]	8588	1			T4	3		T5	1		T6	31
valid_sources[0x56]	6697	1			T6	51		T7	2		T11	6
valid_sources[0x57]	13190	1			T3	1		T6	17		T7	2
valid_sources[0x58]	10365	1			T6	21		T7	3		T8	6
valid_sources[0x59]	6571	1			T6	34		T7	5		T8	3
valid_sources[0x5a]	8563	1			T6	28		T7	3		T8	3
valid_sources[0x5b]	6583	1			T1	61		T6	25		T7	4
valid_sources[0x5c]	7038	1			T6	26		T7	4		T8	5
valid_sources[0x5d]	8216	1			T6	23		T7	14		T11	14
valid_sources[0x5e]	6564	1			T6	33		T7	12		T8	5
valid_sources[0x5f]	6576	1			T6	28		T7	12		T8	5
valid_sources[0x60]	6316	1			T6	34		T7	12		T8	2
valid_sources[0x61]	7978	1			T6	16		T7	4		T8	2
valid_sources[0x62]	10819	1			T6	67		T7	16		T8	7
valid_sources[0x63]	6362	1			T6	40		T7	12		T8	5
valid_sources[0x64]	11343	1			T6	34		T7	3		T8	3
valid_sources[0x65]	7632	1			T6	25		T7	5		T8	7
valid_sources[0x66]	6608	1			T6	32		T7	4		T8	1
valid_sources[0x67]	9164	1			T3	1		T6	51		T7	4
valid_sources[0x68]	12178	1			T6	34		T7	7		T8	4
valid_sources[0x69]	10012	1			T6	22		T7	16		T8	9
valid_sources[0x6a]	12503	1			T6	35		T7	5		T8	4
valid_sources[0x6b]	8247	1			T6	52		T7	4		T8	4
valid_sources[0x6c]	6548	1			T6	23		T7	11		T8	6
valid_sources[0x6d]	6299	1			T6	26		T7	7		T8	2
valid_sources[0x6e]	6997	1			T5	2		T6	21		T7	13
valid_sources[0x6f]	14082	1			T6	26		T7	10		T8	1
valid_sources[0x70]	13763	1			T6	41		T7	5		T11	9
valid_sources[0x71]	6382	1			T6	47		T7	5		T8	6
valid_sources[0x72]	8898	1			T6	30		T7	2		T8	5
valid_sources[0x73]	9496	1			T6	43		T7	7		T8	10
valid_sources[0x74]	10652	1			T6	56		T7	3		T8	6
valid_sources[0x75]	7558	1			T6	49		T7	12		T8	6
valid_sources[0x76]	10996	1			T3	1		T6	17		T7	4
valid_sources[0x77]	7250	1			T6	12		T7	5		T8	2
valid_sources[0x78]	8033	1			T2	938		T6	71		T7	4
valid_sources[0x79]	6168	1			T4	2		T6	44		T7	17
valid_sources[0x7a]	7474	1			T6	27		T8	5		T9	2
valid_sources[0x7b]	6496	1			T6	51		T7	9		T8	6
valid_sources[0x7c]	7174	1			T6	37		T7	7		T8	7
valid_sources[0x7d]	6525	1			T6	36		T7	8		T8	3
valid_sources[0x7e]	6444	1			T6	28		T7	5		T8	3
valid_sources[0x7f]	10844	1			T6	23		T7	11		T8	5
valid_sources[0x80]	6456	1			T6	56		T7	20		T8	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

969803

1

T2

420

T6

3940

T7

860

values[0x0]

all_enables

biggest_size

77780

1

T1

18

T4

5

T2

29

values[0x1]

all_enables

biggest_size

56412

1

T1

22

T4

1

T2

21