Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
97.78	97.78	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	97.78	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.78	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	1	44	97.78

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	0	17	100.00	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	1	15	93.75	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	0	17	100.00

Automatically Generated Bins for fsm_state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2215	1			T8	15		T9	15		T49	21
auto[PWRUP]	116	1			T9	4		T49	6		T50	2
auto[ONEST_0]	79	1			T9	1		T209	1		T54	1
auto[ONEST_021]	13	1			T50	1		T51	1		T30	1
auto[ONEST_1]	97	1			T8	1		T9	4		T49	2
auto[ONEST_DONE]	3	1			T341	1		T342	1		T343	1
auto[LP_0]	124	1			T8	1		T49	5		T50	3
auto[LP_021]	24	1			T49	2		T51	1		T52	1
auto[LP_1]	129	1			T8	1		T49	3		T50	3
auto[LP_EVAL]	44	1			T41	1		T53	2		T51	1
auto[LP_SLP]	518	1			T9	8		T49	4		T50	9
auto[LP_PWRUP]	27	1			T40	1		T53	2		T43	1
auto[NP_0]	209	1			T8	1		T9	1		T49	1
auto[NP_021]	49	1			T49	1		T40	1		T53	1
auto[NP_1]	201	1			T8	3		T9	1		T49	2
auto[NP_EVAL]	34	1			T49	1		T209	2		T42	2
auto[NP_DONE]	1	1			T55	1		-	-		-	-

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

6

1

T344

1

T279

1

T240

1

min

1931

1

T8

22

T9

11

T49

7

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1946	1			T8	22		T9	11		T49	8
pow[0x1]	12	1			T40	1		T53	2		T43	1
pow[0x2]	16	1			T40	1		T53	1		T42	1
pow[0x3]	34	1			T49	1		T50	1		T51	1
pow[0x4]	52	1			T209	1		T29	1		T34	2
pow[0x5]	118	1			T50	3		T53	1		T51	3
pow[0x6]	225	1			T9	3		T49	3		T50	2
pow[0x7]	484	1			T9	6		T49	12		T50	6

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

208

1

T9

1

T50

5

T53

2

min

1349

1

T8

18

T9

4

T49

2

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	1	15	93.75

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x5]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1356	1			T8	18		T9	4		T49	2
pow[0x1]	17	1			T40	1		T42	5		T17	5
pow[0x2]	22	1			T8	2		T42	1		T44	2
pow[0x3]	57	1			T8	2		T40	2		T33	3
pow[0x4]	42	1			T41	2		T42	1		T16	2
pow[0x6]	2	1			T345	1		T346	1		-	-
pow[0x7]	2	1			T310	1		T347	1		-	-
pow[0x8]	5	1			T49	1		T34	1		T348	1
pow[0x9]	9	1			T9	1		T50	1		T52	1
pow[0xa]	15	1			T50	1		T51	1		T43	1
pow[0xb]	32	1			T9	1		T53	1		T34	1
pow[0xc]	73	1			T9	1		T49	1		T50	1
pow[0xd]	158	1			T9	1		T49	5		T50	2
pow[0xe]	304	1			T9	3		T49	5		T50	6
pow[0xf]	535	1			T9	7		T49	9		T50	7