Unified Coverage Report :: Module :: prim_reg_cdc

Module : prim_reg_cdc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.37	100.00	89.49			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_adc_chn_val_0_cdc	78.29	94.12	85.71			83.33	50.00
tb.dut.u_reg.u_adc_chn_val_1_cdc	78.29	94.12	85.71			83.33	50.00
tb.dut.u_reg.u_filter_status_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_adc_fsm_state_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_adc_en_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_adc_pd_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_adc_lp_sample_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_adc_sample_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_adc_wakeup_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_adc_fsm_rst_cdc	98.08	100.00	92.31			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn_val_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
78.29	94.12	85.71			83.33	50.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
78.01	95.31	67.24			89.47	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	87.67	94.90	67.39			88.37	100.00
u_src_to_dst_req	60.00	100.00	40.00			100.00	0.00

---

Module Instance : tb.dut.u_reg.u_adc_chn_val_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
78.29	94.12	85.71			83.33	50.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
78.01	95.31	67.24			89.47	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	87.67	94.90	67.39			88.37	100.00
u_src_to_dst_req	60.00	100.00	40.00			100.00	0.00

---

Module Instance : tb.dut.u_reg.u_filter_status_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.74	100.00	92.65			98.31	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.79	100.00	93.48			97.67	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_adc_fsm_state_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.72	98.44	79.69			94.74	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	86.03	97.87	78.57			92.68	75.00
u_src_to_dst_req	93.75	100.00	75.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_adc_en_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_adc_pd_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_adc_lp_sample_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_adc_sample_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_adc_wakeup_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_adc_fsm_rst_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.08	100.00	92.31			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.22	100.00	96.88			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Line Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Module : prim_reg_cdc ( parameter DataWidth=2,ResetVal=0,BitMask=3,DstWrReq=0,TxnWidth=3 + DataWidth=32,ResetVal,BitMask,DstWrReq=0,TxnWidth=3 + DataWidth=8,ResetVal=4,BitMask=255,DstWrReq=0,TxnWidth=3 + DataWidth=16,ResetVal=155,BitMask=65535,DstWrReq=0,TxnWidth=3 + DataWidth=28,ResetVal=0,BitMask=268374015,DstWrReq=1,TxnWidth=3 + DataWidth=9,ResetVal=0,BitMask=511,DstWrReq=0,TxnWidth=3 + DataWidth=9,ResetVal=0,BitMask=511,DstWrReq=1,TxnWidth=3 + DataWidth=5,ResetVal=0,BitMask=31,DstWrReq=1,TxnWidth=3 )
Cond Coverage for Module self-instances :

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_adc_en_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_adc_pd_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_adc_lp_sample_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_adc_sample_ctl_cdc

SCORE	COND
78.29	85.71

tb.dut.u_reg.u_adc_chn_val_0_cdc

SCORE	COND
78.29	85.71

tb.dut.u_reg.u_adc_chn_val_1_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_adc_wakeup_ctl_cdc

SCORE	COND
96.43	85.71

tb.dut.u_reg.u_filter_status_cdc

SCORE	COND
96.43	85.71

tb.dut.u_reg.u_adc_fsm_state_cdc

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Covered	T8,T40,T41
1	0	Covered	T1,T4,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T2

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_reg_cdc ( parameter DataWidth=1,ResetVal=0,BitMask=1,DstWrReq=0,TxnWidth=3 )
Cond Coverage for Module self-instances :

SCORE	COND
98.08	92.31

tb.dut.u_reg.u_adc_fsm_rst_cdc

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T2,T6,T7

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T2,T6,T7
1	1	Covered	T2,T6,T7

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T2,T6,T7
1	-	Covered	T2,T6,T7

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T2,T6,T7

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T6,T7
1	1	Covered	T2,T6,T7

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T1,T4,T2
0	0	1	Covered	T1,T4,T2
0	0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T1,T4,T2
0	0	1	Covered	T1,T4,T2
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Module : prim_reg_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	182509746	0	0
DstReqKnown_A	874163238	865454044	0	0
SrcAckBusyChk_A	2147483647	196915	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	182509746	0	0
T1	266618	18220	0	0
T2	8634010	9582	0	0
T3	4920014	37648	0	0
T4	121312	0	0	0
T5	9715596	58662	0	0
T6	4182090	37943	0	0
T7	7350156	67127	0	0
T8	11537256	281581	0	0
T9	5844312	786727	0	0
T10	21300816	14462	0	0
T11	7725344	70764	0	0
T12	9487180	7140	0	0
T13	317994	24772	0	0
T14	227244	16422	0	0
T15	643208	61208	0	0
T16	0	1355	0	0
T25	4044	0	0	0
T26	931336	1728	0	0
T40	0	1953	0	0
T41	0	699	0	0
T42	0	1729	0	0
T43	0	1166	0	0
T44	0	213	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	874163238	865454044	0	0
T1	27690	25818	0	0
T2	850304	848796	0	0
T3	125008	123266	0	0
T4	1612	130	0	0
T5	23634	21320	0	0
T6	1929564	1927016	0	0
T7	1767766	1765790	0	0
T8	314366	284830	0	0
T9	1266226	1199016	0	0
T10	170872	169572	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	196915	0	0
T1	266618	41	0	0
T2	8634010	21	0	0
T3	4920014	23	0	0
T4	121312	0	0	0
T5	9715596	35	0	0
T6	4182090	42	0	0
T7	7350156	42	0	0
T8	11537256	194	0	0
T9	5844312	448	0	0
T10	21300816	29	0	0
T11	7725344	42	0	0
T12	9487180	54	0	0
T13	317994	18	0	0
T14	227244	54	0	0
T15	643208	36	0	0
T16	0	1	0	0
T25	4044	0	0	0
T26	931336	4	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	3466034	3464032	0	0
T2	10203830	10203622	0	0
T3	5814562	5814380	0	0
T4	788528	786734	0	0
T5	11482068	11479598	0	0
T6	4727580	4727554	0	0
T7	8308872	8308846	0	0
T8	12498694	12432446	0	0
T9	6331338	6330662	0	0
T10	23075884	23073570	0	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		17	16	94.12
CONT_ASSIGN	54	0	0
ALWAYS	60	5	4	80.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	7	7	100.00
CONT_ASSIGN	139	0	0
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54		unreachable
60	1	1
61	1	1
62	1	1
63		unreachable
64	1	1
65	0	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112		unreachable
113		unreachable
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139		unreachable
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_0_cdc

	Total	Covered	Percent
Conditions	7	6	85.71
Logical	7	6	85.71
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Unreachable

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T4,T2
1	0	Excluded		VC_COV_UNR
1	1	Excluded		VC_COV_UNR

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests	Exclude Annotation
0	0	Covered	T1,T4,T2
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Not Covered
1	0	Excluded		VC_COV_UNR
1	1	Excluded		VC_COV_UNR

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T4,T2
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_0_cdc

	Line No.	Total	Covered	Percent
Branches		6	5	83.33
IF	60	3	2	66.67
IF	104	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Unreachable
0	0	1	Not Covered
0	0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Unreachable
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	2	50.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	2	50.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	0	0	0
DstReqKnown_A	33621663	33286694	0	0
SrcAckBusyChk_A	2147483647	0	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33621663	33286694	0	0
T1	1065	993	0	0
T2	32704	32646	0	0
T3	4808	4741	0	0
T4	62	5	0	0
T5	909	820	0	0
T6	74214	74116	0	0
T7	67991	67915	0	0
T8	12091	10955	0	0
T9	48701	46116	0	0
T10	6572	6522	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	133309	133232	0	0
T2	392455	392447	0	0
T3	223637	223630	0	0
T4	30328	30259	0	0
T5	441618	441523	0	0
T6	181830	181829	0	0
T7	319572	319571	0	0
T8	480719	478171	0	0
T9	243513	243487	0	0
T10	887534	887445	0	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		17	16	94.12
CONT_ASSIGN	54	0	0
ALWAYS	60	5	4	80.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	7	7	100.00
CONT_ASSIGN	139	0	0
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54		unreachable
60	1	1
61	1	1
62	1	1
63		unreachable
64	1	1
65	0	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112		unreachable
113		unreachable
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139		unreachable
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_1_cdc

	Total	Covered	Percent
Conditions	7	6	85.71
Logical	7	6	85.71
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Unreachable

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T4,T2
1	0	Excluded		VC_COV_UNR
1	1	Excluded		VC_COV_UNR

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests	Exclude Annotation
0	0	Covered	T1,T4,T2
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Not Covered
1	0	Excluded		VC_COV_UNR
1	1	Excluded		VC_COV_UNR

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T4,T2
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_1_cdc

	Line No.	Total	Covered	Percent
Branches		6	5	83.33
IF	60	3	2	66.67
IF	104	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Unreachable
0	0	1	Not Covered
0	0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Unreachable
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	2	50.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	2	50.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	0	0	0
DstReqKnown_A	33621663	33286694	0	0
SrcAckBusyChk_A	2147483647	0	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33621663	33286694	0	0
T1	1065	993	0	0
T2	32704	32646	0	0
T3	4808	4741	0	0
T4	62	5	0	0
T5	909	820	0	0
T6	74214	74116	0	0
T7	67991	67915	0	0
T8	12091	10955	0	0
T9	48701	46116	0	0
T10	6572	6522	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	133309	133232	0	0
T2	392455	392447	0	0
T3	223637	223630	0	0
T4	30328	30259	0	0
T5	441618	441523	0	0
T6	181830	181829	0	0
T7	319572	319571	0	0
T8	480719	478171	0	0
T9	243513	243487	0	0
T10	887534	887445	0	0

Line Coverage for Instance : tb.dut.u_reg.u_filter_status_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_filter_status_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T2,T6,T7

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T2,T6,T7
1	1	Covered	T2,T6,T7

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Covered	T2,T6,T7
1	0	Covered	T2,T6,T7

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T6,T7
1	1	Covered	T2,T6,T7

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Not Covered
1	1	Covered	T2,T6,T7

---

Branch Coverage for Instance : tb.dut.u_reg.u_filter_status_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T2,T6,T7
0	0	1	Covered	T2,T6,T7
0	0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T2,T6,T7
0	0	1	Covered	T2,T6,T7
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_filter_status_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	62304985	0	0
DstReqKnown_A	33621663	33286694	0	0
SrcAckBusyChk_A	2147483647	64207	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	62304985	0	0
T2	392455	31206	0	0
T3	223637	0	0	0
T5	441618	0	0	0
T6	181830	120221	0	0
T7	319572	221193	0	0
T8	480719	19795	0	0
T9	243513	135377	0	0
T10	887534	0	0	0
T11	351152	267484	0	0
T12	474359	33646	0	0
T13	0	149827	0	0
T14	0	92332	0	0
T15	0	296903	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33621663	33286694	0	0
T1	1065	993	0	0
T2	32704	32646	0	0
T3	4808	4741	0	0
T4	62	5	0	0
T5	909	820	0	0
T6	74214	74116	0	0
T7	67991	67915	0	0
T8	12091	10955	0	0
T9	48701	46116	0	0
T10	6572	6522	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	64207	0	0
T2	392455	75	0	0
T3	223637	0	0	0
T5	441618	0	0	0
T6	181830	146	0	0
T7	319572	134	0	0
T8	480719	13	0	0
T9	243513	79	0	0
T10	887534	0	0	0
T11	351152	160	0	0
T12	474359	240	0	0
T13	0	90	0	0
T14	0	232	0	0
T15	0	174	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	133309	133232	0	0
T2	392455	392447	0	0
T3	223637	223630	0	0
T4	30328	30259	0	0
T5	441618	441523	0	0
T6	181830	181829	0	0
T7	319572	319571	0	0
T8	480719	478171	0	0
T9	243513	243487	0	0
T10	887534	887445	0	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_fsm_state_cdc

	Line No.	Total	Covered	Percent
TOTAL		21	21	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	0	0
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139		unreachable
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_adc_fsm_state_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Covered	T8,T40,T41
1	0	Unreachable

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T8,T40,T41
1	1	Covered	T8,T40,T41

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T40,T41

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T8,T40,T41
1	1	Covered	T8,T40,T41

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_adc_fsm_state_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T8,T40,T41
0	0	1	Covered	T8,T40,T41
0	0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T8,T40,T41
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_adc_fsm_state_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	94673	0	0
DstReqKnown_A	33621663	33286694	0	0
SrcAckBusyChk_A	2147483647	82	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	94673	0	0
T8	480719	2227	0	0
T9	243513	0	0	0
T10	887534	0	0	0
T11	351152	0	0	0
T12	474359	0	0	0
T13	158997	0	0	0
T14	113622	0	0	0
T15	321604	0	0	0
T16	0	1355	0	0
T17	0	2876	0	0
T25	4044	0	0	0
T26	931336	0	0	0
T33	0	1779	0	0
T36	0	1416	0	0
T40	0	1953	0	0
T41	0	699	0	0
T42	0	1729	0	0
T43	0	1166	0	0
T44	0	213	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33621663	33286694	0	0
T1	1065	993	0	0
T2	32704	32646	0	0
T3	4808	4741	0	0
T4	62	5	0	0
T5	909	820	0	0
T6	74214	74116	0	0
T7	67991	67915	0	0
T8	12091	10955	0	0
T9	48701	46116	0	0
T10	6572	6522	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	82	0	0
T8	480719	1	0	0
T9	243513	0	0	0
T10	887534	0	0	0
T11	351152	0	0	0
T12	474359	0	0	0
T13	158997	0	0	0
T14	113622	0	0	0
T15	321604	0	0	0
T16	0	1	0	0
T17	0	1	0	0
T25	4044	0	0	0
T26	931336	0	0	0
T33	0	1	0	0
T36	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	133309	133232	0	0
T2	392455	392447	0	0
T3	223637	223630	0	0
T4	30328	30259	0	0
T5	441618	441523	0	0
T6	181830	181829	0	0
T7	319572	319571	0	0
T8	480719	478171	0	0
T9	243513	243487	0	0
T10	887534	887445	0	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_en_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_adc_en_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_adc_en_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_adc_en_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	32828830	0	0
DstReqKnown_A	33621663	33286694	0	0
SrcAckBusyChk_A	2147483647	36322	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	32828830	0	0
T1	133309	18220	0	0
T2	392455	1317	0	0
T3	223637	37648	0	0
T4	30328	0	0	0
T5	441618	58662	0	0
T6	181830	5117	0	0
T7	319572	9826	0	0
T8	480719	165241	0	0
T9	243513	445460	0	0
T10	887534	14462	0	0
T11	0	10180	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33621663	33286694	0	0
T1	1065	993	0	0
T2	32704	32646	0	0
T3	4808	4741	0	0
T4	62	5	0	0
T5	909	820	0	0
T6	74214	74116	0	0
T7	67991	67915	0	0
T8	12091	10955	0	0
T9	48701	46116	0	0
T10	6572	6522	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	36322	0	0
T1	133309	41	0	0
T2	392455	3	0	0
T3	223637	23	0	0
T4	30328	0	0	0
T5	441618	35	0	0
T6	181830	6	0	0
T7	319572	6	0	0
T8	480719	113	0	0
T9	243513	256	0	0
T10	887534	29	0	0
T11	0	6	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	133309	133232	0	0
T2	392455	392447	0	0
T3	223637	223630	0	0
T4	30328	30259	0	0
T5	441618	441523	0	0
T6	181830	181829	0	0
T7	319572	319571	0	0
T8	480719	478171	0	0
T9	243513	243487	0	0
T10	887534	887445	0	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_pd_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_adc_pd_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_adc_pd_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_adc_pd_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	14925376	0	0
DstReqKnown_A	33621663	33286694	0	0
SrcAckBusyChk_A	2147483647	17050	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	14925376	0	0
T1	133309	8972	0	0
T2	392455	800	0	0
T3	223637	17652	0	0
T4	30328	0	0	0
T5	441618	28591	0	0
T6	181830	3158	0	0
T7	319572	6319	0	0
T8	480719	59462	0	0
T9	243513	221451	0	0
T10	887534	6701	0	0
T11	0	6711	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33621663	33286694	0	0
T1	1065	993	0	0
T2	32704	32646	0	0
T3	4808	4741	0	0
T4	62	5	0	0
T5	909	820	0	0
T6	74214	74116	0	0
T7	67991	67915	0	0
T8	12091	10955	0	0
T9	48701	46116	0	0
T10	6572	6522	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	17050	0	0
T1	133309	20	0	0
T2	392455	2	0	0
T3	223637	11	0	0
T4	30328	0	0	0
T5	441618	17	0	0
T6	181830	4	0	0
T7	319572	4	0	0
T8	480719	42	0	0
T9	243513	128	0	0
T10	887534	14	0	0
T11	0	4	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	133309	133232	0	0
T2	392455	392447	0	0
T3	223637	223630	0	0
T4	30328	30259	0	0
T5	441618	441523	0	0
T6	181830	181829	0	0
T7	319572	319571	0	0
T8	480719	478171	0	0
T9	243513	243487	0	0
T10	887534	887445	0	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_lp_sample_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_adc_lp_sample_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T4,T2,T6

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T4,T2,T6
1	1	Covered	T4,T2,T6

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T4,T2,T6

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T2,T6
1	1	Covered	T4,T2,T6

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_adc_lp_sample_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T4,T2,T6
0	0	1	Covered	T4,T2,T6
0	0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T4,T2,T6
0	0	1	Covered	T4,T2,T6
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_adc_lp_sample_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	11756837	0	0
DstReqKnown_A	33621663	33286694	0	0
SrcAckBusyChk_A	2147483647	13462	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	11756837	0	0
T2	392455	445	0	0
T3	223637	0	0	0
T4	30328	1266	0	0
T5	441618	0	0	0
T6	181830	1712	0	0
T7	319572	3044	0	0
T8	480719	10257	0	0
T9	243513	222133	0	0
T10	887534	0	0	0
T11	351152	3324	0	0
T12	0	334	0	0
T13	0	1223	0	0
T14	0	810	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33621663	33286694	0	0
T1	1065	993	0	0
T2	32704	32646	0	0
T3	4808	4741	0	0
T4	62	5	0	0
T5	909	820	0	0
T6	74214	74116	0	0
T7	67991	67915	0	0
T8	12091	10955	0	0
T9	48701	46116	0	0
T10	6572	6522	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	13462	0	0
T2	392455	1	0	0
T3	223637	0	0	0
T4	30328	1	0	0
T5	441618	0	0	0
T6	181830	2	0	0
T7	319572	2	0	0
T8	480719	8	0	0
T9	243513	128	0	0
T10	887534	0	0	0
T11	351152	2	0	0
T12	0	3	0	0
T13	0	1	0	0
T14	0	3	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	133309	133232	0	0
T2	392455	392447	0	0
T3	223637	223630	0	0
T4	30328	30259	0	0
T5	441618	441523	0	0
T6	181830	181829	0	0
T7	319572	319571	0	0
T8	480719	478171	0	0
T9	243513	243487	0	0
T10	887534	887445	0	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_sample_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_adc_sample_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T4,T2,T6

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T4,T2,T6
1	1	Covered	T4,T2,T6

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T4,T2,T6

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T2,T6
1	1	Covered	T4,T2,T6

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_adc_sample_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T4,T2,T6
0	0	1	Covered	T4,T2,T6
0	0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T4,T2,T6
0	0	1	Covered	T4,T2,T6
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_adc_sample_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	11820707	0	0
DstReqKnown_A	33621663	33286694	0	0
SrcAckBusyChk_A	2147483647	13466	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	11820707	0	0
T2	392455	447	0	0
T3	223637	0	0	0
T4	30328	1269	0	0
T5	441618	0	0	0
T6	181830	1727	0	0
T7	319572	3067	0	0
T8	480719	10326	0	0
T9	243513	222389	0	0
T10	887534	0	0	0
T11	351152	3328	0	0
T12	0	340	0	0
T13	0	1237	0	0
T14	0	825	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33621663	33286694	0	0
T1	1065	993	0	0
T2	32704	32646	0	0
T3	4808	4741	0	0
T4	62	5	0	0
T5	909	820	0	0
T6	74214	74116	0	0
T7	67991	67915	0	0
T8	12091	10955	0	0
T9	48701	46116	0	0
T10	6572	6522	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	13466	0	0
T2	392455	1	0	0
T3	223637	0	0	0
T4	30328	1	0	0
T5	441618	0	0	0
T6	181830	2	0	0
T7	319572	2	0	0
T8	480719	8	0	0
T9	243513	128	0	0
T10	887534	0	0	0
T11	351152	2	0	0
T12	0	3	0	0
T13	0	1	0	0
T14	0	3	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	133309	133232	0	0
T2	392455	392447	0	0
T3	223637	223630	0	0
T4	30328	30259	0	0
T5	441618	441523	0	0
T6	181830	181829	0	0
T7	319572	319571	0	0
T8	480719	478171	0	0
T9	243513	243487	0	0
T10	887534	887445	0	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T2,T6,T7

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T2,T6,T7
1	1	Covered	T2,T6,T7

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T2,T6,T7

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T6,T7
1	1	Covered	T2,T6,T7

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T2,T6,T7
0	0	1	Covered	T2,T6,T7
0	0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T2,T6,T7
0	0	1	Covered	T2,T6,T7
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	2048954	0	0
DstReqKnown_A	33621663	33286694	0	0
SrcAckBusyChk_A	2147483647	2107	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2048954	0	0
T2	392455	479	0	0
T3	223637	0	0	0
T5	441618	0	0	0
T6	181830	1939	0	0
T7	319572	3281	0	0
T8	480719	7522	0	0
T9	243513	3998	0	0
T10	887534	0	0	0
T11	351152	3392	0	0
T12	474359	436	0	0
T13	0	1432	0	0
T14	0	990	0	0
T15	0	3465	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33621663	33286694	0	0
T1	1065	993	0	0
T2	32704	32646	0	0
T3	4808	4741	0	0
T4	62	5	0	0
T5	909	820	0	0
T6	74214	74116	0	0
T7	67991	67915	0	0
T8	12091	10955	0	0
T9	48701	46116	0	0
T10	6572	6522	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2107	0	0
T2	392455	1	0	0
T3	223637	0	0	0
T5	441618	0	0	0
T6	181830	2	0	0
T7	319572	2	0	0
T8	480719	5	0	0
T9	243513	2	0	0
T10	887534	0	0	0
T11	351152	2	0	0
T12	474359	3	0	0
T13	0	1	0	0
T14	0	3	0	0
T15	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	133309	133232	0	0
T2	392455	392447	0	0
T3	223637	223630	0	0
T4	30328	30259	0	0
T5	441618	441523	0	0
T6	181830	181829	0	0
T7	319572	319571	0	0
T8	480719	478171	0	0
T9	243513	243487	0	0
T10	887534	887445	0	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T2,T6,T7

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T2,T6,T7
1	1	Covered	T2,T6,T7

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T2,T6,T7

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T6,T7
1	1	Covered	T2,T6,T7

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T2,T6,T7
0	0	1	Covered	T2,T6,T7
0	0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T2,T6,T7
0	0	1	Covered	T2,T6,T7
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	1933325	0	0
DstReqKnown_A	33621663	33286694	0	0
SrcAckBusyChk_A	2147483647	2004	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1933325	0	0
T2	392455	477	0	0
T3	223637	0	0	0
T5	441618	0	0	0
T6	181830	1928	0	0
T7	319572	3264	0	0
T8	480719	7452	0	0
T9	243513	1997	0	0
T10	887534	0	0	0
T11	351152	3388	0	0
T12	474359	430	0	0
T13	0	1413	0	0
T14	0	958	0	0
T15	0	3459	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33621663	33286694	0	0
T1	1065	993	0	0
T2	32704	32646	0	0
T3	4808	4741	0	0
T4	62	5	0	0
T5	909	820	0	0
T6	74214	74116	0	0
T7	67991	67915	0	0
T8	12091	10955	0	0
T9	48701	46116	0	0
T10	6572	6522	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2004	0	0
T2	392455	1	0	0
T3	223637	0	0	0
T5	441618	0	0	0
T6	181830	2	0	0
T7	319572	2	0	0
T8	480719	5	0	0
T9	243513	1	0	0
T10	887534	0	0	0
T11	351152	2	0	0
T12	474359	3	0	0
T13	0	1	0	0
T14	0	3	0	0
T15	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	133309	133232	0	0
T2	392455	392447	0	0
T3	223637	223630	0	0
T4	30328	30259	0	0
T5	441618	441523	0	0
T6	181830	181829	0	0
T7	319572	319571	0	0
T8	480719	478171	0	0
T9	243513	243487	0	0
T10	887534	887445	0	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T2,T6,T7

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T2,T6,T7
1	1	Covered	T2,T6,T7

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T2,T6,T7

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T6,T7
1	1	Covered	T2,T6,T7

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T2,T6,T7
0	0	1	Covered	T2,T6,T7
0	0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T2,T6,T7
0	0	1	Covered	T2,T6,T7
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	1931071	0	0
DstReqKnown_A	33621663	33286694	0	0
SrcAckBusyChk_A	2147483647	1982	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1931071	0	0
T2	392455	475	0	0
T3	223637	0	0	0
T5	441618	0	0	0
T6	181830	1918	0	0
T7	319572	3249	0	0
T8	480719	7398	0	0
T9	243513	1995	0	0
T10	887534	0	0	0
T11	351152	3384	0	0
T12	474359	424	0	0
T13	0	1406	0	0
T14	0	930	0	0
T15	0	3442	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33621663	33286694	0	0
T1	1065	993	0	0
T2	32704	32646	0	0
T3	4808	4741	0	0
T4	62	5	0	0
T5	909	820	0	0
T6	74214	74116	0	0
T7	67991	67915	0	0
T8	12091	10955	0	0
T9	48701	46116	0	0
T10	6572	6522	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1982	0	0
T2	392455	1	0	0
T3	223637	0	0	0
T5	441618	0	0	0
T6	181830	2	0	0
T7	319572	2	0	0
T8	480719	5	0	0
T9	243513	1	0	0
T10	887534	0	0	0
T11	351152	2	0	0
T12	474359	3	0	0
T13	0	1	0	0
T14	0	3	0	0
T15	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	133309	133232	0	0
T2	392455	392447	0	0
T3	223637	223630	0	0
T4	30328	30259	0	0
T5	441618	441523	0	0
T6	181830	181829	0	0
T7	319572	319571	0	0
T8	480719	478171	0	0
T9	243513	243487	0	0
T10	887534	887445	0	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T2,T6,T7

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T2,T6,T7
1	1	Covered	T2,T6,T7

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T2,T6,T7

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T6,T7
1	1	Covered	T2,T6,T7

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T2,T6,T7
0	0	1	Covered	T2,T6,T7
0	0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T2,T6,T7
0	0	1	Covered	T2,T6,T7
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	1924374	0	0
DstReqKnown_A	33621663	33286694	0	0
SrcAckBusyChk_A	2147483647	2000	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1924374	0	0
T2	392455	473	0	0
T3	223637	0	0	0
T5	441618	0	0	0
T6	181830	1909	0	0
T7	319572	3226	0	0
T8	480719	7353	0	0
T9	243513	1993	0	0
T10	887534	0	0	0
T11	351152	3380	0	0
T12	474359	418	0	0
T13	0	1392	0	0
T14	0	906	0	0
T15	0	3426	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33621663	33286694	0	0
T1	1065	993	0	0
T2	32704	32646	0	0
T3	4808	4741	0	0
T4	62	5	0	0
T5	909	820	0	0
T6	74214	74116	0	0
T7	67991	67915	0	0
T8	12091	10955	0	0
T9	48701	46116	0	0
T10	6572	6522	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2000	0	0
T2	392455	1	0	0
T3	223637	0	0	0
T5	441618	0	0	0
T6	181830	2	0	0
T7	319572	2	0	0
T8	480719	5	0	0
T9	243513	1	0	0
T10	887534	0	0	0
T11	351152	2	0	0
T12	474359	3	0	0
T13	0	1	0	0
T14	0	3	0	0
T15	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	133309	133232	0	0
T2	392455	392447	0	0
T3	223637	223630	0	0
T4	30328	30259	0	0
T5	441618	441523	0	0
T6	181830	181829	0	0
T7	319572	319571	0	0
T8	480719	478171	0	0
T9	243513	243487	0	0
T10	887534	887445	0	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T2,T6,T7

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T2,T6,T7
1	1	Covered	T2,T6,T7

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T2,T6,T7

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T6,T7
1	1	Covered	T2,T6,T7

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T2,T6,T7
0	0	1	Covered	T2,T6,T7
0	0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T2,T6,T7
0	0	1	Covered	T2,T6,T7
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	1940842	0	0
DstReqKnown_A	33621663	33286694	0	0
SrcAckBusyChk_A	2147483647	2010	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1940842	0	0
T2	392455	471	0	0
T3	223637	0	0	0
T5	441618	0	0	0
T6	181830	1887	0	0
T7	319572	3204	0	0
T8	480719	7296	0	0
T9	243513	1991	0	0
T10	887534	0	0	0
T11	351152	3376	0	0
T12	474359	412	0	0
T13	0	1375	0	0
T14	0	862	0	0
T15	0	3413	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33621663	33286694	0	0
T1	1065	993	0	0
T2	32704	32646	0	0
T3	4808	4741	0	0
T4	62	5	0	0
T5	909	820	0	0
T6	74214	74116	0	0
T7	67991	67915	0	0
T8	12091	10955	0	0
T9	48701	46116	0	0
T10	6572	6522	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2010	0	0
T2	392455	1	0	0
T3	223637	0	0	0
T5	441618	0	0	0
T6	181830	2	0	0
T7	319572	2	0	0
T8	480719	5	0	0
T9	243513	1	0	0
T10	887534	0	0	0
T11	351152	2	0	0
T12	474359	3	0	0
T13	0	1	0	0
T14	0	3	0	0
T15	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	133309	133232	0	0
T2	392455	392447	0	0
T3	223637	223630	0	0
T4	30328	30259	0	0
T5	441618	441523	0	0
T6	181830	181829	0	0
T7	319572	319571	0	0
T8	480719	478171	0	0
T9	243513	243487	0	0
T10	887534	887445	0	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T2,T6,T7

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T2,T6,T7
1	1	Covered	T2,T6,T7

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T2,T6,T7

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T6,T7
1	1	Covered	T2,T6,T7

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T2,T6,T7
0	0	1	Covered	T2,T6,T7
0	0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T2,T6,T7
0	0	1	Covered	T2,T6,T7
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	1916968	0	0
DstReqKnown_A	33621663	33286694	0	0
SrcAckBusyChk_A	2147483647	1995	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1916968	0	0
T2	392455	469	0	0
T3	223637	0	0	0
T5	441618	0	0	0
T6	181830	1875	0	0
T7	319572	3197	0	0
T8	480719	7249	0	0
T9	243513	1989	0	0
T10	887534	0	0	0
T11	351152	3372	0	0
T12	474359	406	0	0
T13	0	1357	0	0
T14	0	832	0	0
T15	0	3396	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33621663	33286694	0	0
T1	1065	993	0	0
T2	32704	32646	0	0
T3	4808	4741	0	0
T4	62	5	0	0
T5	909	820	0	0
T6	74214	74116	0	0
T7	67991	67915	0	0
T8	12091	10955	0	0
T9	48701	46116	0	0
T10	6572	6522	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1995	0	0
T2	392455	1	0	0
T3	223637	0	0	0
T5	441618	0	0	0
T6	181830	2	0	0
T7	319572	2	0	0
T8	480719	5	0	0
T9	243513	1	0	0
T10	887534	0	0	0
T11	351152	2	0	0
T12	474359	3	0	0
T13	0	1	0	0
T14	0	3	0	0
T15	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	133309	133232	0	0
T2	392455	392447	0	0
T3	223637	223630	0	0
T4	30328	30259	0	0
T5	441618	441523	0	0
T6	181830	181829	0	0
T7	319572	319571	0	0
T8	480719	478171	0	0
T9	243513	243487	0	0
T10	887534	887445	0	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T2,T6,T7

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T2,T6,T7
1	1	Covered	T2,T6,T7

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T2,T6,T7

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T6,T7
1	1	Covered	T2,T6,T7

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T2,T6,T7
0	0	1	Covered	T2,T6,T7
0	0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T2,T6,T7
0	0	1	Covered	T2,T6,T7
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	1864099	0	0
DstReqKnown_A	33621663	33286694	0	0
SrcAckBusyChk_A	2147483647	1952	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1864099	0	0
T2	392455	467	0	0
T3	223637	0	0	0
T5	441618	0	0	0
T6	181830	1855	0	0
T7	319572	3185	0	0
T8	480719	7214	0	0
T9	243513	1987	0	0
T10	887534	0	0	0
T11	351152	3368	0	0
T12	474359	400	0	0
T13	0	1348	0	0
T14	0	802	0	0
T15	0	3380	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33621663	33286694	0	0
T1	1065	993	0	0
T2	32704	32646	0	0
T3	4808	4741	0	0
T4	62	5	0	0
T5	909	820	0	0
T6	74214	74116	0	0
T7	67991	67915	0	0
T8	12091	10955	0	0
T9	48701	46116	0	0
T10	6572	6522	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1952	0	0
T2	392455	1	0	0
T3	223637	0	0	0
T5	441618	0	0	0
T6	181830	2	0	0
T7	319572	2	0	0
T8	480719	5	0	0
T9	243513	1	0	0
T10	887534	0	0	0
T11	351152	2	0	0
T12	474359	3	0	0
T13	0	1	0	0
T14	0	3	0	0
T15	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	133309	133232	0	0
T2	392455	392447	0	0
T3	223637	223630	0	0
T4	30328	30259	0	0
T5	441618	441523	0	0
T6	181830	181829	0	0
T7	319572	319571	0	0
T8	480719	478171	0	0
T9	243513	243487	0	0
T10	887534	887445	0	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T2,T6,T7

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T2,T6,T7
1	1	Covered	T2,T6,T7

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T2,T6,T7

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T6,T7
1	1	Covered	T2,T6,T7

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T2,T6,T7
0	0	1	Covered	T2,T6,T7
0	0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T2,T6,T7
0	0	1	Covered	T2,T6,T7
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	1907323	0	0
DstReqKnown_A	33621663	33286694	0	0
SrcAckBusyChk_A	2147483647	1981	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1907323	0	0
T2	392455	465	0	0
T3	223637	0	0	0
T5	441618	0	0	0
T6	181830	1848	0	0
T7	319572	3175	0	0
T8	480719	7169	0	0
T9	243513	1985	0	0
T10	887534	0	0	0
T11	351152	3364	0	0
T12	474359	394	0	0
T13	0	1333	0	0
T14	0	777	0	0
T15	0	3362	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33621663	33286694	0	0
T1	1065	993	0	0
T2	32704	32646	0	0
T3	4808	4741	0	0
T4	62	5	0	0
T5	909	820	0	0
T6	74214	74116	0	0
T7	67991	67915	0	0
T8	12091	10955	0	0
T9	48701	46116	0	0
T10	6572	6522	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1981	0	0
T2	392455	1	0	0
T3	223637	0	0	0
T5	441618	0	0	0
T6	181830	2	0	0
T7	319572	2	0	0
T8	480719	5	0	0
T9	243513	1	0	0
T10	887534	0	0	0
T11	351152	2	0	0
T12	474359	3	0	0
T13	0	1	0	0
T14	0	3	0	0
T15	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	133309	133232	0	0
T2	392455	392447	0	0
T3	223637	223630	0	0
T4	30328	30259	0	0
T5	441618	441523	0	0
T6	181830	181829	0	0
T7	319572	319571	0	0
T8	480719	478171	0	0
T9	243513	243487	0	0
T10	887534	887445	0	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T2,T6,T7

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T2,T6,T7
1	1	Covered	T2,T6,T7

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T2,T6,T7

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T6,T7
1	1	Covered	T2,T6,T7

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T2,T6,T7
0	0	1	Covered	T2,T6,T7
0	0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T2,T6,T7
0	0	1	Covered	T2,T6,T7
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	1988545	0	0
DstReqKnown_A	33621663	33286694	0	0
SrcAckBusyChk_A	2147483647	2076	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1988545	0	0
T2	392455	463	0	0
T3	223637	0	0	0
T5	441618	0	0	0
T6	181830	1830	0	0
T7	319572	3165	0	0
T8	480719	7118	0	0
T9	243513	3980	0	0
T10	887534	0	0	0
T11	351152	3360	0	0
T12	474359	388	0	0
T13	0	1328	0	0
T14	0	863	0	0
T15	0	3342	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33621663	33286694	0	0
T1	1065	993	0	0
T2	32704	32646	0	0
T3	4808	4741	0	0
T4	62	5	0	0
T5	909	820	0	0
T6	74214	74116	0	0
T7	67991	67915	0	0
T8	12091	10955	0	0
T9	48701	46116	0	0
T10	6572	6522	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2076	0	0
T2	392455	1	0	0
T3	223637	0	0	0
T5	441618	0	0	0
T6	181830	2	0	0
T7	319572	2	0	0
T8	480719	5	0	0
T9	243513	2	0	0
T10	887534	0	0	0
T11	351152	2	0	0
T12	474359	3	0	0
T13	0	1	0	0
T14	0	3	0	0
T15	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	133309	133232	0	0
T2	392455	392447	0	0
T3	223637	223630	0	0
T4	30328	30259	0	0
T5	441618	441523	0	0
T6	181830	181829	0	0
T7	319572	319571	0	0
T8	480719	478171	0	0
T9	243513	243487	0	0
T10	887534	887445	0	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T2,T6,T7

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T2,T6,T7
1	1	Covered	T2,T6,T7

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T2,T6,T7

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T6,T7
1	1	Covered	T2,T6,T7

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T2,T6,T7
0	0	1	Covered	T2,T6,T7
0	0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T2,T6,T7
0	0	1	Covered	T2,T6,T7
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	1894590	0	0
DstReqKnown_A	33621663	33286694	0	0
SrcAckBusyChk_A	2147483647	1973	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1894590	0	0
T2	392455	461	0	0
T3	223637	0	0	0
T5	441618	0	0	0
T6	181830	1815	0	0
T7	319572	3147	0	0
T8	480719	7062	0	0
T9	243513	1981	0	0
T10	887534	0	0	0
T11	351152	3356	0	0
T12	474359	382	0	0
T13	0	1316	0	0
T14	0	832	0	0
T15	0	3327	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33621663	33286694	0	0
T1	1065	993	0	0
T2	32704	32646	0	0
T3	4808	4741	0	0
T4	62	5	0	0
T5	909	820	0	0
T6	74214	74116	0	0
T7	67991	67915	0	0
T8	12091	10955	0	0
T9	48701	46116	0	0
T10	6572	6522	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1973	0	0
T2	392455	1	0	0
T3	223637	0	0	0
T5	441618	0	0	0
T6	181830	2	0	0
T7	319572	2	0	0
T8	480719	5	0	0
T9	243513	1	0	0
T10	887534	0	0	0
T11	351152	2	0	0
T12	474359	3	0	0
T13	0	1	0	0
T14	0	3	0	0
T15	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	133309	133232	0	0
T2	392455	392447	0	0
T3	223637	223630	0	0
T4	30328	30259	0	0
T5	441618	441523	0	0
T6	181830	181829	0	0
T7	319572	319571	0	0
T8	480719	478171	0	0
T9	243513	243487	0	0
T10	887534	887445	0	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T2,T6,T7

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T2,T6,T7
1	1	Covered	T2,T6,T7

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T2,T6,T7

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T6,T7
1	1	Covered	T2,T6,T7

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T2,T6,T7
0	0	1	Covered	T2,T6,T7
0	0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T2,T6,T7
0	0	1	Covered	T2,T6,T7
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	1885090	0	0
DstReqKnown_A	33621663	33286694	0	0
SrcAckBusyChk_A	2147483647	1995	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1885090	0	0
T2	392455	459	0	0
T3	223637	0	0	0
T5	441618	0	0	0
T6	181830	1797	0	0
T7	319572	3136	0	0
T8	480719	7007	0	0
T9	243513	1979	0	0
T10	887534	0	0	0
T11	351152	3352	0	0
T12	474359	376	0	0
T13	0	1309	0	0
T14	0	801	0	0
T15	0	3318	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33621663	33286694	0	0
T1	1065	993	0	0
T2	32704	32646	0	0
T3	4808	4741	0	0
T4	62	5	0	0
T5	909	820	0	0
T6	74214	74116	0	0
T7	67991	67915	0	0
T8	12091	10955	0	0
T9	48701	46116	0	0
T10	6572	6522	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1995	0	0
T2	392455	1	0	0
T3	223637	0	0	0
T5	441618	0	0	0
T6	181830	2	0	0
T7	319572	2	0	0
T8	480719	5	0	0
T9	243513	1	0	0
T10	887534	0	0	0
T11	351152	2	0	0
T12	474359	3	0	0
T13	0	1	0	0
T14	0	3	0	0
T15	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	133309	133232	0	0
T2	392455	392447	0	0
T3	223637	223630	0	0
T4	30328	30259	0	0
T5	441618	441523	0	0
T6	181830	181829	0	0
T7	319572	319571	0	0
T8	480719	478171	0	0
T9	243513	243487	0	0
T10	887534	887445	0	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T2,T6,T7

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T2,T6,T7
1	1	Covered	T2,T6,T7

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T2,T6,T7

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T6,T7
1	1	Covered	T2,T6,T7

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T2,T6,T7
0	0	1	Covered	T2,T6,T7
0	0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T2,T6,T7
0	0	1	Covered	T2,T6,T7
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	1867634	0	0
DstReqKnown_A	33621663	33286694	0	0
SrcAckBusyChk_A	2147483647	1961	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1867634	0	0
T2	392455	457	0	0
T3	223637	0	0	0
T5	441618	0	0	0
T6	181830	1790	0	0
T7	319572	3124	0	0
T8	480719	6971	0	0
T9	243513	1977	0	0
T10	887534	0	0	0
T11	351152	3348	0	0
T12	474359	370	0	0
T13	0	1303	0	0
T14	0	989	0	0
T15	0	3312	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33621663	33286694	0	0
T1	1065	993	0	0
T2	32704	32646	0	0
T3	4808	4741	0	0
T4	62	5	0	0
T5	909	820	0	0
T6	74214	74116	0	0
T7	67991	67915	0	0
T8	12091	10955	0	0
T9	48701	46116	0	0
T10	6572	6522	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1961	0	0
T2	392455	1	0	0
T3	223637	0	0	0
T5	441618	0	0	0
T6	181830	2	0	0
T7	319572	2	0	0
T8	480719	5	0	0
T9	243513	1	0	0
T10	887534	0	0	0
T11	351152	2	0	0
T12	474359	3	0	0
T13	0	1	0	0
T14	0	3	0	0
T15	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	133309	133232	0	0
T2	392455	392447	0	0
T3	223637	223630	0	0
T4	30328	30259	0	0
T5	441618	441523	0	0
T6	181830	181829	0	0
T7	319572	319571	0	0
T8	480719	478171	0	0
T9	243513	243487	0	0
T10	887534	887445	0	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T2,T6,T7

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T2,T6,T7
1	1	Covered	T2,T6,T7

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T2,T6,T7

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T6,T7
1	1	Covered	T2,T6,T7

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T2,T6,T7
0	0	1	Covered	T2,T6,T7
0	0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T2,T6,T7
0	0	1	Covered	T2,T6,T7
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	1854745	0	0
DstReqKnown_A	33621663	33286694	0	0
SrcAckBusyChk_A	2147483647	1968	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1854745	0	0
T2	392455	455	0	0
T3	223637	0	0	0
T5	441618	0	0	0
T6	181830	1775	0	0
T7	319572	3116	0	0
T8	480719	6900	0	0
T9	243513	1975	0	0
T10	887534	0	0	0
T11	351152	3344	0	0
T12	474359	364	0	0
T13	0	1294	0	0
T14	0	948	0	0
T15	0	3293	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33621663	33286694	0	0
T1	1065	993	0	0
T2	32704	32646	0	0
T3	4808	4741	0	0
T4	62	5	0	0
T5	909	820	0	0
T6	74214	74116	0	0
T7	67991	67915	0	0
T8	12091	10955	0	0
T9	48701	46116	0	0
T10	6572	6522	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1968	0	0
T2	392455	1	0	0
T3	223637	0	0	0
T5	441618	0	0	0
T6	181830	2	0	0
T7	319572	2	0	0
T8	480719	5	0	0
T9	243513	1	0	0
T10	887534	0	0	0
T11	351152	2	0	0
T12	474359	3	0	0
T13	0	1	0	0
T14	0	3	0	0
T15	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	133309	133232	0	0
T2	392455	392447	0	0
T3	223637	223630	0	0
T4	30328	30259	0	0
T5	441618	441523	0	0
T6	181830	181829	0	0
T7	319572	319571	0	0
T8	480719	478171	0	0
T9	243513	243487	0	0
T10	887534	887445	0	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T2,T6,T7

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T2,T6,T7
1	1	Covered	T2,T6,T7

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T2,T6,T7

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T6,T7
1	1	Covered	T2,T6,T7

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T2,T6,T7
0	0	1	Covered	T2,T6,T7
0	0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T2,T6,T7
0	0	1	Covered	T2,T6,T7
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	1865032	0	0
DstReqKnown_A	33621663	33286694	0	0
SrcAckBusyChk_A	2147483647	1971	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1865032	0	0
T2	392455	453	0	0
T3	223637	0	0	0
T5	441618	0	0	0
T6	181830	1764	0	0
T7	319572	3100	0	0
T8	480719	6851	0	0
T9	243513	1973	0	0
T10	887534	0	0	0
T11	351152	3340	0	0
T12	474359	358	0	0
T13	0	1287	0	0
T14	0	921	0	0
T15	0	3278	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33621663	33286694	0	0
T1	1065	993	0	0
T2	32704	32646	0	0
T3	4808	4741	0	0
T4	62	5	0	0
T5	909	820	0	0
T6	74214	74116	0	0
T7	67991	67915	0	0
T8	12091	10955	0	0
T9	48701	46116	0	0
T10	6572	6522	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1971	0	0
T2	392455	1	0	0
T3	223637	0	0	0
T5	441618	0	0	0
T6	181830	2	0	0
T7	319572	2	0	0
T8	480719	5	0	0
T9	243513	1	0	0
T10	887534	0	0	0
T11	351152	2	0	0
T12	474359	3	0	0
T13	0	1	0	0
T14	0	3	0	0
T15	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	133309	133232	0	0
T2	392455	392447	0	0
T3	223637	223630	0	0
T4	30328	30259	0	0
T5	441618	441523	0	0
T6	181830	181829	0	0
T7	319572	319571	0	0
T8	480719	478171	0	0
T9	243513	243487	0	0
T10	887534	887445	0	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T2,T6,T7

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T2,T6,T7
1	1	Covered	T2,T6,T7

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T2,T6,T7

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T6,T7
1	1	Covered	T2,T6,T7

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T2,T6,T7
0	0	1	Covered	T2,T6,T7
0	0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T2,T6,T7
0	0	1	Covered	T2,T6,T7
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	1868055	0	0
DstReqKnown_A	33621663	33286694	0	0
SrcAckBusyChk_A	2147483647	1993	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1868055	0	0
T2	392455	451	0	0
T3	223637	0	0	0
T5	441618	0	0	0
T6	181830	1751	0	0
T7	319572	3095	0	0
T8	480719	6792	0	0
T9	243513	1971	0	0
T10	887534	0	0	0
T11	351152	3336	0	0
T12	474359	352	0	0
T13	0	1275	0	0
T14	0	891	0	0
T15	0	3268	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33621663	33286694	0	0
T1	1065	993	0	0
T2	32704	32646	0	0
T3	4808	4741	0	0
T4	62	5	0	0
T5	909	820	0	0
T6	74214	74116	0	0
T7	67991	67915	0	0
T8	12091	10955	0	0
T9	48701	46116	0	0
T10	6572	6522	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1993	0	0
T2	392455	1	0	0
T3	223637	0	0	0
T5	441618	0	0	0
T6	181830	2	0	0
T7	319572	2	0	0
T8	480719	5	0	0
T9	243513	1	0	0
T10	887534	0	0	0
T11	351152	2	0	0
T12	474359	3	0	0
T13	0	1	0	0
T14	0	3	0	0
T15	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	133309	133232	0	0
T2	392455	392447	0	0
T3	223637	223630	0	0
T4	30328	30259	0	0
T5	441618	441523	0	0
T6	181830	181829	0	0
T7	319572	319571	0	0
T8	480719	478171	0	0
T9	243513	243487	0	0
T10	887534	887445	0	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T2,T6,T7

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T2,T6,T7
1	1	Covered	T2,T6,T7

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T2,T6,T7

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T6,T7
1	1	Covered	T2,T6,T7

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T2,T6,T7
0	0	1	Covered	T2,T6,T7
0	0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T2,T6,T7
0	0	1	Covered	T2,T6,T7
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	1853937	0	0
DstReqKnown_A	33621663	33286694	0	0
SrcAckBusyChk_A	2147483647	1968	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1853937	0	0
T2	392455	449	0	0
T3	223637	0	0	0
T5	441618	0	0	0
T6	181830	1740	0	0
T7	319572	3080	0	0
T8	480719	6759	0	0
T9	243513	1969	0	0
T10	887534	0	0	0
T11	351152	3332	0	0
T12	474359	346	0	0
T13	0	1258	0	0
T14	0	862	0	0
T15	0	3250	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33621663	33286694	0	0
T1	1065	993	0	0
T2	32704	32646	0	0
T3	4808	4741	0	0
T4	62	5	0	0
T5	909	820	0	0
T6	74214	74116	0	0
T7	67991	67915	0	0
T8	12091	10955	0	0
T9	48701	46116	0	0
T10	6572	6522	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1968	0	0
T2	392455	1	0	0
T3	223637	0	0	0
T5	441618	0	0	0
T6	181830	2	0	0
T7	319572	2	0	0
T8	480719	5	0	0
T9	243513	1	0	0
T10	887534	0	0	0
T11	351152	2	0	0
T12	474359	3	0	0
T13	0	1	0	0
T14	0	3	0	0
T15	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	133309	133232	0	0
T2	392455	392447	0	0
T3	223637	223630	0	0
T4	30328	30259	0	0
T5	441618	441523	0	0
T6	181830	181829	0	0
T7	319572	319571	0	0
T8	480719	478171	0	0
T9	243513	243487	0	0
T10	887534	887445	0	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_wakeup_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_adc_wakeup_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T6,T8,T11

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T6,T8,T11
1	1	Covered	T6,T8,T11

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T6,T8,T11

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T8,T11
1	1	Covered	T6,T8,T11

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_adc_wakeup_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T6,T8,T11
0	0	1	Covered	T6,T8,T11
0	0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T6,T8,T11
0	0	1	Covered	T6,T8,T11
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_adc_wakeup_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	1401625	0	0
DstReqKnown_A	33621663	33286694	0	0
SrcAckBusyChk_A	2147483647	1485	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1401625	0	0
T6	181830	1675	0	0
T7	319572	0	0	0
T8	480719	3621	0	0
T9	243513	0	0	0
T10	887534	0	0	0
T11	351152	3316	0	0
T12	474359	442	0	0
T13	158997	0	0	0
T14	113622	0	0	0
T15	321604	3177	0	0
T26	0	842	0	0
T45	0	1266	0	0
T46	0	455	0	0
T47	0	3777	0	0
T48	0	1191	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33621663	33286694	0	0
T1	1065	993	0	0
T2	32704	32646	0	0
T3	4808	4741	0	0
T4	62	5	0	0
T5	909	820	0	0
T6	74214	74116	0	0
T7	67991	67915	0	0
T8	12091	10955	0	0
T9	48701	46116	0	0
T10	6572	6522	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1485	0	0
T6	181830	2	0	0
T7	319572	0	0	0
T8	480719	3	0	0
T9	243513	0	0	0
T10	887534	0	0	0
T11	351152	2	0	0
T12	474359	3	0	0
T13	158997	0	0	0
T14	113622	0	0	0
T15	321604	2	0	0
T26	0	2	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	3	0	0
T48	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	133309	133232	0	0
T2	392455	392447	0	0
T3	223637	223630	0	0
T4	30328	30259	0	0
T5	441618	441523	0	0
T6	181830	181829	0	0
T7	319572	319571	0	0
T8	480719	478171	0	0
T9	243513	243487	0	0
T10	887534	887445	0	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_fsm_rst_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_adc_fsm_rst_cdc

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T2,T6,T7

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T2,T6,T7
1	1	Covered	T2,T6,T7

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T2,T6,T7
1	-	Covered	T2,T6,T7

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T2,T6,T7

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T6,T7
1	1	Covered	T2,T6,T7

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_adc_fsm_rst_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T2,T6,T7
0	0	1	Covered	T2,T6,T7
0	0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T2,T6,T7
0	0	1	Covered	T2,T6,T7
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_adc_fsm_rst_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	16832129	0	0
DstReqKnown_A	33621663	33286694	0	0
SrcAckBusyChk_A	2147483647	18905	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	16832129	0	0
T2	392455	841	0	0
T3	223637	0	0	0
T5	441618	0	0	0
T6	181830	3405	0	0
T7	319572	6557	0	0
T8	480719	0	0	0
T9	243513	305527	0	0
T10	887534	0	0	0
T11	351152	6792	0	0
T12	474359	884	0	0
T13	0	3346	0	0
T14	0	2258	0	0
T15	0	7477	0	0
T26	0	1728	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	33621663	33286694	0	0
T1	1065	993	0	0
T2	32704	32646	0	0
T3	4808	4741	0	0
T4	62	5	0	0
T5	909	820	0	0
T6	74214	74116	0	0
T7	67991	67915	0	0
T8	12091	10955	0	0
T9	48701	46116	0	0
T10	6572	6522	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	18905	0	0
T2	392455	2	0	0
T3	223637	0	0	0
T5	441618	0	0	0
T6	181830	4	0	0
T7	319572	4	0	0
T8	480719	0	0	0
T9	243513	174	0	0
T10	887534	0	0	0
T11	351152	4	0	0
T12	474359	6	0	0
T13	0	2	0	0
T14	0	6	0	0
T15	0	4	0	0
T26	0	4	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	133309	133232	0	0
T2	392455	392447	0	0
T3	223637	223630	0	0
T4	30328	30259	0	0
T5	441618	441523	0	0
T6	181830	181829	0	0
T7	319572	319571	0	0
T8	480719	478171	0	0
T9	243513	243487	0	0
T10	887534	887445	0	0