Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	96.00						96.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	24	96.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	24	96.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	0	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	1986	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	1833	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	1673	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	1864	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	1875	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	1988	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	1684	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	1799	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	1834	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	1733	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	1707	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	1948	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	1724	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	1791	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	1774	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	1740	0	0
adc_en_ctl_rd_A	2147483647	1456	0	0
adc_fsm_rst_rd_A	2147483647	1216	0	0
adc_intr_ctl_rd_A	2147483647	1597	0	0
adc_lp_sample_ctl_rd_A	2147483647	1216	0	0
adc_pd_ctl_rd_A	2147483647	1516	0	0
adc_sample_ctl_rd_A	2147483647	1196	0	0
adc_wakeup_ctl_rd_A	2147483647	1398	0	0
intr_enable_rd_A	2147483647	1659	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1986	0	0
T8	480719	28	0	0
T9	243513	0	0	0
T10	887534	0	0	0
T11	351152	0	0	0
T12	474359	0	0	0
T13	158997	0	0	0
T14	113622	0	0	0
T15	321604	0	0	0
T16	0	28	0	0
T17	0	38	0	0
T18	0	20	0	0
T19	0	16	0	0
T20	0	43	0	0
T21	0	2	0	0
T22	0	4	0	0
T23	0	23	0	0
T24	0	28	0	0
T25	4044	0	0	0
T26	931336	0	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1833	0	0
T8	480719	21	0	0
T9	243513	0	0	0
T10	887534	0	0	0
T11	351152	0	0	0
T12	474359	0	0	0
T13	158997	0	0	0
T14	113622	0	0	0
T15	321604	0	0	0
T16	0	21	0	0
T17	0	26	0	0
T18	0	25	0	0
T19	0	28	0	0
T20	0	29	0	0
T21	0	20	0	0
T22	0	9	0	0
T23	0	19	0	0
T24	0	23	0	0
T25	4044	0	0	0
T26	931336	0	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1673	0	0
T8	480719	14	0	0
T9	243513	0	0	0
T10	887534	0	0	0
T11	351152	0	0	0
T12	474359	0	0	0
T13	158997	0	0	0
T14	113622	0	0	0
T15	321604	0	0	0
T16	0	14	0	0
T17	0	31	0	0
T18	0	9	0	0
T19	0	18	0	0
T20	0	50	0	0
T21	0	6	0	0
T22	0	4	0	0
T23	0	20	0	0
T24	0	13	0	0
T25	4044	0	0	0
T26	931336	0	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1864	0	0
T8	480719	17	0	0
T9	243513	0	0	0
T10	887534	0	0	0
T11	351152	0	0	0
T12	474359	0	0	0
T13	158997	0	0	0
T14	113622	0	0	0
T15	321604	0	0	0
T16	0	23	0	0
T17	0	27	0	0
T18	0	17	0	0
T19	0	26	0	0
T20	0	14	0	0
T21	0	6	0	0
T22	0	5	0	0
T23	0	38	0	0
T24	0	20	0	0
T25	4044	0	0	0
T26	931336	0	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1875	0	0
T8	480719	21	0	0
T9	243513	0	0	0
T10	887534	0	0	0
T11	351152	0	0	0
T12	474359	0	0	0
T13	158997	0	0	0
T14	113622	0	0	0
T15	321604	0	0	0
T16	0	24	0	0
T17	0	37	0	0
T18	0	17	0	0
T19	0	18	0	0
T20	0	44	0	0
T21	0	13	0	0
T22	0	9	0	0
T23	0	35	0	0
T24	0	19	0	0
T25	4044	0	0	0
T26	931336	0	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1988	0	0
T16	412654	18	0	0
T17	0	49	0	0
T18	0	21	0	0
T19	0	11	0	0
T20	0	51	0	0
T21	0	21	0	0
T22	0	8	0	0
T23	0	25	0	0
T24	0	16	0	0
T27	0	12	0	0
T28	289582	0	0	0
T29	146260	0	0	0
T30	217378	0	0	0
T31	232471	0	0	0
T32	407142	0	0	0
T33	320930	0	0	0
T34	107401	0	0	0
T35	372964	0	0	0
T36	135853	0	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1684	0	0
T8	480719	20	0	0
T9	243513	0	0	0
T10	887534	0	0	0
T11	351152	0	0	0
T12	474359	0	0	0
T13	158997	0	0	0
T14	113622	0	0	0
T15	321604	0	0	0
T16	0	10	0	0
T17	0	38	0	0
T18	0	27	0	0
T19	0	13	0	0
T20	0	74	0	0
T22	0	1	0	0
T23	0	18	0	0
T24	0	18	0	0
T25	4044	0	0	0
T26	931336	0	0	0
T27	0	14	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1799	0	0
T8	480719	15	0	0
T9	243513	0	0	0
T10	887534	0	0	0
T11	351152	0	0	0
T12	474359	0	0	0
T13	158997	0	0	0
T14	113622	0	0	0
T15	321604	0	0	0
T16	0	6	0	0
T17	0	47	0	0
T18	0	23	0	0
T19	0	7	0	0
T20	0	33	0	0
T21	0	17	0	0
T22	0	7	0	0
T23	0	21	0	0
T24	0	20	0	0
T25	4044	0	0	0
T26	931336	0	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1834	0	0
T8	480719	27	0	0
T9	243513	0	0	0
T10	887534	0	0	0
T11	351152	0	0	0
T12	474359	0	0	0
T13	158997	0	0	0
T14	113622	0	0	0
T15	321604	0	0	0
T16	0	16	0	0
T17	0	45	0	0
T18	0	25	0	0
T19	0	34	0	0
T20	0	36	0	0
T21	0	13	0	0
T22	0	2	0	0
T23	0	7	0	0
T24	0	19	0	0
T25	4044	0	0	0
T26	931336	0	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1733	0	0
T8	480719	46	0	0
T9	243513	0	0	0
T10	887534	0	0	0
T11	351152	0	0	0
T12	474359	0	0	0
T13	158997	0	0	0
T14	113622	0	0	0
T15	321604	0	0	0
T16	0	26	0	0
T17	0	47	0	0
T18	0	18	0	0
T19	0	12	0	0
T20	0	50	0	0
T21	0	8	0	0
T22	0	1	0	0
T23	0	14	0	0
T24	0	19	0	0
T25	4044	0	0	0
T26	931336	0	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1707	0	0
T8	480719	25	0	0
T9	243513	0	0	0
T10	887534	0	0	0
T11	351152	0	0	0
T12	474359	0	0	0
T13	158997	0	0	0
T14	113622	0	0	0
T15	321604	0	0	0
T16	0	3	0	0
T17	0	32	0	0
T18	0	22	0	0
T19	0	12	0	0
T20	0	40	0	0
T21	0	5	0	0
T22	0	9	0	0
T23	0	11	0	0
T24	0	15	0	0
T25	4044	0	0	0
T26	931336	0	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1948	0	0
T8	480719	20	0	0
T9	243513	0	0	0
T10	887534	0	0	0
T11	351152	0	0	0
T12	474359	0	0	0
T13	158997	0	0	0
T14	113622	0	0	0
T15	321604	0	0	0
T16	0	29	0	0
T17	0	35	0	0
T18	0	14	0	0
T19	0	23	0	0
T20	0	35	0	0
T21	0	18	0	0
T22	0	7	0	0
T23	0	23	0	0
T24	0	14	0	0
T25	4044	0	0	0
T26	931336	0	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1724	0	0
T8	480719	16	0	0
T9	243513	0	0	0
T10	887534	0	0	0
T11	351152	0	0	0
T12	474359	0	0	0
T13	158997	0	0	0
T14	113622	0	0	0
T15	321604	0	0	0
T16	0	19	0	0
T17	0	20	0	0
T18	0	26	0	0
T19	0	13	0	0
T20	0	26	0	0
T21	0	13	0	0
T22	0	14	0	0
T23	0	13	0	0
T24	0	33	0	0
T25	4044	0	0	0
T26	931336	0	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1791	0	0
T8	480719	21	0	0
T9	243513	0	0	0
T10	887534	0	0	0
T11	351152	0	0	0
T12	474359	0	0	0
T13	158997	0	0	0
T14	113622	0	0	0
T15	321604	0	0	0
T16	0	9	0	0
T17	0	47	0	0
T18	0	14	0	0
T19	0	13	0	0
T20	0	31	0	0
T21	0	3	0	0
T22	0	5	0	0
T23	0	10	0	0
T24	0	12	0	0
T25	4044	0	0	0
T26	931336	0	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1774	0	0
T8	480719	19	0	0
T9	243513	0	0	0
T10	887534	0	0	0
T11	351152	0	0	0
T12	474359	0	0	0
T13	158997	0	0	0
T14	113622	0	0	0
T15	321604	0	0	0
T16	0	8	0	0
T17	0	36	0	0
T18	0	28	0	0
T19	0	18	0	0
T20	0	44	0	0
T21	0	12	0	0
T22	0	22	0	0
T23	0	20	0	0
T24	0	21	0	0
T25	4044	0	0	0
T26	931336	0	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1740	0	0
T8	480719	25	0	0
T9	243513	0	0	0
T10	887534	0	0	0
T11	351152	0	0	0
T12	474359	0	0	0
T13	158997	0	0	0
T14	113622	0	0	0
T15	321604	0	0	0
T16	0	11	0	0
T17	0	25	0	0
T18	0	12	0	0
T19	0	12	0	0
T20	0	38	0	0
T21	0	7	0	0
T22	0	12	0	0
T23	0	27	0	0
T24	0	11	0	0
T25	4044	0	0	0
T26	931336	0	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1456	0	0
T8	480719	34	0	0
T9	243513	0	0	0
T10	887534	0	0	0
T11	351152	0	0	0
T12	474359	0	0	0
T13	158997	0	0	0
T14	113622	0	0	0
T15	321604	0	0	0
T16	0	12	0	0
T17	0	38	0	0
T18	0	19	0	0
T19	0	24	0	0
T20	0	29	0	0
T21	0	16	0	0
T22	0	10	0	0
T23	0	34	0	0
T24	0	21	0	0
T25	4044	0	0	0
T26	931336	0	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1216	0	0
T8	480719	18	0	0
T9	243513	0	0	0
T10	887534	0	0	0
T11	351152	0	0	0
T12	474359	0	0	0
T13	158997	0	0	0
T14	113622	0	0	0
T15	321604	0	0	0
T16	0	13	0	0
T17	0	41	0	0
T18	0	12	0	0
T19	0	26	0	0
T20	0	40	0	0
T21	0	13	0	0
T22	0	8	0	0
T23	0	15	0	0
T24	0	31	0	0
T25	4044	0	0	0
T26	931336	0	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1597	0	0
T8	480719	12	0	0
T9	243513	0	0	0
T10	887534	0	0	0
T11	351152	0	0	0
T12	474359	0	0	0
T13	158997	0	0	0
T14	113622	0	0	0
T15	321604	0	0	0
T16	0	12	0	0
T17	0	46	0	0
T18	0	27	0	0
T19	0	14	0	0
T20	0	38	0	0
T21	0	2	0	0
T22	0	6	0	0
T23	0	26	0	0
T24	0	25	0	0
T25	4044	0	0	0
T26	931336	0	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1216	0	0
T8	480719	32	0	0
T9	243513	0	0	0
T10	887534	0	0	0
T11	351152	0	0	0
T12	474359	0	0	0
T13	158997	0	0	0
T14	113622	0	0	0
T15	321604	0	0	0
T16	0	18	0	0
T17	0	26	0	0
T18	0	19	0	0
T19	0	20	0	0
T20	0	43	0	0
T21	0	3	0	0
T22	0	13	0	0
T23	0	26	0	0
T24	0	20	0	0
T25	4044	0	0	0
T26	931336	0	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1516	0	0
T8	480719	20	0	0
T9	243513	0	0	0
T10	887534	0	0	0
T11	351152	0	0	0
T12	474359	0	0	0
T13	158997	0	0	0
T14	113622	0	0	0
T15	321604	0	0	0
T16	0	18	0	0
T17	0	40	0	0
T18	0	24	0	0
T19	0	11	0	0
T20	0	38	0	0
T21	0	14	0	0
T22	0	10	0	0
T23	0	12	0	0
T24	0	23	0	0
T25	4044	0	0	0
T26	931336	0	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1196	0	0
T8	480719	18	0	0
T9	243513	0	0	0
T10	887534	0	0	0
T11	351152	0	0	0
T12	474359	0	0	0
T13	158997	0	0	0
T14	113622	0	0	0
T15	321604	0	0	0
T16	0	38	0	0
T17	0	33	0	0
T18	0	19	0	0
T19	0	22	0	0
T20	0	41	0	0
T21	0	20	0	0
T22	0	9	0	0
T23	0	23	0	0
T24	0	16	0	0
T25	4044	0	0	0
T26	931336	0	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1398	0	0
T8	480719	19	0	0
T9	243513	0	0	0
T10	887534	0	0	0
T11	351152	0	0	0
T12	474359	0	0	0
T13	158997	0	0	0
T14	113622	0	0	0
T15	321604	0	0	0
T16	0	15	0	0
T17	0	38	0	0
T18	0	20	0	0
T19	0	25	0	0
T20	0	34	0	0
T21	0	15	0	0
T22	0	7	0	0
T23	0	27	0	0
T24	0	16	0	0
T25	4044	0	0	0
T26	931336	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1659	0	0
T8	480719	21	0	0
T9	243513	0	0	0
T10	887534	0	0	0
T11	351152	0	0	0
T12	474359	0	0	0
T13	158997	0	0	0
T14	113622	0	0	0
T15	321604	0	0	0
T16	0	15	0	0
T17	0	51	0	0
T18	0	16	0	0
T19	0	25	0	0
T20	0	64	0	0
T21	0	7	0	0
T25	4044	0	0	0
T26	931336	0	0	0
T37	0	17	0	0
T38	0	9	0	0
T39	0	15	0	0