Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1255156	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1225993

1

T1

404

T4

5

T2

921

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2169519	1			T1	19		T4	1		T2	1693
values[0x0]	155285	1			T1	467		T4	10		T2	92
values[0x1]	156345	1			T1	542		T4	8		T2	89

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1005198	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1475951

1

T1

506

T4

7

T2

1106

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	16164	1			T1	2		T2	2		T5	3
valid_sources[0x01]	11836	1			T1	7		T2	10		T5	22
valid_sources[0x02]	7751	1			T1	10		T2	8		T5	32
valid_sources[0x03]	11467	1			T1	5		T2	5		T5	18
valid_sources[0x04]	8545	1			T1	3		T2	5		T5	56
valid_sources[0x05]	13994	1			T1	8		T2	3		T5	14
valid_sources[0x06]	12616	1			T1	7		T5	18		T6	17
valid_sources[0x07]	9622	1			T1	4		T4	1		T2	7
valid_sources[0x08]	21126	1			T1	3		T2	5		T5	71
valid_sources[0x09]	11460	1			T1	4		T2	2		T5	17
valid_sources[0x0a]	6939	1			T1	3		T2	8		T5	37
valid_sources[0x0b]	10416	1			T1	2		T2	8		T3	144
valid_sources[0x0c]	8850	1			T1	3		T2	6		T5	11
valid_sources[0x0d]	7261	1			T1	6		T2	13		T5	13
valid_sources[0x0e]	13218	1			T1	3		T2	10		T5	7
valid_sources[0x0f]	11655	1			T1	4		T2	1		T5	18
valid_sources[0x10]	7438	1			T1	8		T2	8		T5	21
valid_sources[0x11]	11655	1			T1	4		T2	13		T5	6
valid_sources[0x12]	7167	1			T1	4		T2	13		T5	18
valid_sources[0x13]	11438	1			T1	2		T5	46		T6	10
valid_sources[0x14]	7243	1			T1	6		T2	3		T5	6
valid_sources[0x15]	11164	1			T1	2		T2	11		T5	25
valid_sources[0x16]	8930	1			T1	2		T2	7		T5	14
valid_sources[0x17]	7711	1			T2	2		T5	33		T6	5
valid_sources[0x18]	8524	1			T1	1		T2	3		T5	19
valid_sources[0x19]	8032	1			T1	3		T2	10		T5	22
valid_sources[0x1a]	7452	1			T1	2		T5	34		T6	2
valid_sources[0x1b]	7488	1			T1	6		T5	27		T6	2
valid_sources[0x1c]	9035	1			T1	6		T2	7		T5	45
valid_sources[0x1d]	12204	1			T1	4		T2	2		T5	29
valid_sources[0x1e]	8104	1			T1	2		T2	7		T5	10
valid_sources[0x1f]	7636	1			T1	7		T2	1		T5	12
valid_sources[0x20]	7264	1			T1	5		T2	7		T5	19
valid_sources[0x21]	11825	1			T1	3		T2	6		T5	12
valid_sources[0x22]	11780	1			T1	4		T2	6		T5	8
valid_sources[0x23]	8908	1			T1	8		T2	6		T5	7
valid_sources[0x24]	7332	1			T1	7		T2	19		T5	19
valid_sources[0x25]	18515	1			T1	5		T2	10		T5	19
valid_sources[0x26]	11430	1			T1	3		T2	6		T5	19
valid_sources[0x27]	6971	1			T1	2		T2	4		T5	11
valid_sources[0x28]	7162	1			T1	8		T2	4		T5	12
valid_sources[0x29]	8182	1			T1	5		T2	8		T5	80
valid_sources[0x2a]	8306	1			T1	3		T2	1		T5	31
valid_sources[0x2b]	7272	1			T1	10		T4	1		T2	1
valid_sources[0x2c]	7745	1			T2	7		T5	10		T6	3
valid_sources[0x2d]	11703	1			T1	4		T2	5		T5	5
valid_sources[0x2e]	7472	1			T1	6		T5	9		T6	5
valid_sources[0x2f]	8209	1			T1	3		T2	8		T5	13
valid_sources[0x30]	8331	1			T1	2		T2	13		T5	8
valid_sources[0x31]	13615	1			T1	4		T2	2		T5	24
valid_sources[0x32]	7895	1			T1	5		T2	10		T5	55
valid_sources[0x33]	7713	1			T1	3		T2	2		T5	16
valid_sources[0x34]	8278	1			T1	6		T5	9		T6	15
valid_sources[0x35]	7135	1			T1	4		T2	9		T5	15
valid_sources[0x36]	7011	1			T1	6		T2	7		T5	16
valid_sources[0x37]	6867	1			T2	3		T5	31		T6	11
valid_sources[0x38]	21109	1			T1	6		T2	5		T5	50
valid_sources[0x39]	7166	1			T1	2		T2	15		T5	15
valid_sources[0x3a]	10002	1			T1	3		T2	5		T5	29
valid_sources[0x3b]	7454	1			T1	3		T2	6		T5	13
valid_sources[0x3c]	13814	1			T1	3		T2	6		T5	11
valid_sources[0x3d]	7588	1			T1	8		T2	6		T5	11
valid_sources[0x3e]	10454	1			T1	4		T2	5		T5	41
valid_sources[0x3f]	7077	1			T1	3		T2	1		T5	9
valid_sources[0x40]	10339	1			T1	3		T2	9		T5	16
valid_sources[0x41]	9042	1			T1	5		T2	5		T5	17
valid_sources[0x42]	7406	1			T1	5		T2	1		T5	19
valid_sources[0x43]	9272	1			T1	2		T2	3		T5	55
valid_sources[0x44]	7465	1			T1	4		T2	10		T5	11
valid_sources[0x45]	8699	1			T1	3		T2	11		T5	22
valid_sources[0x46]	8302	1			T1	2		T2	7		T5	25
valid_sources[0x47]	12534	1			T1	7		T2	3		T5	5
valid_sources[0x48]	7528	1			T1	6		T2	14		T5	17
valid_sources[0x49]	11726	1			T1	2		T2	8		T5	23
valid_sources[0x4a]	7182	1			T1	1		T2	5		T5	28
valid_sources[0x4b]	7154	1			T1	4		T2	7		T5	7
valid_sources[0x4c]	8033	1			T1	3		T2	10		T5	13
valid_sources[0x4d]	8946	1			T2	1		T5	52		T6	10
valid_sources[0x4e]	7140	1			T1	6		T2	11		T5	21
valid_sources[0x4f]	9928	1			T1	3		T2	15		T5	49
valid_sources[0x50]	7038	1			T1	5		T2	11		T5	20
valid_sources[0x51]	7411	1			T1	2		T2	4		T5	8
valid_sources[0x52]	8012	1			T1	5		T2	10		T5	17
valid_sources[0x53]	7030	1			T1	5		T2	14		T5	8
valid_sources[0x54]	8333	1			T1	4		T2	10		T5	10
valid_sources[0x55]	7368	1			T1	3		T2	6		T5	5
valid_sources[0x56]	7572	1			T1	2		T2	1		T5	25
valid_sources[0x57]	8824	1			T1	3		T2	2		T5	9
valid_sources[0x58]	7075	1			T2	7		T5	11		T6	13
valid_sources[0x59]	7792	1			T1	4		T2	6		T5	8
valid_sources[0x5a]	8570	1			T1	1		T2	10		T5	14
valid_sources[0x5b]	7722	1			T1	1		T2	4		T5	55
valid_sources[0x5c]	11139	1			T1	4		T2	8		T5	17
valid_sources[0x5d]	7963	1			T1	3		T2	13		T5	9
valid_sources[0x5e]	14502	1			T1	5		T2	6		T5	10
valid_sources[0x5f]	7375	1			T1	3		T2	11		T5	21
valid_sources[0x60]	13173	1			T1	2		T2	8		T5	20
valid_sources[0x61]	10907	1			T1	1		T2	11		T5	10
valid_sources[0x62]	7241	1			T1	7		T2	6		T5	17
valid_sources[0x63]	9106	1			T1	5		T2	22		T5	19
valid_sources[0x64]	9191	1			T1	2		T2	4		T5	31
valid_sources[0x65]	7121	1			T1	3		T2	3		T5	11
valid_sources[0x66]	7365	1			T1	3		T2	6		T5	19
valid_sources[0x67]	7401	1			T1	7		T2	3		T5	38
valid_sources[0x68]	13041	1			T1	6		T2	8		T5	20
valid_sources[0x69]	6887	1			T1	2		T5	7		T6	5
valid_sources[0x6a]	7743	1			T1	2		T2	13		T5	10
valid_sources[0x6b]	7620	1			T1	1		T2	11		T5	14
valid_sources[0x6c]	13683	1			T1	7		T4	1		T2	6
valid_sources[0x6d]	7574	1			T1	4		T2	6		T5	16
valid_sources[0x6e]	10643	1			T1	8		T2	6		T5	18
valid_sources[0x6f]	11479	1			T1	1		T2	19		T5	10
valid_sources[0x70]	11671	1			T1	3		T2	2		T5	18
valid_sources[0x71]	7709	1			T1	4		T2	4		T5	17
valid_sources[0x72]	7601	1			T1	4		T2	5		T5	53
valid_sources[0x73]	20674	1			T1	9		T2	15		T5	3
valid_sources[0x74]	12395	1			T1	1		T2	1		T5	18
valid_sources[0x75]	15878	1			T1	10		T2	6		T5	82
valid_sources[0x76]	7546	1			T1	1		T4	1		T2	8
valid_sources[0x77]	7657	1			T1	7		T2	2		T5	8
valid_sources[0x78]	12282	1			T1	2		T2	4		T5	18
valid_sources[0x79]	7704	1			T1	2		T4	1		T2	4
valid_sources[0x7a]	7369	1			T1	2		T2	5		T5	20
valid_sources[0x7b]	8995	1			T1	5		T2	3		T5	16
valid_sources[0x7c]	12116	1			T1	2		T2	14		T5	13
valid_sources[0x7d]	7362	1			T1	4		T2	5		T5	15
valid_sources[0x7e]	7221	1			T2	12		T5	18		T6	10
valid_sources[0x7f]	8328	1			T1	4		T2	12		T5	15
valid_sources[0x80]	9955	1			T1	4		T4	1		T2	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1079857

1

T1

10

T4

1

T2

828

values[0x0]

all_enables

biggest_size

84731

1

T1

204

T4

3

T2

56

values[0x1]

all_enables

biggest_size

61405

1

T1

190

T4

1

T2

37