Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
86.67	86.67	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	86.67	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
86.67	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	6	39	86.67

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	5	11	68.75	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	30185	1			T1	227		T2	15		T5	15
auto[PWRUP]	117	1			T36	1		T50	1		T26	2
auto[ONEST_0]	70	1			T1	1		T50	1		T173	2
auto[ONEST_021]	24	1			T40	1		T50	1		T165	1
auto[ONEST_1]	77	1			T1	1		T36	2		T40	1
auto[ONEST_DONE]	5	1			T208	1		T209	1		T205	1
auto[LP_0]	129	1			T1	1		T36	1		T40	2
auto[LP_021]	26	1			T50	1		T26	1		T173	1
auto[LP_1]	151	1			T1	2		T36	2		T50	1
auto[LP_EVAL]	60	1			T36	1		T50	1		T26	2
auto[LP_SLP]	508	1			T1	10		T36	10		T13	1
auto[LP_PWRUP]	27	1			T36	1		T26	2		T210	2
auto[NP_0]	187	1			T1	1		T36	5		T26	2
auto[NP_021]	44	1			T36	1		T32	1		T211	1
auto[NP_1]	143	1			T1	1		T36	4		T40	1
auto[NP_EVAL]	39	1			T1	1		T36	2		T26	3

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

5

1

T212

1

T213

1

T214

1

min

29604

1

T1

222

T2

15

T5

15

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	29612	1			T1	222		T2	15		T5	15
pow[0x1]	4	1			T210	1		T215	1		T216	1
pow[0x2]	20	1			T36	2		T26	2		T173	1
pow[0x3]	43	1			T1	1		T36	2		T40	2
pow[0x4]	58	1			T36	1		T50	1		T26	1
pow[0x5]	122	1			T1	4		T36	1		T40	2
pow[0x6]	285	1			T1	2		T36	5		T40	7
pow[0x7]	550	1			T1	7		T36	5		T13	2

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

214

1

T1

3

T36

3

T13

1

min

29128

1

T1

213

T2

15

T5

15

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	5	11	68.75

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x2]	0	1	1
pow[0x3]	0	1	1
pow[0x4]	0	1	1
pow[0x5]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	29128	1			T1	213		T2	15		T5	15
pow[0x6]	2	1			T50	1		T217	1		-	-
pow[0x7]	2	1			T218	1		T219	1		-	-
pow[0x8]	4	1			T173	2		T216	1		T220	1
pow[0x9]	10	1			T221	1		T195	1		T222	1
pow[0xa]	9	1			T210	1		T51	1		T221	1
pow[0xb]	39	1			T36	1		T50	1		T173	1
pow[0xc]	79	1			T1	3		T36	2		T40	2
pow[0xd]	164	1			T1	4		T36	3		T40	2
pow[0xe]	313	1			T1	3		T36	4		T40	1
pow[0xf]	608	1			T1	7		T36	14		T40	6