Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.56	95.56	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	95.56	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.56	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	2	43	95.56

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	1	15	93.75	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2448	1			T1	14		T36	17		T13	16
auto[PWRUP]	144	1			T1	2		T36	2		T40	3
auto[ONEST_0]	88	1			T1	2		T16	1		T37	1
auto[ONEST_021]	22	1			T37	1		T195	1		T323	1
auto[ONEST_1]	92	1			T36	1		T40	1		T50	1
auto[ONEST_DONE]	7	1			T162	1		T324	2		T301	1
auto[LP_0]	127	1			T1	4		T36	1		T40	1
auto[LP_021]	35	1			T1	1		T50	1		T26	2
auto[LP_1]	154	1			T36	3		T40	3		T50	1
auto[LP_EVAL]	61	1			T1	1		T36	1		T40	1
auto[LP_SLP]	549	1			T1	9		T36	6		T13	2
auto[LP_PWRUP]	30	1			T26	1		T37	1		T173	1
auto[NP_0]	245	1			T1	2		T36	2		T13	5
auto[NP_021]	56	1			T36	1		T40	1		T32	1
auto[NP_1]	247	1			T1	1		T36	7		T13	1
auto[NP_EVAL]	29	1			T13	1		T50	1		T26	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

9

1

T50

1

T211

1

T195

1

min

2049

1

T1

13

T36

8

T13

21

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	2068	1			T1	13		T36	8		T13	22
pow[0x1]	11	1			T221	1		T20	1		T24	1
pow[0x2]	23	1			T1	1		T26	2		T37	1
pow[0x3]	48	1			T36	1		T26	1		T325	2
pow[0x4]	85	1			T1	1		T50	1		T173	2
pow[0x5]	132	1			T1	1		T36	1		T50	1
pow[0x6]	259	1			T1	4		T36	5		T40	3
pow[0x7]	583	1			T1	8		T36	11		T40	6

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

220

1

T1

1

T36

3

T50

2

min

1426

1

T1

3

T36

4

T13

16

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	1	15	93.75

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x5]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1427	1			T1	3		T36	4		T13	16
pow[0x1]	16	1			T260	1		T60	3		T199	1
pow[0x2]	50	1			T16	2		T32	2		T37	1
pow[0x3]	49	1			T13	1		T16	4		T33	1
pow[0x4]	55	1			T13	5		T33	1		T38	5
pow[0x6]	2	1			T214	1		T326	1		-	-
pow[0x7]	1	1			T327	1		-	-		-	-
pow[0x8]	8	1			T328	1		T212	1		T215	1
pow[0x9]	13	1			T325	1		T209	1		T53	1
pow[0xa]	23	1			T26	1		T173	2		T328	1
pow[0xb]	39	1			T1	1		T40	2		T325	1
pow[0xc]	72	1			T1	2		T40	2		T26	1
pow[0xd]	154	1			T1	2		T36	3		T40	2
pow[0xe]	303	1			T1	2		T36	4		T13	1
pow[0xf]	619	1			T1	10		T36	8		T40	12