Unified Coverage Report :: Module :: adc_ctrl_core

Module : adc_ctrl_core

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_adc_ctrl_core	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_adc_ctrl_core

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.83	100.00	99.76		100.00	99.37	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_adc_ctrl_fsm	99.75	100.00	100.00		100.00	98.73	100.00
u_adc_ctrl_intr	99.00	100.00	96.00			100.00	100.00
u_oneshot_done_sync	100.00	100.00	100.00			100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : adc_ctrl_core

	Line No.	Total	Covered	Percent
TOTAL		63	63	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	73	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	83	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	137	1	1	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	213	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv' or '../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	8	8
63	8	8
72	1	1
73	1	1
74	1	1
75	1	1
83	1	1
86	1	1
87	1	1
88	1	1
89	1	1
104	8	8
107	8	8
117	8	8
121	8	8
137	1	1
138	1	1
140	1	1
141	1	1
145	1	1
213	1	1

---

Cond Coverage for Module : adc_ctrl_core

	Total	Covered	Percent
Conditions	293	293	100.00
Logical	293	293	100.00
Non-Logical	0	0
Event	0	0

 LINE       83
 EXPRESSION (reg2hw_i.adc_en_ctl.oneshot_mode.q ? oneshot_done : (reg2hw_i.adc_en_ctl.adc_enable.q ? ((|match_pulse)) : '0))
             -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T3,T7

 LINE       83
 SUB-EXPRESSION (reg2hw_i.adc_en_ctl.adc_enable.q ? ((|match_pulse)) : '0)
                 ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T4,T2
1	Covered	T1,T2,T5

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][0].cond)) ? ((aon_filter_ctl[0][0].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][0].max_v)) : ((aon_filter_ctl[0][0].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][0].max_v)))

-1-	Status	Tests
0	Covered	T2,T5,T6
1	Covered	T1,T4,T2

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][0].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][0].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T11
1	0	Covered	T1,T3,T5
1	1	Covered	T1,T4,T2

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][0].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][0].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T5,T6
0	1	Covered	T2,T6,T9
1	0	Covered	T2,T5,T6

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][1].cond)) ? ((aon_filter_ctl[0][1].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][1].max_v)) : ((aon_filter_ctl[0][1].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][1].max_v)))

-1-	Status	Tests
0	Covered	T2,T6,T9
1	Covered	T1,T4,T2

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][1].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][1].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T9
1	0	Covered	T1,T3,T5
1	1	Covered	T1,T4,T2

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][1].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][1].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T6,T9
0	1	Covered	T2,T6,T9
1	0	Covered	T2,T6,T9

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][2].cond)) ? ((aon_filter_ctl[0][2].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][2].max_v)) : ((aon_filter_ctl[0][2].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][2].max_v)))

-1-	Status	Tests
0	Covered	T2,T5,T6
1	Covered	T1,T4,T2

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][2].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][2].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T2

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][2].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][2].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T5,T6
0	1	Covered	T2,T5,T6
1	0	Covered	T2,T5,T6

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][3].cond)) ? ((aon_filter_ctl[0][3].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][3].max_v)) : ((aon_filter_ctl[0][3].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][3].max_v)))

-1-	Status	Tests
0	Covered	T5,T6,T11
1	Covered	T1,T4,T2

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][3].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][3].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T2

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][3].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][3].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T11
0	1	Covered	T5,T6,T11
1	0	Covered	T5,T6,T11

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][4].cond)) ? ((aon_filter_ctl[0][4].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][4].max_v)) : ((aon_filter_ctl[0][4].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][4].max_v)))

-1-	Status	Tests
0	Covered	T2,T5,T6
1	Covered	T1,T4,T2

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][4].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][4].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T9,T10
1	0	Covered	T1,T3,T6
1	1	Covered	T1,T4,T2

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][4].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][4].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T5,T6
0	1	Covered	T2,T5,T6
1	0	Covered	T2,T5,T6

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][5].cond)) ? ((aon_filter_ctl[0][5].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][5].max_v)) : ((aon_filter_ctl[0][5].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][5].max_v)))

-1-	Status	Tests
0	Covered	T2,T5,T6
1	Covered	T1,T4,T2

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][5].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][5].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T9,T11
1	0	Covered	T1,T3,T6
1	1	Covered	T1,T4,T2

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][5].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][5].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T5,T6
0	1	Covered	T2,T5,T6
1	0	Covered	T2,T5,T6

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][6].cond)) ? ((aon_filter_ctl[0][6].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][6].max_v)) : ((aon_filter_ctl[0][6].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][6].max_v)))

-1-	Status	Tests
0	Covered	T2,T6,T9
1	Covered	T1,T4,T2

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][6].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][6].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T2

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][6].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][6].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T6,T9
0	1	Covered	T2,T6,T9
1	0	Covered	T2,T6,T9

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][7].cond)) ? ((aon_filter_ctl[0][7].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][7].max_v)) : ((aon_filter_ctl[0][7].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][7].max_v)))

-1-	Status	Tests
0	Covered	T2,T5,T6
1	Covered	T1,T4,T2

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][7].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][7].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T2

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][7].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][7].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T5,T6
0	1	Covered	T2,T5,T6
1	0	Covered	T2,T5,T6

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][0].cond)) ? ((aon_filter_ctl[1][0].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][0].max_v)) : ((aon_filter_ctl[1][0].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][0].max_v)))

-1-	Status	Tests
0	Covered	T2,T5,T6
1	Covered	T1,T4,T2

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][0].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][0].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T9
1	0	Covered	T1,T3,T5
1	1	Covered	T1,T4,T2

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][0].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][0].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T5,T6
0	1	Covered	T2,T5,T6
1	0	Covered	T2,T5,T6

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][1].cond)) ? ((aon_filter_ctl[1][1].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][1].max_v)) : ((aon_filter_ctl[1][1].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][1].max_v)))

-1-	Status	Tests
0	Covered	T5,T6,T9
1	Covered	T1,T4,T2

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][1].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][1].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T2

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][1].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][1].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T9
0	1	Covered	T5,T6,T9
1	0	Covered	T5,T6,T9

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][2].cond)) ? ((aon_filter_ctl[1][2].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][2].max_v)) : ((aon_filter_ctl[1][2].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][2].max_v)))

-1-	Status	Tests
0	Covered	T2,T5,T6
1	Covered	T1,T4,T2

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][2].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][2].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T2

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][2].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][2].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T5,T6
0	1	Covered	T2,T5,T6
1	0	Covered	T2,T5,T6

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][3].cond)) ? ((aon_filter_ctl[1][3].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][3].max_v)) : ((aon_filter_ctl[1][3].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][3].max_v)))

-1-	Status	Tests
0	Covered	T5,T6,T11
1	Covered	T1,T4,T2

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][3].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][3].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T2

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][3].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][3].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T11
0	1	Covered	T5,T6,T11
1	0	Covered	T5,T6,T11

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][4].cond)) ? ((aon_filter_ctl[1][4].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][4].max_v)) : ((aon_filter_ctl[1][4].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][4].max_v)))

-1-	Status	Tests
0	Covered	T2,T5,T6
1	Covered	T1,T4,T2

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][4].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][4].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T9,T10
1	0	Covered	T1,T3,T6
1	1	Covered	T1,T4,T2

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][4].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][4].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T5,T6
0	1	Covered	T2,T5,T6
1	0	Covered	T2,T5,T6

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][5].cond)) ? ((aon_filter_ctl[1][5].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][5].max_v)) : ((aon_filter_ctl[1][5].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][5].max_v)))

-1-	Status	Tests
0	Covered	T2,T5,T6
1	Covered	T1,T4,T2

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][5].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][5].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T9,T11
1	0	Covered	T1,T3,T6
1	1	Covered	T1,T4,T2

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][5].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][5].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T5,T6
0	1	Covered	T2,T5,T6
1	0	Covered	T2,T5,T6

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][6].cond)) ? ((aon_filter_ctl[1][6].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][6].max_v)) : ((aon_filter_ctl[1][6].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][6].max_v)))

-1-	Status	Tests
0	Covered	T2,T6,T9
1	Covered	T1,T4,T2

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][6].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][6].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T2

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][6].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][6].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T6,T9
0	1	Covered	T2,T6,T9
1	0	Covered	T2,T6,T9

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][7].cond)) ? ((aon_filter_ctl[1][7].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][7].max_v)) : ((aon_filter_ctl[1][7].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][7].max_v)))

-1-	Status	Tests
0	Covered	T2,T5,T6
1	Covered	T1,T4,T2

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][7].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][7].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T2

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][7].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][7].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T5,T6
0	1	Covered	T2,T5,T6
1	0	Covered	T2,T5,T6

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][0].en, aon_filter_ctl[1][0].en})) & 
      2  (((!aon_filter_ctl[0][0].en)) | (chn0_match[0] & aon_filter_ctl[0][0].en)) & 
      3  (((!aon_filter_ctl[1][0].en)) | (chn1_match[0] & aon_filter_ctl[1][0].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T2
1	0	1	Covered	T6,T9,T10
1	1	0	Covered	T6,T9,T10
1	1	1	Covered	T1,T6,T9

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][0].en)) | (chn0_match[0] & aon_filter_ctl[0][0].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T9,T10
0	1	Covered	T1,T6,T9
1	0	Covered	T1,T4,T2

 LINE       117
 SUB-EXPRESSION (chn0_match[0] & aon_filter_ctl[0][0].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T6,T9,T10
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T6,T9

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][0].en)) | (chn1_match[0] & aon_filter_ctl[1][0].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T9,T10
0	1	Covered	T1,T6,T9
1	0	Covered	T1,T4,T2

 LINE       117
 SUB-EXPRESSION (chn1_match[0] & aon_filter_ctl[1][0].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T6,T9,T10
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T6,T9

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][1].en, aon_filter_ctl[1][1].en})) & 
      2  (((!aon_filter_ctl[0][1].en)) | (chn0_match[1] & aon_filter_ctl[0][1].en)) & 
      3  (((!aon_filter_ctl[1][1].en)) | (chn1_match[1] & aon_filter_ctl[1][1].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T2
1	0	1	Covered	T2,T5,T9
1	1	0	Covered	T2,T5,T9
1	1	1	Covered	T2,T5,T9

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][1].en)) | (chn0_match[1] & aon_filter_ctl[0][1].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T5,T9
0	1	Covered	T2,T5,T9
1	0	Covered	T1,T4,T2

 LINE       117
 SUB-EXPRESSION (chn0_match[1] & aon_filter_ctl[0][1].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T9
1	0	Covered	T1,T4,T2
1	1	Covered	T2,T5,T9

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][1].en)) | (chn1_match[1] & aon_filter_ctl[1][1].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T5,T9
0	1	Covered	T2,T5,T9
1	0	Covered	T1,T4,T2

 LINE       117
 SUB-EXPRESSION (chn1_match[1] & aon_filter_ctl[1][1].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T9
1	0	Covered	T1,T4,T2
1	1	Covered	T2,T5,T9

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][2].en, aon_filter_ctl[1][2].en})) & 
      2  (((!aon_filter_ctl[0][2].en)) | (chn0_match[2] & aon_filter_ctl[0][2].en)) & 
      3  (((!aon_filter_ctl[1][2].en)) | (chn1_match[2] & aon_filter_ctl[1][2].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T2
1	0	1	Covered	T2,T5,T6
1	1	0	Covered	T2,T5,T6
1	1	1	Covered	T2,T5,T6

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][2].en)) | (chn0_match[2] & aon_filter_ctl[0][2].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T5,T6
0	1	Covered	T2,T5,T6
1	0	Covered	T1,T4,T2

 LINE       117
 SUB-EXPRESSION (chn0_match[2] & aon_filter_ctl[0][2].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T1,T4,T2
1	1	Covered	T2,T5,T6

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][2].en)) | (chn1_match[2] & aon_filter_ctl[1][2].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T5,T6
0	1	Covered	T2,T5,T6
1	0	Covered	T1,T4,T2

 LINE       117
 SUB-EXPRESSION (chn1_match[2] & aon_filter_ctl[1][2].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T1,T4,T2
1	1	Covered	T2,T5,T6

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][3].en, aon_filter_ctl[1][3].en})) & 
      2  (((!aon_filter_ctl[0][3].en)) | (chn0_match[3] & aon_filter_ctl[0][3].en)) & 
      3  (((!aon_filter_ctl[1][3].en)) | (chn1_match[3] & aon_filter_ctl[1][3].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T2
1	0	1	Covered	T5,T6,T9
1	1	0	Covered	T5,T6,T9
1	1	1	Covered	T5,T6,T9

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][3].en)) | (chn0_match[3] & aon_filter_ctl[0][3].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T9
0	1	Covered	T5,T6,T9
1	0	Covered	T1,T4,T2

 LINE       117
 SUB-EXPRESSION (chn0_match[3] & aon_filter_ctl[0][3].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T9
1	0	Covered	T1,T4,T2
1	1	Covered	T5,T6,T9

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][3].en)) | (chn1_match[3] & aon_filter_ctl[1][3].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T9
0	1	Covered	T5,T6,T9
1	0	Covered	T1,T4,T2

 LINE       117
 SUB-EXPRESSION (chn1_match[3] & aon_filter_ctl[1][3].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T9
1	0	Covered	T1,T4,T2
1	1	Covered	T5,T6,T9

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][4].en, aon_filter_ctl[1][4].en})) & 
      2  (((!aon_filter_ctl[0][4].en)) | (chn0_match[4] & aon_filter_ctl[0][4].en)) & 
      3  (((!aon_filter_ctl[1][4].en)) | (chn1_match[4] & aon_filter_ctl[1][4].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T2
1	0	1	Covered	T2,T5,T6
1	1	0	Covered	T2,T5,T6
1	1	1	Covered	T2,T5,T6

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][4].en)) | (chn0_match[4] & aon_filter_ctl[0][4].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T5,T6
0	1	Covered	T2,T5,T6
1	0	Covered	T1,T4,T2

 LINE       117
 SUB-EXPRESSION (chn0_match[4] & aon_filter_ctl[0][4].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T1,T4,T2
1	1	Covered	T2,T5,T6

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][4].en)) | (chn1_match[4] & aon_filter_ctl[1][4].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T5,T6
0	1	Covered	T2,T5,T6
1	0	Covered	T1,T4,T2

 LINE       117
 SUB-EXPRESSION (chn1_match[4] & aon_filter_ctl[1][4].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T1,T4,T2
1	1	Covered	T2,T5,T6

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][5].en, aon_filter_ctl[1][5].en})) & 
      2  (((!aon_filter_ctl[0][5].en)) | (chn0_match[5] & aon_filter_ctl[0][5].en)) & 
      3  (((!aon_filter_ctl[1][5].en)) | (chn1_match[5] & aon_filter_ctl[1][5].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T2
1	0	1	Covered	T2,T5,T6
1	1	0	Covered	T2,T5,T6
1	1	1	Covered	T2,T5,T6

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][5].en)) | (chn0_match[5] & aon_filter_ctl[0][5].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T5,T6
0	1	Covered	T2,T5,T6
1	0	Covered	T1,T4,T2

 LINE       117
 SUB-EXPRESSION (chn0_match[5] & aon_filter_ctl[0][5].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T1,T4,T2
1	1	Covered	T2,T5,T6

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][5].en)) | (chn1_match[5] & aon_filter_ctl[1][5].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T5,T6
0	1	Covered	T2,T5,T6
1	0	Covered	T1,T4,T2

 LINE       117
 SUB-EXPRESSION (chn1_match[5] & aon_filter_ctl[1][5].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T1,T4,T2
1	1	Covered	T2,T5,T6

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][6].en, aon_filter_ctl[1][6].en})) & 
      2  (((!aon_filter_ctl[0][6].en)) | (chn0_match[6] & aon_filter_ctl[0][6].en)) & 
      3  (((!aon_filter_ctl[1][6].en)) | (chn1_match[6] & aon_filter_ctl[1][6].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T2
1	0	1	Covered	T2,T6,T9
1	1	0	Covered	T2,T6,T9
1	1	1	Covered	T2,T6,T9

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][6].en)) | (chn0_match[6] & aon_filter_ctl[0][6].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T6,T9
0	1	Covered	T2,T6,T9
1	0	Covered	T1,T4,T2

 LINE       117
 SUB-EXPRESSION (chn0_match[6] & aon_filter_ctl[0][6].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T9
1	0	Covered	T1,T4,T2
1	1	Covered	T2,T6,T9

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][6].en)) | (chn1_match[6] & aon_filter_ctl[1][6].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T6,T9
0	1	Covered	T2,T6,T9
1	0	Covered	T1,T4,T2

 LINE       117
 SUB-EXPRESSION (chn1_match[6] & aon_filter_ctl[1][6].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T9
1	0	Covered	T1,T4,T2
1	1	Covered	T2,T6,T9

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][7].en, aon_filter_ctl[1][7].en})) & 
      2  (((!aon_filter_ctl[0][7].en)) | (chn0_match[7] & aon_filter_ctl[0][7].en)) & 
      3  (((!aon_filter_ctl[1][7].en)) | (chn1_match[7] & aon_filter_ctl[1][7].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T4,T2
1	0	1	Covered	T2,T5,T6
1	1	0	Covered	T2,T5,T6
1	1	1	Covered	T2,T5,T6

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][7].en)) | (chn0_match[7] & aon_filter_ctl[0][7].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T5,T6
0	1	Covered	T2,T5,T6
1	0	Covered	T1,T4,T2

 LINE       117
 SUB-EXPRESSION (chn0_match[7] & aon_filter_ctl[0][7].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T1,T4,T2
1	1	Covered	T2,T5,T6

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][7].en)) | (chn1_match[7] & aon_filter_ctl[1][7].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T5,T6
0	1	Covered	T2,T5,T6
1	0	Covered	T1,T4,T2

 LINE       117
 SUB-EXPRESSION (chn1_match[7] & aon_filter_ctl[1][7].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T1,T4,T2
1	1	Covered	T2,T5,T6

 LINE       121
 EXPRESSION (adc_ctrl_done && match[0])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T6,T9
1	0	Covered	T2,T5,T6
1	1	Covered	T6,T9,T10

 LINE       121
 EXPRESSION (adc_ctrl_done && match[1])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T9
1	0	Covered	T2,T5,T6
1	1	Covered	T2,T5,T9

 LINE       121
 EXPRESSION (adc_ctrl_done && match[2])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T2,T5,T6
1	1	Covered	T2,T5,T6

 LINE       121
 EXPRESSION (adc_ctrl_done && match[3])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T9
1	0	Covered	T2,T5,T6
1	1	Covered	T5,T6,T9

 LINE       121
 EXPRESSION (adc_ctrl_done && match[4])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T2,T5,T6
1	1	Covered	T2,T5,T6

 LINE       121
 EXPRESSION (adc_ctrl_done && match[5])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T2,T5,T6
1	1	Covered	T2,T5,T6

 LINE       121
 EXPRESSION (adc_ctrl_done && match[6])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T9
1	0	Covered	T2,T5,T6
1	1	Covered	T2,T6,T9

 LINE       121
 EXPRESSION (adc_ctrl_done && match[7])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T2,T5,T6
1	1	Covered	T2,T5,T6

 LINE       140
 EXPRESSION (aon_fsm_trans | reg2hw_i.filter_status.trans.q)
             ------1------   ---------------2--------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Covered	T2,T5,T6
1	0	Covered	T2,T5,T6

 LINE       145
 EXPRESSION (((|(reg2hw_i.filter_status.match.q & reg2hw_i.adc_wakeup_ctl.match_en.q))) || (reg2hw_i.filter_status.trans.q & reg2hw_i.adc_wakeup_ctl.trans_en.q))
             -------------------------------------1------------------------------------    ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Covered	T6,T9,T11
1	0	Covered	T2,T5,T6

 LINE       145
 SUB-EXPRESSION (reg2hw_i.filter_status.trans.q & reg2hw_i.adc_wakeup_ctl.trans_en.q)
                 ---------------1--------------   -----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T9
1	0	Covered	T2,T5,T6
1	1	Covered	T6,T9,T11

---

Branch Coverage for Module : adc_ctrl_core

	Line No.	Total	Covered	Percent
Branches		35	35	100.00
TERNARY	83	3	3	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv' or '../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	83	(reg2hw_i.adc_en_ctl.oneshot_mode.q) ? 
-2-:	83	(reg2hw_i.adc_en_ctl.adc_enable.q) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T3,T7
0	1	Covered	T1,T2,T5
0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][0].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T2,T5,T6

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][0].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T2,T5,T6

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][1].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T2,T6,T9

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][1].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T5,T6,T9

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][2].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T2,T5,T6

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][2].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T2,T5,T6

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][3].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T5,T6,T11

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][3].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T5,T6,T11

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][4].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T2,T5,T6

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][4].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T2,T5,T6

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][5].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T2,T5,T6

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][5].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T2,T5,T6

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][6].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T2,T6,T9

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][6].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T2,T6,T9

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][7].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T2,T5,T6

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][7].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T2,T5,T6

---

Assert Coverage for Module : adc_ctrl_core

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	33	33	100.00	33	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	33	33	100.00	33	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
MaxFilters_A	34797592	34468034	0	0
gen_filter_match[0].MatchCheck00_A	34797592	10484779	0	0
gen_filter_match[0].MatchCheck01_A	34797592	2545889	0	0
gen_filter_match[0].MatchCheck10_A	34797592	2257549	0	0
gen_filter_match[0].MatchCheck11_A	34797592	19179817	0	0
gen_filter_match[1].MatchCheck00_A	34797592	12136929	0	0
gen_filter_match[1].MatchCheck01_A	34797592	971055	0	0
gen_filter_match[1].MatchCheck10_A	34797592	1151486	0	0
gen_filter_match[1].MatchCheck11_A	34797592	20208564	0	0
gen_filter_match[2].MatchCheck00_A	34797592	12398398	0	0
gen_filter_match[2].MatchCheck01_A	34797592	623720	0	0
gen_filter_match[2].MatchCheck10_A	34797592	697932	0	0
gen_filter_match[2].MatchCheck11_A	34797592	20747984	0	0
gen_filter_match[3].MatchCheck00_A	34797592	12338195	0	0
gen_filter_match[3].MatchCheck01_A	34797592	353389	0	0
gen_filter_match[3].MatchCheck10_A	34797592	564380	0	0
gen_filter_match[3].MatchCheck11_A	34797592	21212070	0	0
gen_filter_match[4].MatchCheck00_A	34797592	12887439	0	0
gen_filter_match[4].MatchCheck01_A	34797592	33349	0	0
gen_filter_match[4].MatchCheck10_A	34797592	69068	0	0
gen_filter_match[4].MatchCheck11_A	34797592	21478178	0	0
gen_filter_match[5].MatchCheck00_A	34797592	13356209	0	0
gen_filter_match[5].MatchCheck01_A	34797592	70490	0	0
gen_filter_match[5].MatchCheck10_A	34797592	50656	0	0
gen_filter_match[5].MatchCheck11_A	34797592	20990679	0	0
gen_filter_match[6].MatchCheck00_A	34797592	13516194	0	0
gen_filter_match[6].MatchCheck01_A	34797592	11967	0	0
gen_filter_match[6].MatchCheck10_A	34797592	100477	0	0
gen_filter_match[6].MatchCheck11_A	34797592	20839396	0	0
gen_filter_match[7].MatchCheck00_A	34797592	12778542	0	0
gen_filter_match[7].MatchCheck01_A	34797592	103947	0	0
gen_filter_match[7].MatchCheck10_A	34797592	196559	0	0
gen_filter_match[7].MatchCheck11_A	34797592	21388986	0	0

MaxFilters_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34797592	34468034	0	0
T1	21683	18904	0	0
T2	72186	72126	0	0
T3	1166	1075	0	0
T4	77	5	0	0
T5	66452	66378	0	0
T6	104304	104242	0	0
T7	836	738	0	0
T8	1174	1124	0	0
T9	65886	65791	0	0
T10	32767	32703	0	0

gen_filter_match[0].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34797592	10484779	0	0
T1	21683	18555	0	0
T2	72186	72126	0	0
T3	1166	1075	0	0
T4	77	5	0	0
T5	66452	66378	0	0
T6	104304	33418	0	0
T7	836	738	0	0
T8	1174	1124	0	0
T9	65886	32380	0	0
T10	32767	3	0	0

gen_filter_match[0].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34797592	2545889	0	0
T16	0	23119	0	0
T33	0	585	0	0
T44	98974	31997	0	0
T45	9034	0	0	0
T48	96730	32312	0	0
T104	884	0	0	0
T105	82671	0	0	0
T106	106241	0	0	0
T124	1217	0	0	0
T125	0	34218	0	0
T126	0	33380	0	0
T127	0	32610	0	0
T128	0	37288	0	0
T129	0	35064	0	0
T130	0	32030	0	0
T131	97922	0	0	0
T132	97477	0	0	0
T133	6227	0	0	0

gen_filter_match[0].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34797592	2257549	0	0
T16	0	4	0	0
T41	120735	2	0	0
T42	9359	0	0	0
T43	65291	0	0	0
T44	98974	0	0	0
T45	9034	0	0	0
T48	96730	0	0	0
T104	884	0	0	0
T127	0	32853	0	0
T131	97922	0	0	0
T132	97477	0	0	0
T133	6227	0	0	0
T134	0	32648	0	0
T135	0	32563	0	0
T136	0	1	0	0
T137	0	31835	0	0
T138	0	33938	0	0
T139	0	34295	0	0
T140	0	36410	0	0

gen_filter_match[0].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34797592	19179817	0	0
T1	21683	349	0	0
T2	72186	0	0	0
T3	1166	0	0	0
T4	77	0	0	0
T5	66452	0	0	0
T6	104304	70824	0	0
T7	836	0	0	0
T8	1174	0	0	0
T9	65886	33411	0	0
T10	32767	32700	0	0
T12	0	34541	0	0
T13	0	10374	0	0
T14	0	38011	0	0
T15	0	32856	0	0
T36	0	619	0	0
T40	0	173	0	0

gen_filter_match[1].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34797592	12136929	0	0
T1	21683	18904	0	0
T2	72186	4	0	0
T3	1166	1075	0	0
T4	77	5	0	0
T5	66452	3	0	0
T6	104304	104242	0	0
T7	836	738	0	0
T8	1174	1124	0	0
T9	65886	32380	0	0
T10	32767	32703	0	0

gen_filter_match[1].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34797592	971055	0	0
T5	66452	32543	0	0
T6	104304	0	0	0
T7	836	0	0	0
T8	1174	0	0	0
T9	65886	0	0	0
T10	32767	0	0	0
T11	89993	0	0	0
T12	34601	0	0	0
T13	17189	0	0	0
T15	0	32856	0	0
T36	23670	0	0	0
T51	0	32565	0	0
T125	0	34624	0	0
T141	0	33371	0	0
T142	0	32978	0	0
T143	0	33517	0	0
T144	0	32195	0	0
T145	0	1	0	0
T146	0	1	0	0

gen_filter_match[1].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34797592	1151486	0	0
T2	72186	35892	0	0
T3	1166	0	0	0
T5	66452	0	0	0
T6	104304	0	0	0
T7	836	0	0	0
T8	1174	0	0	0
T9	65886	0	0	0
T10	32767	0	0	0
T11	89993	0	0	0
T12	34601	34541	0	0
T16	0	33692	0	0
T32	0	9956	0	0
T41	0	2	0	0
T129	0	32568	0	0
T136	0	1	0	0
T138	0	32353	0	0
T147	0	1	0	0
T148	0	32593	0	0

gen_filter_match[1].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34797592	20208564	0	0
T2	72186	36230	0	0
T3	1166	0	0	0
T5	66452	33832	0	0
T6	104304	0	0	0
T7	836	0	0	0
T8	1174	0	0	0
T9	65886	33411	0	0
T10	32767	0	0	0
T11	89993	35594	0	0
T12	34601	0	0	0
T13	0	10067	0	0
T14	0	39478	0	0
T41	0	120678	0	0
T43	0	65231	0	0
T44	0	32853	0	0
T48	0	96643	0	0

gen_filter_match[2].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34797592	12398398	0	0
T1	21683	18904	0	0
T2	72186	35896	0	0
T3	1166	1075	0	0
T4	77	5	0	0
T5	66452	33835	0	0
T6	104304	4	0	0
T7	836	738	0	0
T8	1174	1124	0	0
T9	65886	32380	0	0
T10	32767	3	0	0

gen_filter_match[2].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34797592	623720	0	0
T37	56395	6785	0	0
T78	0	33950	0	0
T79	0	3	0	0
T127	65516	0	0	0
T135	103168	0	0	0
T136	66166	0	0	0
T141	64535	0	0	0
T142	33056	0	0	0
T145	0	1	0	0
T149	0	32052	0	0
T150	0	34593	0	0
T151	0	32519	0	0
T152	0	1	0	0
T153	0	65121	0	0
T154	0	1	0	0
T155	77	0	0	0
T156	101638	0	0	0
T157	86	0	0	0
T158	32939	0	0	0

gen_filter_match[2].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34797592	697932	0	0
T38	0	9141	0	0
T41	120735	2	0	0
T42	9359	0	0	0
T43	65291	0	0	0
T44	98974	0	0	0
T45	9034	0	0	0
T48	96730	0	0	0
T104	884	0	0	0
T131	97922	0	0	0
T132	97477	0	0	0
T133	6227	0	0	0
T136	0	1	0	0
T145	0	38767	0	0
T146	0	1	0	0
T159	0	33077	0	0
T160	0	32413	0	0
T161	0	32025	0	0
T162	0	32799	0	0
T163	0	38524	0	0

gen_filter_match[2].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34797592	20747984	0	0
T2	72186	36230	0	0
T3	1166	0	0	0
T5	66452	32543	0	0
T6	104304	104238	0	0
T7	836	0	0	0
T8	1174	0	0	0
T9	65886	33411	0	0
T10	32767	32700	0	0
T11	89993	0	0	0
T12	34601	0	0	0
T15	0	87153	0	0
T41	0	120678	0	0
T43	0	65231	0	0
T44	0	31997	0	0
T48	0	64331	0	0

gen_filter_match[3].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34797592	12338195	0	0
T1	21683	18904	0	0
T2	72186	72126	0	0
T3	1166	1075	0	0
T4	77	5	0	0
T5	66452	32546	0	0
T6	104304	33901	0	0
T7	836	738	0	0
T8	1174	1124	0	0
T9	65886	32380	0	0
T10	32767	3	0	0

gen_filter_match[3].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34797592	353389	0	0
T18	0	15889	0	0
T79	0	3	0	0
T82	0	1	0	0
T137	103695	32924	0	0
T138	99430	0	0	0
T139	104667	0	0	0
T144	98336	0	0	0
T145	0	1	0	0
T152	0	1	0	0
T164	0	33004	0	0
T165	0	36470	0	0
T166	0	33094	0	0
T167	0	32060	0	0
T168	1174	0	0	0
T169	81528	0	0	0
T170	33275	0	0	0
T171	9400	0	0	0
T172	33355	0	0	0
T173	21708	0	0	0

gen_filter_match[3].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34797592	564380	0	0
T16	0	3	0	0
T41	120735	1	0	0
T42	9359	0	0	0
T43	65291	0	0	0
T44	98974	0	0	0
T45	9034	0	0	0
T48	96730	0	0	0
T104	884	0	0	0
T106	0	35859	0	0
T130	0	31629	0	0
T131	97922	0	0	0
T132	97477	32277	0	0
T133	6227	0	0	0
T136	0	1	0	0
T139	0	32062	0	0
T145	0	2	0	0
T174	0	1	0	0
T175	0	1	0	0

gen_filter_match[3].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34797592	21212070	0	0
T5	66452	33832	0	0
T6	104304	70341	0	0
T7	836	0	0	0
T8	1174	0	0	0
T9	65886	33411	0	0
T10	32767	32700	0	0
T11	89993	0	0	0
T12	34601	34541	0	0
T13	17189	0	0	0
T14	0	34219	0	0
T15	0	54297	0	0
T36	23670	0	0	0
T41	0	120678	0	0
T43	0	65231	0	0
T44	0	98874	0	0

gen_filter_match[4].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34797592	12887439	0	0
T1	21683	18904	0	0
T2	72186	36234	0	0
T3	1166	1075	0	0
T4	77	5	0	0
T5	66452	3	0	0
T6	104304	70828	0	0
T7	836	738	0	0
T8	1174	1124	0	0
T9	65886	33415	0	0
T10	32767	3	0	0

gen_filter_match[4].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34797592	33349	0	0
T50	16474	0	0	0
T82	0	1	0	0
T106	106241	1	0	0
T125	105230	0	0	0
T126	65906	0	0	0
T146	0	1	0	0
T152	0	1	0	0
T154	0	1	0	0
T174	66557	0	0	0
T176	0	1	0	0
T177	0	1	0	0
T178	0	2	0	0
T179	0	1	0	0
T180	0	1	0	0
T181	32536	0	0	0
T182	64933	0	0	0
T183	67368	0	0	0
T184	1122	0	0	0
T185	98229	0	0	0

gen_filter_match[4].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34797592	69068	0	0
T16	0	8	0	0
T41	120735	1	0	0
T42	9359	0	0	0
T43	65291	0	0	0
T44	98974	0	0	0
T45	9034	0	0	0
T48	96730	0	0	0
T104	884	0	0	0
T127	0	1	0	0
T131	97922	0	0	0
T132	97477	0	0	0
T133	6227	0	0	0
T136	0	1	0	0
T142	0	1	0	0
T145	0	1	0	0
T146	0	1	0	0
T174	0	1	0	0
T175	0	1	0	0
T186	0	1	0	0

gen_filter_match[4].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34797592	21478178	0	0
T2	72186	35892	0	0
T3	1166	0	0	0
T5	66452	66375	0	0
T6	104304	33414	0	0
T7	836	0	0	0
T8	1174	0	0	0
T9	65886	32376	0	0
T10	32767	32700	0	0
T11	89993	35594	0	0
T12	34601	0	0	0
T13	0	10067	0	0
T14	0	73697	0	0
T41	0	120678	0	0
T43	0	65231	0	0

gen_filter_match[5].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34797592	13356209	0	0
T1	21683	18904	0	0
T2	72186	35896	0	0
T3	1166	1075	0	0
T4	77	5	0	0
T5	66452	3	0	0
T6	104304	36931	0	0
T7	836	738	0	0
T8	1174	1124	0	0
T9	65886	32380	0	0
T10	32767	3	0	0

gen_filter_match[5].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34797592	70490	0	0
T146	70425	1	0	0
T150	100416	0	0	0
T152	0	1	0	0
T178	0	2	0	0
T180	0	1	0	0
T187	0	1	0	0
T188	0	3	0	0
T189	0	32532	0	0
T190	0	37949	0	0
T191	76562	0	0	0
T192	35737	0	0	0
T193	98544	0	0	0
T194	6949	0	0	0
T195	22876	0	0	0
T196	32167	0	0	0
T197	98543	0	0	0
T198	8282	0	0	0

gen_filter_match[5].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34797592	50656	0	0
T10	32767	1	0	0
T11	89993	0	0	0
T12	34601	0	0	0
T13	17189	0	0	0
T14	111777	0	0	0
T15	87245	0	0	0
T16	0	7	0	0
T36	23670	0	0	0
T40	21627	0	0	0
T41	120735	2	0	0
T42	9359	0	0	0
T106	0	1	0	0
T127	0	1	0	0
T136	0	1	0	0
T147	0	1	0	0
T162	0	1	0	0
T174	0	1	0	0
T175	0	1	0	0

gen_filter_match[5].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34797592	20990679	0	0
T2	72186	36230	0	0
T3	1166	0	0	0
T5	66452	66375	0	0
T6	104304	67311	0	0
T7	836	0	0	0
T8	1174	0	0	0
T9	65886	33411	0	0
T10	32767	32699	0	0
T11	89993	0	0	0
T12	34601	34541	0	0
T13	0	10067	0	0
T14	0	111708	0	0
T15	0	32856	0	0
T41	0	120677	0	0

gen_filter_match[6].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34797592	13516194	0	0
T1	21683	18904	0	0
T2	72186	36234	0	0
T3	1166	1075	0	0
T4	77	5	0	0
T5	66452	66378	0	0
T6	104304	70828	0	0
T7	836	738	0	0
T8	1174	1124	0	0
T9	65886	33415	0	0
T10	32767	3	0	0

gen_filter_match[6].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34797592	11967	0	0
T103	0	1	0	0
T127	65516	1	0	0
T128	37370	0	0	0
T136	66166	0	0	0
T141	64535	0	0	0
T142	33056	0	0	0
T145	0	1	0	0
T154	0	1	0	0
T158	32939	0	0	0
T159	65969	0	0	0
T180	0	1	0	0
T188	0	3	0	0
T199	0	11957	0	0
T200	0	2	0	0
T201	1181	0	0	0
T202	64955	0	0	0
T203	32371	0	0	0

gen_filter_match[6].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34797592	100477	0	0
T10	32767	1	0	0
T11	89993	0	0	0
T12	34601	0	0	0
T13	17189	0	0	0
T14	111777	0	0	0
T15	87245	0	0	0
T16	0	2	0	0
T36	23670	0	0	0
T40	21627	0	0	0
T41	120735	2	0	0
T42	9359	0	0	0
T44	0	34024	0	0
T106	0	1	0	0
T127	0	1	0	0
T136	0	1	0	0
T137	0	1	0	0
T147	0	1	0	0
T174	0	1	0	0

gen_filter_match[6].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34797592	20839396	0	0
T2	72186	35892	0	0
T3	1166	0	0	0
T5	66452	0	0	0
T6	104304	33414	0	0
T7	836	0	0	0
T8	1174	0	0	0
T9	65886	32376	0	0
T10	32767	32699	0	0
T11	89993	0	0	0
T12	34601	0	0	0
T14	0	39478	0	0
T41	0	120677	0	0
T43	0	65231	0	0
T48	0	64331	0	0
T131	0	31955	0	0
T132	0	65193	0	0

gen_filter_match[7].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34797592	12778542	0	0
T1	21683	18904	0	0
T2	72186	4	0	0
T3	1166	1075	0	0
T4	77	5	0	0
T5	66452	32546	0	0
T6	104304	70345	0	0
T7	836	738	0	0
T8	1174	1124	0	0
T9	65886	32380	0	0
T10	32767	32703	0	0

gen_filter_match[7].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34797592	103947	0	0
T37	0	32019	0	0
T50	16474	0	0	0
T79	0	3	0	0
T103	0	1	0	0
T106	106241	1	0	0
T125	105230	0	0	0
T126	65906	0	0	0
T139	0	1	0	0
T140	0	35586	0	0
T152	0	1	0	0
T174	66557	0	0	0
T176	0	1	0	0
T181	32536	0	0	0
T182	64933	0	0	0
T183	67368	0	0	0
T184	1122	0	0	0
T185	98229	0	0	0
T204	0	1	0	0
T205	0	36329	0	0

gen_filter_match[7].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34797592	196559	0	0
T16	0	2	0	0
T41	120735	2	0	0
T42	9359	0	0	0
T43	65291	0	0	0
T44	98974	0	0	0
T45	9034	0	0	0
T48	96730	32077	0	0
T104	884	0	0	0
T106	0	1	0	0
T131	97922	0	0	0
T132	97477	0	0	0
T133	6227	0	0	0
T136	0	1	0	0
T162	0	1	0	0
T174	0	1	0	0
T175	0	1	0	0
T186	0	1	0	0
T206	0	1	0	0

gen_filter_match[7].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34797592	21388986	0	0
T2	72186	72122	0	0
T3	1166	0	0	0
T5	66452	33832	0	0
T6	104304	33897	0	0
T7	836	0	0	0
T8	1174	0	0	0
T9	65886	33411	0	0
T10	32767	0	0	0
T11	89993	89934	0	0
T12	34601	34541	0	0
T13	0	10067	0	0
T14	0	73697	0	0
T41	0	120677	0	0
T43	0	65231	0	0