Unified Coverage Report :: Module :: prim_reg_cdc

Module : prim_reg_cdc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.37	100.00	89.49			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_adc_chn_val_0_cdc	78.29	94.12	85.71			83.33	50.00
tb.dut.u_reg.u_adc_chn_val_1_cdc	78.29	94.12	85.71			83.33	50.00
tb.dut.u_reg.u_filter_status_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_adc_fsm_state_cdc	96.43	100.00	85.71			100.00	100.00
tb.dut.u_reg.u_adc_en_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_adc_pd_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_adc_lp_sample_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_adc_sample_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_adc_wakeup_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_adc_fsm_rst_cdc	98.08	100.00	92.31			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn_val_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
78.29	94.12	85.71			83.33	50.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
78.01	95.31	67.24			89.47	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.92	100.00	99.70			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	87.67	94.90	67.39			88.37	100.00
u_src_to_dst_req	60.00	100.00	40.00			100.00	0.00

---

Module Instance : tb.dut.u_reg.u_adc_chn_val_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
78.29	94.12	85.71			83.33	50.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
78.01	95.31	67.24			89.47	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.92	100.00	99.70			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	87.67	94.90	67.39			88.37	100.00
u_src_to_dst_req	60.00	100.00	40.00			100.00	0.00

---

Module Instance : tb.dut.u_reg.u_filter_status_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.74	100.00	92.65			98.31	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.92	100.00	99.70			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.79	100.00	93.48			97.67	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_adc_fsm_state_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.72	98.44	79.69			94.74	90.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.92	100.00	99.70			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	86.03	97.87	78.57			92.68	75.00
u_src_to_dst_req	93.75	100.00	75.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_adc_en_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.92	100.00	99.70			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_adc_pd_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.92	100.00	99.70			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_adc_lp_sample_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.92	100.00	99.70			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_adc_sample_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.92	100.00	99.70			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.92	100.00	99.70			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.92	100.00	99.70			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.92	100.00	99.70			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.92	100.00	99.70			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.92	100.00	99.70			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.92	100.00	99.70			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.92	100.00	99.70			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.92	100.00	99.70			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.92	100.00	99.70			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.92	100.00	99.70			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.92	100.00	99.70			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.92	100.00	99.70			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.92	100.00	99.70			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.92	100.00	99.70			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.92	100.00	99.70			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.92	100.00	99.70			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_adc_wakeup_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.92	100.00	99.70			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_adc_fsm_rst_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.08	100.00	92.31			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.22	100.00	96.88			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.92	100.00	99.70			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Line Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Module : prim_reg_cdc ( parameter DataWidth=2,ResetVal=0,BitMask=3,DstWrReq=0,TxnWidth=3 + DataWidth=32,ResetVal,BitMask,DstWrReq=0,TxnWidth=3 + DataWidth=8,ResetVal=4,BitMask=255,DstWrReq=0,TxnWidth=3 + DataWidth=16,ResetVal=155,BitMask=65535,DstWrReq=0,TxnWidth=3 + DataWidth=28,ResetVal=0,BitMask=268374015,DstWrReq=1,TxnWidth=3 + DataWidth=9,ResetVal=0,BitMask=511,DstWrReq=0,TxnWidth=3 + DataWidth=9,ResetVal=0,BitMask=511,DstWrReq=1,TxnWidth=3 + DataWidth=5,ResetVal=0,BitMask=31,DstWrReq=1,TxnWidth=3 )
Cond Coverage for Module self-instances :

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_adc_en_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_adc_pd_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_adc_lp_sample_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_adc_sample_ctl_cdc

SCORE	COND
78.29	85.71

tb.dut.u_reg.u_adc_chn_val_0_cdc

SCORE	COND
78.29	85.71

tb.dut.u_reg.u_adc_chn_val_1_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_adc_wakeup_ctl_cdc

SCORE	COND
96.43	85.71

tb.dut.u_reg.u_filter_status_cdc

SCORE	COND
96.43	85.71

tb.dut.u_reg.u_adc_fsm_state_cdc

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Covered	T13,T16,T32
1	0	Covered	T1,T4,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T2

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_reg_cdc ( parameter DataWidth=1,ResetVal=0,BitMask=1,DstWrReq=0,TxnWidth=3 )
Cond Coverage for Module self-instances :

SCORE	COND
98.08	92.31

tb.dut.u_reg.u_adc_fsm_rst_cdc

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T1,T2,T5

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T5

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T5
1	-	Covered	T1,T2,T5

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T1,T2,T5

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T5

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T1,T4,T2
0	0	1	Covered	T1,T4,T2
0	0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T1,T4,T2
0	0	1	Covered	T1,T4,T2
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Module : prim_reg_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	198895924	0	0
DstReqKnown_A	907199722	897673686	0	0
SrcAckBusyChk_A	2147483647	218343	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	198895924	0	0
T1	2168516	464905	0	0
T2	16242192	20110	0	0
T3	10082484	67048	0	0
T4	154292	0	0	0
T5	5667480	64228	0	0
T6	17836056	20965	0	0
T7	2413476	16068	0	0
T8	10152324	69554	0	0
T9	5870556	70874	0	0
T10	6068214	7130	0	0
T11	2897832	37896	0	0
T12	2422140	26020	0	0
T13	391227	112876	0	0
T14	199243	32858	0	0
T15	331534	35353	0	0
T16	0	1340	0	0
T32	0	1218	0	0
T33	0	1693	0	0
T36	0	456324	0	0
T37	0	386	0	0
T38	0	1074	0	0
T39	0	2226	0	0
T40	270358	0	0	0
T41	543311	0	0	0
T42	234014	0	0	0
T43	326462	0	0	0
T44	469148	0	0	0
T45	361426	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	907199722	897673686	0	0
T1	563758	491504	0	0
T2	1876836	1875276	0	0
T3	30316	27950	0	0
T4	2002	130	0	0
T5	1727752	1725828	0	0
T6	2711904	2710292	0	0
T7	21736	19188	0	0
T8	30524	29224	0	0
T9	1713036	1710566	0	0
T10	851942	850278	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	218343	0	0
T1	2168516	529	0	0
T2	16242192	42	0	0
T3	10082484	41	0	0
T4	154292	0	0	0
T5	5667480	42	0	0
T6	17836056	63	0	0
T7	2413476	29	0	0
T8	10152324	41	0	0
T9	5870556	42	0	0
T10	6068214	21	0	0
T11	2897832	42	0	0
T12	2422140	18	0	0
T13	391227	130	0	0
T14	199243	42	0	0
T15	331534	28	0	0
T16	0	2	0	0
T32	0	1	0	0
T33	0	1	0	0
T36	0	270	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	270358	0	0	0
T41	543311	0	0	0
T42	234014	0	0	0
T43	326462	0	0	0
T44	469148	0	0	0
T45	361426	0	0	0
T46	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	14095354	14087892	0	0
T2	23460944	23460710	0	0
T3	14563588	14561612	0	0
T4	1002898	1001260	0	0
T5	8186360	8186334	0	0
T6	25763192	25763062	0	0
T7	3486132	3484754	0	0
T8	14664468	14662336	0	0
T9	8479692	8479666	0	0
T10	8765198	8764990	0	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		17	16	94.12
CONT_ASSIGN	54	0	0
ALWAYS	60	5	4	80.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	7	7	100.00
CONT_ASSIGN	139	0	0
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54		unreachable
60	1	1
61	1	1
62	1	1
63		unreachable
64	1	1
65	0	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112		unreachable
113		unreachable
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139		unreachable
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_0_cdc

	Total	Covered	Percent
Conditions	7	6	85.71
Logical	7	6	85.71
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Unreachable

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T4,T2
1	0	Excluded		VC_COV_UNR
1	1	Excluded		VC_COV_UNR

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests	Exclude Annotation
0	0	Covered	T1,T4,T2
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Not Covered
1	0	Excluded		VC_COV_UNR
1	1	Excluded		VC_COV_UNR

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T4,T2
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_0_cdc

	Line No.	Total	Covered	Percent
Branches		6	5	83.33
IF	60	3	2	66.67
IF	104	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Unreachable
0	0	1	Not Covered
0	0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Unreachable
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	2	50.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	2	50.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	0	0	0
DstReqKnown_A	34892297	34525911	0	0
SrcAckBusyChk_A	2147483647	0	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34892297	34525911	0	0
T1	21683	18904	0	0
T2	72186	72126	0	0
T3	1166	1075	0	0
T4	77	5	0	0
T5	66452	66378	0	0
T6	104304	104242	0	0
T7	836	738	0	0
T8	1174	1124	0	0
T9	65886	65791	0	0
T10	32767	32703	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	542129	541842	0	0
T2	902344	902335	0	0
T3	560138	560062	0	0
T4	38573	38510	0	0
T5	314860	314859	0	0
T6	990892	990887	0	0
T7	134082	134029	0	0
T8	564018	563936	0	0
T9	326142	326141	0	0
T10	337123	337115	0	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		17	16	94.12
CONT_ASSIGN	54	0	0
ALWAYS	60	5	4	80.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	7	7	100.00
CONT_ASSIGN	139	0	0
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54		unreachable
60	1	1
61	1	1
62	1	1
63		unreachable
64	1	1
65	0	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112		unreachable
113		unreachable
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139		unreachable
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_1_cdc

	Total	Covered	Percent
Conditions	7	6	85.71
Logical	7	6	85.71
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Unreachable

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T4,T2
1	0	Excluded		VC_COV_UNR
1	1	Excluded		VC_COV_UNR

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests	Exclude Annotation
0	0	Covered	T1,T4,T2
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Not Covered
1	0	Excluded		VC_COV_UNR
1	1	Excluded		VC_COV_UNR

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T4,T2
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_1_cdc

	Line No.	Total	Covered	Percent
Branches		6	5	83.33
IF	60	3	2	66.67
IF	104	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Unreachable
0	0	1	Not Covered
0	0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Unreachable
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	2	50.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	2	50.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	0	0	0
DstReqKnown_A	34892297	34525911	0	0
SrcAckBusyChk_A	2147483647	0	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34892297	34525911	0	0
T1	21683	18904	0	0
T2	72186	72126	0	0
T3	1166	1075	0	0
T4	77	5	0	0
T5	66452	66378	0	0
T6	104304	104242	0	0
T7	836	738	0	0
T8	1174	1124	0	0
T9	65886	65791	0	0
T10	32767	32703	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	542129	541842	0	0
T2	902344	902335	0	0
T3	560138	560062	0	0
T4	38573	38510	0	0
T5	314860	314859	0	0
T6	990892	990887	0	0
T7	134082	134029	0	0
T8	564018	563936	0	0
T9	326142	326141	0	0
T10	337123	337115	0	0

Line Coverage for Instance : tb.dut.u_reg.u_filter_status_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_filter_status_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T2,T5,T6

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T2,T5,T6
1	1	Covered	T2,T5,T6

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Covered	T2,T5,T6
1	0	Covered	T2,T5,T6

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T5,T6
1	1	Covered	T2,T5,T6

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Not Covered
1	1	Covered	T2,T5,T6

---

Branch Coverage for Instance : tb.dut.u_reg.u_filter_status_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T2,T5,T6
0	0	1	Covered	T2,T5,T6
0	0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T2,T5,T6
0	0	1	Covered	T2,T5,T6
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_filter_status_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	66706538	0	0
DstReqKnown_A	34892297	34525911	0	0
SrcAckBusyChk_A	2147483647	69776	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	66706538	0	0
T2	902344	55309	0	0
T3	560138	0	0	0
T5	314860	247480	0	0
T6	990892	77371	0	0
T7	134082	0	0	0
T8	564018	0	0	0
T9	326142	269856	0	0
T10	337123	26177	0	0
T11	206988	108026	0	0
T12	173010	137839	0	0
T13	0	13067	0	0
T14	0	152217	0	0
T15	0	206880	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34892297	34525911	0	0
T1	21683	18904	0	0
T2	72186	72126	0	0
T3	1166	1075	0	0
T4	77	5	0	0
T5	66452	66378	0	0
T6	104304	104242	0	0
T7	836	738	0	0
T8	1174	1124	0	0
T9	65886	65791	0	0
T10	32767	32703	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	69776	0	0
T2	902344	127	0	0
T3	560138	0	0	0
T5	314860	149	0	0
T6	990892	230	0	0
T7	134082	0	0	0
T8	564018	0	0	0
T9	326142	162	0	0
T10	337123	60	0	0
T11	206988	133	0	0
T12	173010	78	0	0
T13	0	15	0	0
T14	0	184	0	0
T15	0	157	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	542129	541842	0	0
T2	902344	902335	0	0
T3	560138	560062	0	0
T4	38573	38510	0	0
T5	314860	314859	0	0
T6	990892	990887	0	0
T7	134082	134029	0	0
T8	564018	563936	0	0
T9	326142	326141	0	0
T10	337123	337115	0	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_fsm_state_cdc

	Line No.	Total	Covered	Percent
TOTAL		21	21	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	0	0
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139		unreachable
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_adc_fsm_state_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Covered	T13,T16,T32
1	0	Unreachable

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T13,T16,T32
1	1	Covered	T13,T16,T32

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Covered	T1,T2,T3
1	0	Covered	T13,T16,T32

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T13,T16,T32
1	1	Covered	T13,T16,T32

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_adc_fsm_state_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T13,T16,T32
0	0	1	Covered	T13,T16,T32
0	0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T13,T16,T32
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_adc_fsm_state_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	98894	0	0
DstReqKnown_A	34892297	34525911	0	0
SrcAckBusyChk_A	2147483647	95	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	98894	0	0
T13	391227	1627	0	0
T14	199243	0	0	0
T15	331534	0	0	0
T16	0	1340	0	0
T17	0	478	0	0
T32	0	1218	0	0
T33	0	1693	0	0
T37	0	386	0	0
T38	0	1074	0	0
T39	0	2226	0	0
T40	270358	0	0	0
T41	543311	0	0	0
T42	234014	0	0	0
T43	326462	0	0	0
T44	469148	0	0	0
T45	361426	0	0	0
T46	0	1956	0	0
T47	0	1116	0	0
T48	464292	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34892297	34525911	0	0
T1	21683	18904	0	0
T2	72186	72126	0	0
T3	1166	1075	0	0
T4	77	5	0	0
T5	66452	66378	0	0
T6	104304	104242	0	0
T7	836	738	0	0
T8	1174	1124	0	0
T9	65886	65791	0	0
T10	32767	32703	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	95	0	0
T13	391227	1	0	0
T14	199243	0	0	0
T15	331534	0	0	0
T16	0	2	0	0
T18	0	1	0	0
T32	0	1	0	0
T33	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	270358	0	0	0
T41	543311	0	0	0
T42	234014	0	0	0
T43	326462	0	0	0
T44	469148	0	0	0
T45	361426	0	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	464292	0	0	0
T49	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	542129	541842	0	0
T2	902344	902335	0	0
T3	560138	560062	0	0
T4	38573	38510	0	0
T5	314860	314859	0	0
T6	990892	990887	0	0
T7	134082	134029	0	0
T8	564018	563936	0	0
T9	326142	326141	0	0
T10	337123	337115	0	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_en_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_adc_en_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_adc_en_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_adc_en_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	36934375	0	0
DstReqKnown_A	34892297	34525911	0	0
SrcAckBusyChk_A	2147483647	41025	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	36934375	0	0
T1	542129	268127	0	0
T2	902344	2744	0	0
T3	560138	67048	0	0
T4	38573	0	0	0
T5	314860	6708	0	0
T6	990892	3031	0	0
T7	134082	16068	0	0
T8	564018	69554	0	0
T9	326142	10370	0	0
T10	337123	804	0	0
T11	0	5284	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34892297	34525911	0	0
T1	21683	18904	0	0
T2	72186	72126	0	0
T3	1166	1075	0	0
T4	77	5	0	0
T5	66452	66378	0	0
T6	104304	104242	0	0
T7	836	738	0	0
T8	1174	1124	0	0
T9	65886	65791	0	0
T10	32767	32703	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	41025	0	0
T1	542129	307	0	0
T2	902344	6	0	0
T3	560138	41	0	0
T4	38573	0	0	0
T5	314860	6	0	0
T6	990892	9	0	0
T7	134082	29	0	0
T8	564018	41	0	0
T9	326142	6	0	0
T10	337123	3	0	0
T11	0	6	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	542129	541842	0	0
T2	902344	902335	0	0
T3	560138	560062	0	0
T4	38573	38510	0	0
T5	314860	314859	0	0
T6	990892	990887	0	0
T7	134082	134029	0	0
T8	564018	563936	0	0
T9	326142	326141	0	0
T10	337123	337115	0	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_pd_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_adc_pd_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_adc_pd_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_adc_pd_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	16756705	0	0
DstReqKnown_A	34892297	34525911	0	0
SrcAckBusyChk_A	2147483647	19235	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	16756705	0	0
T1	542129	133266	0	0
T2	902344	1796	0	0
T3	560138	1435	0	0
T4	38573	0	0	0
T5	314860	2986	0	0
T6	990892	1876	0	0
T7	134082	7671	0	0
T8	564018	1898	0	0
T9	326142	6647	0	0
T10	337123	385	0	0
T11	0	3601	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34892297	34525911	0	0
T1	21683	18904	0	0
T2	72186	72126	0	0
T3	1166	1075	0	0
T4	77	5	0	0
T5	66452	66378	0	0
T6	104304	104242	0	0
T7	836	738	0	0
T8	1174	1124	0	0
T9	65886	65791	0	0
T10	32767	32703	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	19235	0	0
T1	542129	153	0	0
T2	902344	4	0	0
T3	560138	1	0	0
T4	38573	0	0	0
T5	314860	4	0	0
T6	990892	6	0	0
T7	134082	14	0	0
T8	564018	1	0	0
T9	326142	4	0	0
T10	337123	2	0	0
T11	0	4	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	542129	541842	0	0
T2	902344	902335	0	0
T3	560138	560062	0	0
T4	38573	38510	0	0
T5	314860	314859	0	0
T6	990892	990887	0	0
T7	134082	134029	0	0
T8	564018	563936	0	0
T9	326142	326141	0	0
T10	337123	337115	0	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_lp_sample_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_adc_lp_sample_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T1,T4,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T1,T4,T2

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_adc_lp_sample_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T1,T4,T2
0	0	1	Covered	T1,T4,T2
0	0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T1,T4,T2
0	0	1	Covered	T1,T4,T2
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_adc_lp_sample_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	13458238	0	0
DstReqKnown_A	34892297	34525911	0	0
SrcAckBusyChk_A	2147483647	15272	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	13458238	0	0
T1	542129	132489	0	0
T2	902344	930	0	0
T3	560138	0	0	0
T4	38573	1249	0	0
T5	314860	2981	0	0
T6	990892	939	0	0
T7	134082	0	0	0
T8	564018	0	0	0
T9	326142	3204	0	0
T10	337123	373	0	0
T11	0	1770	0	0
T12	0	1316	0	0
T36	0	281771	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34892297	34525911	0	0
T1	21683	18904	0	0
T2	72186	72126	0	0
T3	1166	1075	0	0
T4	77	5	0	0
T5	66452	66378	0	0
T6	104304	104242	0	0
T7	836	738	0	0
T8	1174	1124	0	0
T9	65886	65791	0	0
T10	32767	32703	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	15272	0	0
T1	542129	154	0	0
T2	902344	2	0	0
T3	560138	0	0	0
T4	38573	1	0	0
T5	314860	2	0	0
T6	990892	3	0	0
T7	134082	0	0	0
T8	564018	0	0	0
T9	326142	2	0	0
T10	337123	1	0	0
T11	0	2	0	0
T12	0	1	0	0
T36	0	170	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	542129	541842	0	0
T2	902344	902335	0	0
T3	560138	560062	0	0
T4	38573	38510	0	0
T5	314860	314859	0	0
T6	990892	990887	0	0
T7	134082	134029	0	0
T8	564018	563936	0	0
T9	326142	326141	0	0
T10	337123	337115	0	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_sample_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_adc_sample_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T1,T4,T2

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T1,T4,T2

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_adc_sample_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T1,T4,T2
0	0	1	Covered	T1,T4,T2
0	0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T1,T4,T2
0	0	1	Covered	T1,T4,T2
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_adc_sample_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	13594774	0	0
DstReqKnown_A	34892297	34525911	0	0
SrcAckBusyChk_A	2147483647	15305	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	13594774	0	0
T1	542129	132797	0	0
T2	902344	934	0	0
T3	560138	0	0	0
T4	38573	1259	0	0
T5	314860	3001	0	0
T6	990892	945	0	0
T7	134082	0	0	0
T8	564018	0	0	0
T9	326142	3224	0	0
T10	337123	375	0	0
T11	0	1774	0	0
T12	0	1324	0	0
T36	0	283249	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34892297	34525911	0	0
T1	21683	18904	0	0
T2	72186	72126	0	0
T3	1166	1075	0	0
T4	77	5	0	0
T5	66452	66378	0	0
T6	104304	104242	0	0
T7	836	738	0	0
T8	1174	1124	0	0
T9	65886	65791	0	0
T10	32767	32703	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	15305	0	0
T1	542129	154	0	0
T2	902344	2	0	0
T3	560138	0	0	0
T4	38573	1	0	0
T5	314860	2	0	0
T6	990892	3	0	0
T7	134082	0	0	0
T8	564018	0	0	0
T9	326142	2	0	0
T10	337123	1	0	0
T11	0	2	0	0
T12	0	1	0	0
T36	0	170	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	542129	541842	0	0
T2	902344	902335	0	0
T3	560138	560062	0	0
T4	38573	38510	0	0
T5	314860	314859	0	0
T6	990892	990887	0	0
T7	134082	134029	0	0
T8	564018	563936	0	0
T9	326142	326141	0	0
T10	337123	337115	0	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T1,T2,T5

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T5

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T1,T2,T5

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T5

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T1,T2,T5
0	0	1	Covered	T1,T2,T5
0	0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T1,T2,T5
0	0	1	Covered	T1,T2,T5
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	2075704	0	0
DstReqKnown_A	34892297	34525911	0	0
SrcAckBusyChk_A	2147483647	2311	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2075704	0	0
T1	542129	748	0	0
T2	902344	998	0	0
T3	560138	0	0	0
T4	38573	0	0	0
T5	314860	3326	0	0
T6	990892	1041	0	0
T7	134082	0	0	0
T8	564018	0	0	0
T9	326142	3454	0	0
T10	337123	383	0	0
T11	0	1838	0	0
T12	0	1486	0	0
T13	0	7166	0	0
T36	0	1909	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34892297	34525911	0	0
T1	21683	18904	0	0
T2	72186	72126	0	0
T3	1166	1075	0	0
T4	77	5	0	0
T5	66452	66378	0	0
T6	104304	104242	0	0
T7	836	738	0	0
T8	1174	1124	0	0
T9	65886	65791	0	0
T10	32767	32703	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2311	0	0
T1	542129	1	0	0
T2	902344	2	0	0
T3	560138	0	0	0
T4	38573	0	0	0
T5	314860	2	0	0
T6	990892	3	0	0
T7	134082	0	0	0
T8	564018	0	0	0
T9	326142	2	0	0
T10	337123	1	0	0
T11	0	2	0	0
T12	0	1	0	0
T13	0	8	0	0
T36	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	542129	541842	0	0
T2	902344	902335	0	0
T3	560138	560062	0	0
T4	38573	38510	0	0
T5	314860	314859	0	0
T6	990892	990887	0	0
T7	134082	134029	0	0
T8	564018	563936	0	0
T9	326142	326141	0	0
T10	337123	337115	0	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T2,T5,T6

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T2,T5,T6
1	1	Covered	T2,T5,T6

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T2,T5,T6

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T5,T6
1	1	Covered	T2,T5,T6

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T2,T5,T6
0	0	1	Covered	T2,T5,T6
0	0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T2,T5,T6
0	0	1	Covered	T2,T5,T6
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	1926212	0	0
DstReqKnown_A	34892297	34525911	0	0
SrcAckBusyChk_A	2147483647	2141	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1926212	0	0
T2	902344	994	0	0
T3	560138	0	0	0
T5	314860	3306	0	0
T6	990892	1035	0	0
T7	134082	0	0	0
T8	564018	0	0	0
T9	326142	3439	0	0
T10	337123	368	0	0
T11	206988	1834	0	0
T12	173010	1480	0	0
T13	0	6355	0	0
T14	0	2389	0	0
T15	0	2624	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34892297	34525911	0	0
T1	21683	18904	0	0
T2	72186	72126	0	0
T3	1166	1075	0	0
T4	77	5	0	0
T5	66452	66378	0	0
T6	104304	104242	0	0
T7	836	738	0	0
T8	1174	1124	0	0
T9	65886	65791	0	0
T10	32767	32703	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2141	0	0
T2	902344	2	0	0
T3	560138	0	0	0
T5	314860	2	0	0
T6	990892	3	0	0
T7	134082	0	0	0
T8	564018	0	0	0
T9	326142	2	0	0
T10	337123	1	0	0
T11	206988	2	0	0
T12	173010	1	0	0
T13	0	7	0	0
T14	0	3	0	0
T15	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	542129	541842	0	0
T2	902344	902335	0	0
T3	560138	560062	0	0
T4	38573	38510	0	0
T5	314860	314859	0	0
T6	990892	990887	0	0
T7	134082	134029	0	0
T8	564018	563936	0	0
T9	326142	326141	0	0
T10	337123	337115	0	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T2,T5,T6

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T2,T5,T6
1	1	Covered	T2,T5,T6

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T2,T5,T6

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T5,T6
1	1	Covered	T2,T5,T6

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T2,T5,T6
0	0	1	Covered	T2,T5,T6
0	0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T2,T5,T6
0	0	1	Covered	T2,T5,T6
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	1905090	0	0
DstReqKnown_A	34892297	34525911	0	0
SrcAckBusyChk_A	2147483647	2128	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1905090	0	0
T2	902344	990	0	0
T3	560138	0	0	0
T5	314860	3288	0	0
T6	990892	1029	0	0
T7	134082	0	0	0
T8	564018	0	0	0
T9	326142	3425	0	0
T10	337123	364	0	0
T11	206988	1830	0	0
T12	173010	1471	0	0
T13	0	6294	0	0
T14	0	2383	0	0
T15	0	2612	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34892297	34525911	0	0
T1	21683	18904	0	0
T2	72186	72126	0	0
T3	1166	1075	0	0
T4	77	5	0	0
T5	66452	66378	0	0
T6	104304	104242	0	0
T7	836	738	0	0
T8	1174	1124	0	0
T9	65886	65791	0	0
T10	32767	32703	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2128	0	0
T2	902344	2	0	0
T3	560138	0	0	0
T5	314860	2	0	0
T6	990892	3	0	0
T7	134082	0	0	0
T8	564018	0	0	0
T9	326142	2	0	0
T10	337123	1	0	0
T11	206988	2	0	0
T12	173010	1	0	0
T13	0	7	0	0
T14	0	3	0	0
T15	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	542129	541842	0	0
T2	902344	902335	0	0
T3	560138	560062	0	0
T4	38573	38510	0	0
T5	314860	314859	0	0
T6	990892	990887	0	0
T7	134082	134029	0	0
T8	564018	563936	0	0
T9	326142	326141	0	0
T10	337123	337115	0	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T2,T5,T6

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T2,T5,T6
1	1	Covered	T2,T5,T6

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T2,T5,T6

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T5,T6
1	1	Covered	T2,T5,T6

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T2,T5,T6
0	0	1	Covered	T2,T5,T6
0	0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T2,T5,T6
0	0	1	Covered	T2,T5,T6
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	1935332	0	0
DstReqKnown_A	34892297	34525911	0	0
SrcAckBusyChk_A	2147483647	2163	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1935332	0	0
T2	902344	986	0	0
T3	560138	0	0	0
T5	314860	3278	0	0
T6	990892	1023	0	0
T7	134082	0	0	0
T8	564018	0	0	0
T9	326142	3410	0	0
T10	337123	353	0	0
T11	206988	1826	0	0
T12	173010	1461	0	0
T13	0	6239	0	0
T14	0	2377	0	0
T15	0	2595	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34892297	34525911	0	0
T1	21683	18904	0	0
T2	72186	72126	0	0
T3	1166	1075	0	0
T4	77	5	0	0
T5	66452	66378	0	0
T6	104304	104242	0	0
T7	836	738	0	0
T8	1174	1124	0	0
T9	65886	65791	0	0
T10	32767	32703	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2163	0	0
T2	902344	2	0	0
T3	560138	0	0	0
T5	314860	2	0	0
T6	990892	3	0	0
T7	134082	0	0	0
T8	564018	0	0	0
T9	326142	2	0	0
T10	337123	1	0	0
T11	206988	2	0	0
T12	173010	1	0	0
T13	0	7	0	0
T14	0	3	0	0
T15	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	542129	541842	0	0
T2	902344	902335	0	0
T3	560138	560062	0	0
T4	38573	38510	0	0
T5	314860	314859	0	0
T6	990892	990887	0	0
T7	134082	134029	0	0
T8	564018	563936	0	0
T9	326142	326141	0	0
T10	337123	337115	0	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T2,T5,T6

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T2,T5,T6
1	1	Covered	T2,T5,T6

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T2,T5,T6

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T5,T6
1	1	Covered	T2,T5,T6

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T2,T5,T6
0	0	1	Covered	T2,T5,T6
0	0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T2,T5,T6
0	0	1	Covered	T2,T5,T6
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	1876282	0	0
DstReqKnown_A	34892297	34525911	0	0
SrcAckBusyChk_A	2147483647	2126	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1876282	0	0
T2	902344	982	0	0
T3	560138	0	0	0
T5	314860	3257	0	0
T6	990892	1017	0	0
T7	134082	0	0	0
T8	564018	0	0	0
T9	326142	3389	0	0
T10	337123	339	0	0
T11	206988	1822	0	0
T12	173010	1450	0	0
T13	0	6192	0	0
T14	0	2371	0	0
T15	0	2580	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34892297	34525911	0	0
T1	21683	18904	0	0
T2	72186	72126	0	0
T3	1166	1075	0	0
T4	77	5	0	0
T5	66452	66378	0	0
T6	104304	104242	0	0
T7	836	738	0	0
T8	1174	1124	0	0
T9	65886	65791	0	0
T10	32767	32703	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2126	0	0
T2	902344	2	0	0
T3	560138	0	0	0
T5	314860	2	0	0
T6	990892	3	0	0
T7	134082	0	0	0
T8	564018	0	0	0
T9	326142	2	0	0
T10	337123	1	0	0
T11	206988	2	0	0
T12	173010	1	0	0
T13	0	7	0	0
T14	0	3	0	0
T15	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	542129	541842	0	0
T2	902344	902335	0	0
T3	560138	560062	0	0
T4	38573	38510	0	0
T5	314860	314859	0	0
T6	990892	990887	0	0
T7	134082	134029	0	0
T8	564018	563936	0	0
T9	326142	326141	0	0
T10	337123	337115	0	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T2,T5,T6

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T2,T5,T6
1	1	Covered	T2,T5,T6

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T2,T5,T6

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T5,T6
1	1	Covered	T2,T5,T6

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T2,T5,T6
0	0	1	Covered	T2,T5,T6
0	0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T2,T5,T6
0	0	1	Covered	T2,T5,T6
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	1970435	0	0
DstReqKnown_A	34892297	34525911	0	0
SrcAckBusyChk_A	2147483647	2210	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1970435	0	0
T2	902344	978	0	0
T3	560138	0	0	0
T5	314860	3230	0	0
T6	990892	1011	0	0
T7	134082	0	0	0
T8	564018	0	0	0
T9	326142	3383	0	0
T10	337123	326	0	0
T11	206988	1818	0	0
T12	173010	1438	0	0
T13	0	6139	0	0
T14	0	2365	0	0
T15	0	2568	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34892297	34525911	0	0
T1	21683	18904	0	0
T2	72186	72126	0	0
T3	1166	1075	0	0
T4	77	5	0	0
T5	66452	66378	0	0
T6	104304	104242	0	0
T7	836	738	0	0
T8	1174	1124	0	0
T9	65886	65791	0	0
T10	32767	32703	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2210	0	0
T2	902344	2	0	0
T3	560138	0	0	0
T5	314860	2	0	0
T6	990892	3	0	0
T7	134082	0	0	0
T8	564018	0	0	0
T9	326142	2	0	0
T10	337123	1	0	0
T11	206988	2	0	0
T12	173010	1	0	0
T13	0	7	0	0
T14	0	3	0	0
T15	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	542129	541842	0	0
T2	902344	902335	0	0
T3	560138	560062	0	0
T4	38573	38510	0	0
T5	314860	314859	0	0
T6	990892	990887	0	0
T7	134082	134029	0	0
T8	564018	563936	0	0
T9	326142	326141	0	0
T10	337123	337115	0	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T2,T5,T6

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T2,T5,T6
1	1	Covered	T2,T5,T6

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T2,T5,T6

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T5,T6
1	1	Covered	T2,T5,T6

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T2,T5,T6
0	0	1	Covered	T2,T5,T6
0	0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T2,T5,T6
0	0	1	Covered	T2,T5,T6
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	1904341	0	0
DstReqKnown_A	34892297	34525911	0	0
SrcAckBusyChk_A	2147483647	2163	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1904341	0	0
T2	902344	974	0	0
T3	560138	0	0	0
T5	314860	3207	0	0
T6	990892	1005	0	0
T7	134082	0	0	0
T8	564018	0	0	0
T9	326142	3371	0	0
T10	337123	318	0	0
T11	206988	1814	0	0
T12	173010	1420	0	0
T13	0	6091	0	0
T14	0	2359	0	0
T15	0	2552	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34892297	34525911	0	0
T1	21683	18904	0	0
T2	72186	72126	0	0
T3	1166	1075	0	0
T4	77	5	0	0
T5	66452	66378	0	0
T6	104304	104242	0	0
T7	836	738	0	0
T8	1174	1124	0	0
T9	65886	65791	0	0
T10	32767	32703	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2163	0	0
T2	902344	2	0	0
T3	560138	0	0	0
T5	314860	2	0	0
T6	990892	3	0	0
T7	134082	0	0	0
T8	564018	0	0	0
T9	326142	2	0	0
T10	337123	1	0	0
T11	206988	2	0	0
T12	173010	1	0	0
T13	0	7	0	0
T14	0	3	0	0
T15	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	542129	541842	0	0
T2	902344	902335	0	0
T3	560138	560062	0	0
T4	38573	38510	0	0
T5	314860	314859	0	0
T6	990892	990887	0	0
T7	134082	134029	0	0
T8	564018	563936	0	0
T9	326142	326141	0	0
T10	337123	337115	0	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T2,T5,T6

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T2,T5,T6
1	1	Covered	T2,T5,T6

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T2,T5,T6

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T5,T6
1	1	Covered	T2,T5,T6

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T2,T5,T6
0	0	1	Covered	T2,T5,T6
0	0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T2,T5,T6
0	0	1	Covered	T2,T5,T6
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	1884912	0	0
DstReqKnown_A	34892297	34525911	0	0
SrcAckBusyChk_A	2147483647	2148	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1884912	0	0
T2	902344	970	0	0
T3	560138	0	0	0
T5	314860	3190	0	0
T6	990892	999	0	0
T7	134082	0	0	0
T8	564018	0	0	0
T9	326142	3357	0	0
T10	337123	309	0	0
T11	206988	1810	0	0
T12	173010	1417	0	0
T13	0	6044	0	0
T14	0	2353	0	0
T15	0	2531	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34892297	34525911	0	0
T1	21683	18904	0	0
T2	72186	72126	0	0
T3	1166	1075	0	0
T4	77	5	0	0
T5	66452	66378	0	0
T6	104304	104242	0	0
T7	836	738	0	0
T8	1174	1124	0	0
T9	65886	65791	0	0
T10	32767	32703	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2148	0	0
T2	902344	2	0	0
T3	560138	0	0	0
T5	314860	2	0	0
T6	990892	3	0	0
T7	134082	0	0	0
T8	564018	0	0	0
T9	326142	2	0	0
T10	337123	1	0	0
T11	206988	2	0	0
T12	173010	1	0	0
T13	0	7	0	0
T14	0	3	0	0
T15	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	542129	541842	0	0
T2	902344	902335	0	0
T3	560138	560062	0	0
T4	38573	38510	0	0
T5	314860	314859	0	0
T6	990892	990887	0	0
T7	134082	134029	0	0
T8	564018	563936	0	0
T9	326142	326141	0	0
T10	337123	337115	0	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T1,T2,T5

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T5

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T1,T2,T5

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T5

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T1,T2,T5
0	0	1	Covered	T1,T2,T5
0	0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T1,T2,T5
0	0	1	Covered	T1,T2,T5
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	1985660	0	0
DstReqKnown_A	34892297	34525911	0	0
SrcAckBusyChk_A	2147483647	2258	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1985660	0	0
T1	542129	746	0	0
T2	902344	966	0	0
T3	560138	0	0	0
T4	38573	0	0	0
T5	314860	3165	0	0
T6	990892	993	0	0
T7	134082	0	0	0
T8	564018	0	0	0
T9	326142	3351	0	0
T10	337123	299	0	0
T11	0	1806	0	0
T12	0	1399	0	0
T13	0	6733	0	0
T36	0	1902	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34892297	34525911	0	0
T1	21683	18904	0	0
T2	72186	72126	0	0
T3	1166	1075	0	0
T4	77	5	0	0
T5	66452	66378	0	0
T6	104304	104242	0	0
T7	836	738	0	0
T8	1174	1124	0	0
T9	65886	65791	0	0
T10	32767	32703	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2258	0	0
T1	542129	1	0	0
T2	902344	2	0	0
T3	560138	0	0	0
T4	38573	0	0	0
T5	314860	2	0	0
T6	990892	3	0	0
T7	134082	0	0	0
T8	564018	0	0	0
T9	326142	2	0	0
T10	337123	1	0	0
T11	0	2	0	0
T12	0	1	0	0
T13	0	8	0	0
T36	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	542129	541842	0	0
T2	902344	902335	0	0
T3	560138	560062	0	0
T4	38573	38510	0	0
T5	314860	314859	0	0
T6	990892	990887	0	0
T7	134082	134029	0	0
T8	564018	563936	0	0
T9	326142	326141	0	0
T10	337123	337115	0	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T2,T5,T6

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T2,T5,T6
1	1	Covered	T2,T5,T6

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T2,T5,T6

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T5,T6
1	1	Covered	T2,T5,T6

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T2,T5,T6
0	0	1	Covered	T2,T5,T6
0	0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T2,T5,T6
0	0	1	Covered	T2,T5,T6
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	1869127	0	0
DstReqKnown_A	34892297	34525911	0	0
SrcAckBusyChk_A	2147483647	2134	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1869127	0	0
T2	902344	962	0	0
T3	560138	0	0	0
T5	314860	3149	0	0
T6	990892	987	0	0
T7	134082	0	0	0
T8	564018	0	0	0
T9	326142	3339	0	0
T10	337123	297	0	0
T11	206988	1802	0	0
T12	173010	1381	0	0
T13	0	5951	0	0
T14	0	2341	0	0
T15	0	2510	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34892297	34525911	0	0
T1	21683	18904	0	0
T2	72186	72126	0	0
T3	1166	1075	0	0
T4	77	5	0	0
T5	66452	66378	0	0
T6	104304	104242	0	0
T7	836	738	0	0
T8	1174	1124	0	0
T9	65886	65791	0	0
T10	32767	32703	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2134	0	0
T2	902344	2	0	0
T3	560138	0	0	0
T5	314860	2	0	0
T6	990892	3	0	0
T7	134082	0	0	0
T8	564018	0	0	0
T9	326142	2	0	0
T10	337123	1	0	0
T11	206988	2	0	0
T12	173010	1	0	0
T13	0	7	0	0
T14	0	3	0	0
T15	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	542129	541842	0	0
T2	902344	902335	0	0
T3	560138	560062	0	0
T4	38573	38510	0	0
T5	314860	314859	0	0
T6	990892	990887	0	0
T7	134082	134029	0	0
T8	564018	563936	0	0
T9	326142	326141	0	0
T10	337123	337115	0	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T2,T5,T6

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T2,T5,T6
1	1	Covered	T2,T5,T6

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T2,T5,T6

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T5,T6
1	1	Covered	T2,T5,T6

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T2,T5,T6
0	0	1	Covered	T2,T5,T6
0	0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T2,T5,T6
0	0	1	Covered	T2,T5,T6
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	1887298	0	0
DstReqKnown_A	34892297	34525911	0	0
SrcAckBusyChk_A	2147483647	2149	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1887298	0	0
T2	902344	958	0	0
T3	560138	0	0	0
T5	314860	3126	0	0
T6	990892	981	0	0
T7	134082	0	0	0
T8	564018	0	0	0
T9	326142	3322	0	0
T10	337123	290	0	0
T11	206988	1798	0	0
T12	173010	1371	0	0
T13	0	5891	0	0
T14	0	2335	0	0
T15	0	2493	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34892297	34525911	0	0
T1	21683	18904	0	0
T2	72186	72126	0	0
T3	1166	1075	0	0
T4	77	5	0	0
T5	66452	66378	0	0
T6	104304	104242	0	0
T7	836	738	0	0
T8	1174	1124	0	0
T9	65886	65791	0	0
T10	32767	32703	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2149	0	0
T2	902344	2	0	0
T3	560138	0	0	0
T5	314860	2	0	0
T6	990892	3	0	0
T7	134082	0	0	0
T8	564018	0	0	0
T9	326142	2	0	0
T10	337123	1	0	0
T11	206988	2	0	0
T12	173010	1	0	0
T13	0	7	0	0
T14	0	3	0	0
T15	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	542129	541842	0	0
T2	902344	902335	0	0
T3	560138	560062	0	0
T4	38573	38510	0	0
T5	314860	314859	0	0
T6	990892	990887	0	0
T7	134082	134029	0	0
T8	564018	563936	0	0
T9	326142	326141	0	0
T10	337123	337115	0	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T2,T5,T6

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T2,T5,T6
1	1	Covered	T2,T5,T6

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T2,T5,T6

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T5,T6
1	1	Covered	T2,T5,T6

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T2,T5,T6
0	0	1	Covered	T2,T5,T6
0	0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T2,T5,T6
0	0	1	Covered	T2,T5,T6
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	1888370	0	0
DstReqKnown_A	34892297	34525911	0	0
SrcAckBusyChk_A	2147483647	2156	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1888370	0	0
T2	902344	954	0	0
T3	560138	0	0	0
T5	314860	3102	0	0
T6	990892	975	0	0
T7	134082	0	0	0
T8	564018	0	0	0
T9	326142	3305	0	0
T10	337123	281	0	0
T11	206988	1794	0	0
T12	173010	1366	0	0
T13	0	5840	0	0
T14	0	2329	0	0
T15	0	2488	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34892297	34525911	0	0
T1	21683	18904	0	0
T2	72186	72126	0	0
T3	1166	1075	0	0
T4	77	5	0	0
T5	66452	66378	0	0
T6	104304	104242	0	0
T7	836	738	0	0
T8	1174	1124	0	0
T9	65886	65791	0	0
T10	32767	32703	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2156	0	0
T2	902344	2	0	0
T3	560138	0	0	0
T5	314860	2	0	0
T6	990892	3	0	0
T7	134082	0	0	0
T8	564018	0	0	0
T9	326142	2	0	0
T10	337123	1	0	0
T11	206988	2	0	0
T12	173010	1	0	0
T13	0	7	0	0
T14	0	3	0	0
T15	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	542129	541842	0	0
T2	902344	902335	0	0
T3	560138	560062	0	0
T4	38573	38510	0	0
T5	314860	314859	0	0
T6	990892	990887	0	0
T7	134082	134029	0	0
T8	564018	563936	0	0
T9	326142	326141	0	0
T10	337123	337115	0	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T2,T5,T6

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T2,T5,T6
1	1	Covered	T2,T5,T6

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T2,T5,T6

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T5,T6
1	1	Covered	T2,T5,T6

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T2,T5,T6
0	0	1	Covered	T2,T5,T6
0	0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T2,T5,T6
0	0	1	Covered	T2,T5,T6
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	1884940	0	0
DstReqKnown_A	34892297	34525911	0	0
SrcAckBusyChk_A	2147483647	2140	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1884940	0	0
T2	902344	950	0	0
T3	560138	0	0	0
T5	314860	3078	0	0
T6	990892	969	0	0
T7	134082	0	0	0
T8	564018	0	0	0
T9	326142	3293	0	0
T10	337123	276	0	0
T11	206988	1790	0	0
T12	173010	1355	0	0
T13	0	5786	0	0
T14	0	2323	0	0
T15	0	2476	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34892297	34525911	0	0
T1	21683	18904	0	0
T2	72186	72126	0	0
T3	1166	1075	0	0
T4	77	5	0	0
T5	66452	66378	0	0
T6	104304	104242	0	0
T7	836	738	0	0
T8	1174	1124	0	0
T9	65886	65791	0	0
T10	32767	32703	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2140	0	0
T2	902344	2	0	0
T3	560138	0	0	0
T5	314860	2	0	0
T6	990892	3	0	0
T7	134082	0	0	0
T8	564018	0	0	0
T9	326142	2	0	0
T10	337123	1	0	0
T11	206988	2	0	0
T12	173010	1	0	0
T13	0	7	0	0
T14	0	3	0	0
T15	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	542129	541842	0	0
T2	902344	902335	0	0
T3	560138	560062	0	0
T4	38573	38510	0	0
T5	314860	314859	0	0
T6	990892	990887	0	0
T7	134082	134029	0	0
T8	564018	563936	0	0
T9	326142	326141	0	0
T10	337123	337115	0	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T2,T5,T6

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T2,T5,T6
1	1	Covered	T2,T5,T6

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T2,T5,T6

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T5,T6
1	1	Covered	T2,T5,T6

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T2,T5,T6
0	0	1	Covered	T2,T5,T6
0	0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T2,T5,T6
0	0	1	Covered	T2,T5,T6
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	1876777	0	0
DstReqKnown_A	34892297	34525911	0	0
SrcAckBusyChk_A	2147483647	2159	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1876777	0	0
T2	902344	946	0	0
T3	560138	0	0	0
T5	314860	3059	0	0
T6	990892	963	0	0
T7	134082	0	0	0
T8	564018	0	0	0
T9	326142	3270	0	0
T10	337123	404	0	0
T11	206988	1786	0	0
T12	173010	1353	0	0
T13	0	5740	0	0
T14	0	2317	0	0
T15	0	2456	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34892297	34525911	0	0
T1	21683	18904	0	0
T2	72186	72126	0	0
T3	1166	1075	0	0
T4	77	5	0	0
T5	66452	66378	0	0
T6	104304	104242	0	0
T7	836	738	0	0
T8	1174	1124	0	0
T9	65886	65791	0	0
T10	32767	32703	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2159	0	0
T2	902344	2	0	0
T3	560138	0	0	0
T5	314860	2	0	0
T6	990892	3	0	0
T7	134082	0	0	0
T8	564018	0	0	0
T9	326142	2	0	0
T10	337123	1	0	0
T11	206988	2	0	0
T12	173010	1	0	0
T13	0	7	0	0
T14	0	3	0	0
T15	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	542129	541842	0	0
T2	902344	902335	0	0
T3	560138	560062	0	0
T4	38573	38510	0	0
T5	314860	314859	0	0
T6	990892	990887	0	0
T7	134082	134029	0	0
T8	564018	563936	0	0
T9	326142	326141	0	0
T10	337123	337115	0	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T2,T5,T6

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T2,T5,T6
1	1	Covered	T2,T5,T6

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T2,T5,T6

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T5,T6
1	1	Covered	T2,T5,T6

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T2,T5,T6
0	0	1	Covered	T2,T5,T6
0	0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T2,T5,T6
0	0	1	Covered	T2,T5,T6
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	1872006	0	0
DstReqKnown_A	34892297	34525911	0	0
SrcAckBusyChk_A	2147483647	2164	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1872006	0	0
T2	902344	942	0	0
T3	560138	0	0	0
T5	314860	3038	0	0
T6	990892	957	0	0
T7	134082	0	0	0
T8	564018	0	0	0
T9	326142	3255	0	0
T10	337123	398	0	0
T11	206988	1782	0	0
T12	173010	1345	0	0
T13	0	5693	0	0
T14	0	2311	0	0
T15	0	2439	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34892297	34525911	0	0
T1	21683	18904	0	0
T2	72186	72126	0	0
T3	1166	1075	0	0
T4	77	5	0	0
T5	66452	66378	0	0
T6	104304	104242	0	0
T7	836	738	0	0
T8	1174	1124	0	0
T9	65886	65791	0	0
T10	32767	32703	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2164	0	0
T2	902344	2	0	0
T3	560138	0	0	0
T5	314860	2	0	0
T6	990892	3	0	0
T7	134082	0	0	0
T8	564018	0	0	0
T9	326142	2	0	0
T10	337123	1	0	0
T11	206988	2	0	0
T12	173010	1	0	0
T13	0	7	0	0
T14	0	3	0	0
T15	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	542129	541842	0	0
T2	902344	902335	0	0
T3	560138	560062	0	0
T4	38573	38510	0	0
T5	314860	314859	0	0
T6	990892	990887	0	0
T7	134082	134029	0	0
T8	564018	563936	0	0
T9	326142	326141	0	0
T10	337123	337115	0	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T2,T5,T6

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T2,T5,T6
1	1	Covered	T2,T5,T6

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T2,T5,T6

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T5,T6
1	1	Covered	T2,T5,T6

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T2,T5,T6
0	0	1	Covered	T2,T5,T6
0	0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T2,T5,T6
0	0	1	Covered	T2,T5,T6
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	1909916	0	0
DstReqKnown_A	34892297	34525911	0	0
SrcAckBusyChk_A	2147483647	2171	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1909916	0	0
T2	902344	938	0	0
T3	560138	0	0	0
T5	314860	3022	0	0
T6	990892	951	0	0
T7	134082	0	0	0
T8	564018	0	0	0
T9	326142	3233	0	0
T10	337123	384	0	0
T11	206988	1778	0	0
T12	173010	1335	0	0
T13	0	5654	0	0
T14	0	2305	0	0
T15	0	2429	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34892297	34525911	0	0
T1	21683	18904	0	0
T2	72186	72126	0	0
T3	1166	1075	0	0
T4	77	5	0	0
T5	66452	66378	0	0
T6	104304	104242	0	0
T7	836	738	0	0
T8	1174	1124	0	0
T9	65886	65791	0	0
T10	32767	32703	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2171	0	0
T2	902344	2	0	0
T3	560138	0	0	0
T5	314860	2	0	0
T6	990892	3	0	0
T7	134082	0	0	0
T8	564018	0	0	0
T9	326142	2	0	0
T10	337123	1	0	0
T11	206988	2	0	0
T12	173010	1	0	0
T13	0	7	0	0
T14	0	3	0	0
T15	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	542129	541842	0	0
T2	902344	902335	0	0
T3	560138	560062	0	0
T4	38573	38510	0	0
T5	314860	314859	0	0
T6	990892	990887	0	0
T7	134082	134029	0	0
T8	564018	563936	0	0
T9	326142	326141	0	0
T10	337123	337115	0	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_wakeup_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_adc_wakeup_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T2,T5,T6

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T2,T5,T6
1	1	Covered	T2,T5,T6

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T2,T5,T6

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T5,T6
1	1	Covered	T2,T5,T6

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_adc_wakeup_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T2,T5,T6
0	0	1	Covered	T2,T5,T6
0	0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T2,T5,T6
0	0	1	Covered	T2,T5,T6
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_adc_wakeup_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	1362038	0	0
DstReqKnown_A	34892297	34525911	0	0
SrcAckBusyChk_A	2147483647	1608	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1362038	0	0
T2	902344	922	0	0
T3	560138	0	0	0
T5	314860	2935	0	0
T6	990892	927	0	0
T7	134082	0	0	0
T8	564018	0	0	0
T9	326142	3168	0	0
T10	337123	346	0	0
T11	206988	1762	0	0
T12	173010	1293	0	0
T13	0	3755	0	0
T14	0	2281	0	0
T15	0	2382	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34892297	34525911	0	0
T1	21683	18904	0	0
T2	72186	72126	0	0
T3	1166	1075	0	0
T4	77	5	0	0
T5	66452	66378	0	0
T6	104304	104242	0	0
T7	836	738	0	0
T8	1174	1124	0	0
T9	65886	65791	0	0
T10	32767	32703	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1608	0	0
T2	902344	2	0	0
T3	560138	0	0	0
T5	314860	2	0	0
T6	990892	3	0	0
T7	134082	0	0	0
T8	564018	0	0	0
T9	326142	2	0	0
T10	337123	1	0	0
T11	206988	2	0	0
T12	173010	1	0	0
T13	0	5	0	0
T14	0	3	0	0
T15	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	542129	541842	0	0
T2	902344	902335	0	0
T3	560138	560062	0	0
T4	38573	38510	0	0
T5	314860	314859	0	0
T6	990892	990887	0	0
T7	134082	134029	0	0
T8	564018	563936	0	0
T9	326142	326141	0	0
T10	337123	337115	0	0

Line Coverage for Instance : tb.dut.u_reg.u_adc_fsm_rst_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_adc_fsm_rst_cdc

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T1,T2,T5

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T5

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T5
1	-	Covered	T1,T2,T5

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T1,T2,T5

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T5

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_adc_fsm_rst_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T1,T2,T5
0	0	1	Covered	T1,T2,T5
0	0	0	Covered	T1,T4,T2

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T4,T2
0	1	-	Covered	T1,T2,T5
0	0	1	Covered	T1,T2,T5
0	0	0	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.u_reg.u_adc_fsm_rst_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	19331960	0	0
DstReqKnown_A	34892297	34525911	0	0
SrcAckBusyChk_A	2147483647	21306	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	19331960	0	0
T1	542129	195284	0	0
T2	902344	1878	0	0
T3	560138	0	0	0
T4	38573	0	0	0
T5	314860	6699	0	0
T6	990892	1998	0	0
T7	134082	0	0	0
T8	564018	0	0	0
T9	326142	6908	0	0
T10	337123	937	0	0
T11	0	3684	0	0
T12	0	3492	0	0
T13	0	13441	0	0
T36	0	452513	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34892297	34525911	0	0
T1	21683	18904	0	0
T2	72186	72126	0	0
T3	1166	1075	0	0
T4	77	5	0	0
T5	66452	66378	0	0
T6	104304	104242	0	0
T7	836	738	0	0
T8	1174	1124	0	0
T9	65886	65791	0	0
T10	32767	32703	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	21306	0	0
T1	542129	220	0	0
T2	902344	4	0	0
T3	560138	0	0	0
T4	38573	0	0	0
T5	314860	4	0	0
T6	990892	6	0	0
T7	134082	0	0	0
T8	564018	0	0	0
T9	326142	4	0	0
T10	337123	2	0	0
T11	0	4	0	0
T12	0	2	0	0
T13	0	15	0	0
T36	0	268	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	542129	541842	0	0
T2	902344	902335	0	0
T3	560138	560062	0	0
T4	38573	38510	0	0
T5	314860	314859	0	0
T6	990892	990887	0	0
T7	134082	134029	0	0
T8	564018	563936	0	0
T9	326142	326141	0	0
T10	337123	337115	0	0