Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	96.00						96.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	24	96.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	24	96.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	0	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	1775	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	1707	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	1722	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	1782	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	1715	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	1721	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	1806	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	1803	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	1719	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	1883	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	1681	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	1845	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	1820	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	1760	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	1826	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	1720	0	0
adc_en_ctl_rd_A	2147483647	1314	0	0
adc_fsm_rst_rd_A	2147483647	1093	0	0
adc_intr_ctl_rd_A	2147483647	1610	0	0
adc_lp_sample_ctl_rd_A	2147483647	1110	0	0
adc_pd_ctl_rd_A	2147483647	1499	0	0
adc_sample_ctl_rd_A	2147483647	1171	0	0
adc_wakeup_ctl_rd_A	2147483647	1239	0	0
intr_enable_rd_A	2147483647	1691	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1775	0	0
T16	491844	45	0	0
T17	0	10	0	0
T18	0	22	0	0
T19	0	17	0	0
T20	0	30	0	0
T21	0	25	0	0
T22	0	36	0	0
T23	0	45	0	0
T24	0	34	0	0
T25	0	22	0	0
T26	365459	0	0	0
T27	363467	0	0	0
T28	33885	0	0	0
T29	29470	0	0	0
T30	186288	0	0	0
T31	317432	0	0	0
T32	164303	0	0	0
T33	342250	0	0	0
T34	412270	0	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1707	0	0
T16	491844	37	0	0
T17	0	13	0	0
T18	0	35	0	0
T19	0	13	0	0
T20	0	39	0	0
T21	0	30	0	0
T22	0	48	0	0
T23	0	37	0	0
T24	0	27	0	0
T25	0	14	0	0
T26	365459	0	0	0
T27	363467	0	0	0
T28	33885	0	0	0
T29	29470	0	0	0
T30	186288	0	0	0
T31	317432	0	0	0
T32	164303	0	0	0
T33	342250	0	0	0
T34	412270	0	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1722	0	0
T16	491844	47	0	0
T17	0	14	0	0
T18	0	36	0	0
T19	0	29	0	0
T20	0	29	0	0
T21	0	30	0	0
T22	0	57	0	0
T23	0	40	0	0
T24	0	5	0	0
T25	0	15	0	0
T26	365459	0	0	0
T27	363467	0	0	0
T28	33885	0	0	0
T29	29470	0	0	0
T30	186288	0	0	0
T31	317432	0	0	0
T32	164303	0	0	0
T33	342250	0	0	0
T34	412270	0	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1782	0	0
T16	491844	31	0	0
T17	0	32	0	0
T18	0	28	0	0
T19	0	13	0	0
T20	0	38	0	0
T21	0	32	0	0
T22	0	45	0	0
T23	0	54	0	0
T24	0	28	0	0
T25	0	12	0	0
T26	365459	0	0	0
T27	363467	0	0	0
T28	33885	0	0	0
T29	29470	0	0	0
T30	186288	0	0	0
T31	317432	0	0	0
T32	164303	0	0	0
T33	342250	0	0	0
T34	412270	0	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1715	0	0
T16	491844	53	0	0
T17	0	21	0	0
T18	0	36	0	0
T19	0	26	0	0
T20	0	24	0	0
T21	0	53	0	0
T22	0	39	0	0
T23	0	28	0	0
T24	0	26	0	0
T25	0	30	0	0
T26	365459	0	0	0
T27	363467	0	0	0
T28	33885	0	0	0
T29	29470	0	0	0
T30	186288	0	0	0
T31	317432	0	0	0
T32	164303	0	0	0
T33	342250	0	0	0
T34	412270	0	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1721	0	0
T16	491844	29	0	0
T17	0	21	0	0
T18	0	39	0	0
T19	0	26	0	0
T20	0	27	0	0
T21	0	36	0	0
T22	0	37	0	0
T23	0	34	0	0
T24	0	15	0	0
T25	0	15	0	0
T26	365459	0	0	0
T27	363467	0	0	0
T28	33885	0	0	0
T29	29470	0	0	0
T30	186288	0	0	0
T31	317432	0	0	0
T32	164303	0	0	0
T33	342250	0	0	0
T34	412270	0	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1806	0	0
T16	491844	32	0	0
T17	0	19	0	0
T18	0	41	0	0
T19	0	40	0	0
T20	0	34	0	0
T21	0	38	0	0
T22	0	39	0	0
T23	0	36	0	0
T24	0	32	0	0
T25	0	15	0	0
T26	365459	0	0	0
T27	363467	0	0	0
T28	33885	0	0	0
T29	29470	0	0	0
T30	186288	0	0	0
T31	317432	0	0	0
T32	164303	0	0	0
T33	342250	0	0	0
T34	412270	0	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1803	0	0
T16	491844	30	0	0
T17	0	27	0	0
T18	0	39	0	0
T19	0	12	0	0
T20	0	36	0	0
T21	0	36	0	0
T22	0	49	0	0
T23	0	34	0	0
T24	0	35	0	0
T25	0	14	0	0
T26	365459	0	0	0
T27	363467	0	0	0
T28	33885	0	0	0
T29	29470	0	0	0
T30	186288	0	0	0
T31	317432	0	0	0
T32	164303	0	0	0
T33	342250	0	0	0
T34	412270	0	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1719	0	0
T16	491844	28	0	0
T17	0	8	0	0
T18	0	32	0	0
T19	0	12	0	0
T20	0	25	0	0
T21	0	25	0	0
T22	0	40	0	0
T23	0	26	0	0
T24	0	26	0	0
T25	0	22	0	0
T26	365459	0	0	0
T27	363467	0	0	0
T28	33885	0	0	0
T29	29470	0	0	0
T30	186288	0	0	0
T31	317432	0	0	0
T32	164303	0	0	0
T33	342250	0	0	0
T34	412270	0	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1883	0	0
T16	491844	44	0	0
T17	0	19	0	0
T18	0	52	0	0
T19	0	33	0	0
T20	0	41	0	0
T21	0	34	0	0
T22	0	33	0	0
T23	0	48	0	0
T24	0	28	0	0
T25	0	13	0	0
T26	365459	0	0	0
T27	363467	0	0	0
T28	33885	0	0	0
T29	29470	0	0	0
T30	186288	0	0	0
T31	317432	0	0	0
T32	164303	0	0	0
T33	342250	0	0	0
T34	412270	0	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1681	0	0
T16	491844	48	0	0
T17	0	11	0	0
T18	0	33	0	0
T19	0	11	0	0
T20	0	32	0	0
T21	0	19	0	0
T22	0	24	0	0
T23	0	25	0	0
T24	0	23	0	0
T25	0	15	0	0
T26	365459	0	0	0
T27	363467	0	0	0
T28	33885	0	0	0
T29	29470	0	0	0
T30	186288	0	0	0
T31	317432	0	0	0
T32	164303	0	0	0
T33	342250	0	0	0
T34	412270	0	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1845	0	0
T16	491844	25	0	0
T17	0	14	0	0
T18	0	26	0	0
T19	0	30	0	0
T20	0	54	0	0
T21	0	40	0	0
T22	0	43	0	0
T23	0	44	0	0
T24	0	39	0	0
T25	0	18	0	0
T26	365459	0	0	0
T27	363467	0	0	0
T28	33885	0	0	0
T29	29470	0	0	0
T30	186288	0	0	0
T31	317432	0	0	0
T32	164303	0	0	0
T33	342250	0	0	0
T34	412270	0	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1820	0	0
T16	491844	32	0	0
T17	0	31	0	0
T18	0	32	0	0
T19	0	20	0	0
T20	0	33	0	0
T21	0	25	0	0
T22	0	37	0	0
T23	0	36	0	0
T24	0	33	0	0
T25	0	29	0	0
T26	365459	0	0	0
T27	363467	0	0	0
T28	33885	0	0	0
T29	29470	0	0	0
T30	186288	0	0	0
T31	317432	0	0	0
T32	164303	0	0	0
T33	342250	0	0	0
T34	412270	0	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1760	0	0
T16	491844	24	0	0
T17	0	32	0	0
T18	0	34	0	0
T19	0	22	0	0
T20	0	33	0	0
T21	0	33	0	0
T22	0	35	0	0
T23	0	41	0	0
T24	0	15	0	0
T25	0	9	0	0
T26	365459	0	0	0
T27	363467	0	0	0
T28	33885	0	0	0
T29	29470	0	0	0
T30	186288	0	0	0
T31	317432	0	0	0
T32	164303	0	0	0
T33	342250	0	0	0
T34	412270	0	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1826	0	0
T16	491844	31	0	0
T17	0	12	0	0
T18	0	48	0	0
T19	0	23	0	0
T20	0	42	0	0
T21	0	37	0	0
T22	0	35	0	0
T23	0	35	0	0
T24	0	28	0	0
T25	0	22	0	0
T26	365459	0	0	0
T27	363467	0	0	0
T28	33885	0	0	0
T29	29470	0	0	0
T30	186288	0	0	0
T31	317432	0	0	0
T32	164303	0	0	0
T33	342250	0	0	0
T34	412270	0	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1720	0	0
T16	491844	37	0	0
T17	0	4	0	0
T18	0	48	0	0
T19	0	19	0	0
T20	0	37	0	0
T21	0	38	0	0
T22	0	21	0	0
T23	0	31	0	0
T24	0	37	0	0
T25	0	28	0	0
T26	365459	0	0	0
T27	363467	0	0	0
T28	33885	0	0	0
T29	29470	0	0	0
T30	186288	0	0	0
T31	317432	0	0	0
T32	164303	0	0	0
T33	342250	0	0	0
T34	412270	0	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1314	0	0
T16	491844	43	0	0
T17	0	24	0	0
T18	0	27	0	0
T19	0	20	0	0
T20	0	42	0	0
T21	0	49	0	0
T22	0	32	0	0
T23	0	46	0	0
T24	0	36	0	0
T25	0	20	0	0
T26	365459	0	0	0
T27	363467	0	0	0
T28	33885	0	0	0
T29	29470	0	0	0
T30	186288	0	0	0
T31	317432	0	0	0
T32	164303	0	0	0
T33	342250	0	0	0
T34	412270	0	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1093	0	0
T16	491844	30	0	0
T17	0	15	0	0
T18	0	24	0	0
T19	0	26	0	0
T20	0	34	0	0
T21	0	14	0	0
T22	0	22	0	0
T23	0	37	0	0
T24	0	18	0	0
T25	0	32	0	0
T26	365459	0	0	0
T27	363467	0	0	0
T28	33885	0	0	0
T29	29470	0	0	0
T30	186288	0	0	0
T31	317432	0	0	0
T32	164303	0	0	0
T33	342250	0	0	0
T34	412270	0	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1610	0	0
T16	491844	23	0	0
T17	0	17	0	0
T18	0	49	0	0
T19	0	25	0	0
T20	0	16	0	0
T21	0	39	0	0
T22	0	43	0	0
T23	0	32	0	0
T24	0	27	0	0
T25	0	9	0	0
T26	365459	0	0	0
T27	363467	0	0	0
T28	33885	0	0	0
T29	29470	0	0	0
T30	186288	0	0	0
T31	317432	0	0	0
T32	164303	0	0	0
T33	342250	0	0	0
T34	412270	0	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1110	0	0
T16	491844	29	0	0
T17	0	12	0	0
T18	0	27	0	0
T19	0	42	0	0
T20	0	28	0	0
T21	0	46	0	0
T22	0	45	0	0
T23	0	37	0	0
T24	0	20	0	0
T25	0	15	0	0
T26	365459	0	0	0
T27	363467	0	0	0
T28	33885	0	0	0
T29	29470	0	0	0
T30	186288	0	0	0
T31	317432	0	0	0
T32	164303	0	0	0
T33	342250	0	0	0
T34	412270	0	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1499	0	0
T16	491844	46	0	0
T17	0	22	0	0
T18	0	56	0	0
T19	0	25	0	0
T20	0	41	0	0
T21	0	21	0	0
T22	0	47	0	0
T23	0	31	0	0
T24	0	23	0	0
T25	0	6	0	0
T26	365459	0	0	0
T27	363467	0	0	0
T28	33885	0	0	0
T29	29470	0	0	0
T30	186288	0	0	0
T31	317432	0	0	0
T32	164303	0	0	0
T33	342250	0	0	0
T34	412270	0	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1171	0	0
T16	491844	33	0	0
T17	0	17	0	0
T18	0	33	0	0
T19	0	34	0	0
T20	0	44	0	0
T21	0	19	0	0
T22	0	53	0	0
T23	0	48	0	0
T24	0	34	0	0
T25	0	23	0	0
T26	365459	0	0	0
T27	363467	0	0	0
T28	33885	0	0	0
T29	29470	0	0	0
T30	186288	0	0	0
T31	317432	0	0	0
T32	164303	0	0	0
T33	342250	0	0	0
T34	412270	0	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1239	0	0
T16	491844	24	0	0
T17	0	20	0	0
T18	0	24	0	0
T19	0	36	0	0
T20	0	37	0	0
T21	0	30	0	0
T22	0	26	0	0
T23	0	35	0	0
T24	0	33	0	0
T25	0	11	0	0
T26	365459	0	0	0
T27	363467	0	0	0
T28	33885	0	0	0
T29	29470	0	0	0
T30	186288	0	0	0
T31	317432	0	0	0
T32	164303	0	0	0
T33	342250	0	0	0
T34	412270	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1691	0	0
T16	491844	34	0	0
T17	0	15	0	0
T18	0	74	0	0
T19	0	26	0	0
T20	0	23	0	0
T21	0	65	0	0
T22	0	74	0	0
T23	0	86	0	0
T24	0	24	0	0
T26	365459	0	0	0
T27	363467	0	0	0
T28	33885	0	0	0
T29	29470	0	0	0
T30	186288	0	0	0
T31	317432	0	0	0
T32	164303	0	0	0
T33	342250	0	0	0
T34	412270	0	0	0
T35	0	12	0	0