Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1231001	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1203951

1

T1

1445

T2

2223

T3

26

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2137580	1			T1	2544		T2	4134		T4	1651
values[0x0]	148331	1			T1	164		T2	121		T3	24
values[0x1]	149041	1			T1	149		T2	114		T3	19

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	986034	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1448918

1

T1

1735

T2

2662

T3

28

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7372	1			T1	3		T4	10		T5	25
valid_sources[0x01]	11378	1			T1	5		T4	3		T5	17
valid_sources[0x02]	6841	1			T1	23		T4	5		T5	14
valid_sources[0x03]	7376	1			T1	3		T4	11		T5	4
valid_sources[0x04]	12572	1			T1	4		T4	9		T5	21
valid_sources[0x05]	12155	1			T1	16		T4	8		T5	6
valid_sources[0x06]	11858	1			T1	33		T4	8		T5	13
valid_sources[0x07]	8477	1			T1	12		T4	5		T5	17
valid_sources[0x08]	11134	1			T1	4		T4	8		T5	5
valid_sources[0x09]	8934	1			T1	6		T4	11		T5	18
valid_sources[0x0a]	7175	1			T1	29		T4	15		T5	7
valid_sources[0x0b]	9563	1			T1	11		T4	8		T5	31
valid_sources[0x0c]	7119	1			T1	13		T4	7		T5	42
valid_sources[0x0d]	9599	1			T1	22		T4	6		T5	10
valid_sources[0x0e]	8463	1			T1	8		T4	10		T5	46
valid_sources[0x0f]	7117	1			T1	8		T4	4		T5	26
valid_sources[0x10]	7341	1			T1	13		T4	3		T5	26
valid_sources[0x11]	7194	1			T1	10		T4	14		T5	9
valid_sources[0x12]	6512	1			T1	1		T4	2		T5	2
valid_sources[0x13]	10201	1			T1	11		T4	10		T5	1
valid_sources[0x14]	7607	1			T1	5		T4	6		T5	28
valid_sources[0x15]	7211	1			T1	2		T4	16		T5	19
valid_sources[0x16]	12012	1			T1	5		T4	17		T5	13
valid_sources[0x17]	7332	1			T1	25		T4	6		T5	19
valid_sources[0x18]	6834	1			T1	14		T4	8		T5	28
valid_sources[0x19]	7416	1			T1	7		T4	13		T5	14
valid_sources[0x1a]	13704	1			T1	21		T4	13		T5	21
valid_sources[0x1b]	6731	1			T1	16		T4	8		T5	10
valid_sources[0x1c]	7077	1			T1	4		T4	7		T5	23
valid_sources[0x1d]	16048	1			T1	8		T4	12		T5	3
valid_sources[0x1e]	11636	1			T1	10		T4	9		T5	18
valid_sources[0x1f]	7878	1			T1	23		T4	7		T5	29
valid_sources[0x20]	8381	1			T1	2		T4	5		T5	13
valid_sources[0x21]	7277	1			T1	10		T4	7		T5	9
valid_sources[0x22]	11584	1			T1	8		T4	4		T5	1
valid_sources[0x23]	14190	1			T4	6		T5	1		T6	13
valid_sources[0x24]	7083	1			T1	19		T4	9		T5	29
valid_sources[0x25]	11550	1			T1	9		T4	6		T5	12
valid_sources[0x26]	8218	1			T1	25		T4	1		T5	33
valid_sources[0x27]	15953	1			T1	1		T4	15		T5	14
valid_sources[0x28]	7676	1			T1	10		T4	3		T5	1
valid_sources[0x29]	7010	1			T1	22		T4	16		T5	9
valid_sources[0x2a]	7120	1			T1	2		T4	16		T5	31
valid_sources[0x2b]	10300	1			T1	5		T4	9		T5	22
valid_sources[0x2c]	7338	1			T1	12		T4	6		T5	16
valid_sources[0x2d]	7888	1			T1	9		T4	8		T5	7
valid_sources[0x2e]	11767	1			T1	2		T4	11		T5	12
valid_sources[0x2f]	12375	1			T1	17		T4	8		T5	8
valid_sources[0x30]	12402	1			T1	9		T4	9		T5	16
valid_sources[0x31]	7335	1			T1	36		T4	11		T5	52
valid_sources[0x32]	8472	1			T1	1		T4	2		T5	11
valid_sources[0x33]	9146	1			T4	15		T5	4		T7	94
valid_sources[0x34]	7386	1			T1	3		T4	12		T5	34
valid_sources[0x35]	6987	1			T4	5		T5	3		T6	12
valid_sources[0x36]	10100	1			T1	5		T4	8		T5	38
valid_sources[0x37]	7703	1			T1	11		T4	9		T5	15
valid_sources[0x38]	7864	1			T1	9		T4	12		T5	21
valid_sources[0x39]	6959	1			T1	2		T4	8		T5	19
valid_sources[0x3a]	7110	1			T1	7		T4	3		T5	27
valid_sources[0x3b]	11602	1			T1	2		T4	9		T5	6
valid_sources[0x3c]	7903	1			T1	29		T4	7		T5	19
valid_sources[0x3d]	7440	1			T1	23		T4	14		T5	18
valid_sources[0x3e]	9973	1			T1	16		T4	10		T5	27
valid_sources[0x3f]	8460	1			T1	13		T4	1		T5	37
valid_sources[0x40]	7251	1			T1	18		T4	3		T5	16
valid_sources[0x41]	11560	1			T1	1		T4	12		T5	18
valid_sources[0x42]	8009	1			T1	25		T4	7		T5	18
valid_sources[0x43]	9762	1			T1	3		T4	7		T5	31
valid_sources[0x44]	9900	1			T1	12		T4	2		T5	10
valid_sources[0x45]	7339	1			T1	7		T4	12		T5	18
valid_sources[0x46]	7019	1			T1	10		T4	10		T5	30
valid_sources[0x47]	9724	1			T1	4		T4	11		T5	12
valid_sources[0x48]	7449	1			T1	7		T4	2		T5	17
valid_sources[0x49]	6927	1			T1	18		T4	10		T5	7
valid_sources[0x4a]	11747	1			T1	10		T4	7		T5	12
valid_sources[0x4b]	12285	1			T1	9		T4	9		T5	8
valid_sources[0x4c]	7673	1			T1	10		T4	6		T5	20
valid_sources[0x4d]	10089	1			T1	5		T4	14		T5	22
valid_sources[0x4e]	7466	1			T4	13		T5	8		T6	6
valid_sources[0x4f]	8803	1			T1	6		T4	12		T5	15
valid_sources[0x50]	23447	1			T1	8		T4	6		T5	30
valid_sources[0x51]	7279	1			T1	34		T4	6		T5	9
valid_sources[0x52]	9339	1			T1	32		T4	12		T5	16
valid_sources[0x53]	8269	1			T1	14		T4	4		T5	12
valid_sources[0x54]	11200	1			T1	13		T4	8		T5	17
valid_sources[0x55]	10140	1			T1	8		T4	7		T5	1
valid_sources[0x56]	7693	1			T1	20		T5	2		T7	41
valid_sources[0x57]	7754	1			T1	34		T4	1		T5	7
valid_sources[0x58]	10298	1			T1	5		T4	8		T5	28
valid_sources[0x59]	8934	1			T1	8		T4	6		T5	9
valid_sources[0x5a]	15274	1			T1	7		T4	3		T5	15
valid_sources[0x5b]	9108	1			T1	10		T4	17		T5	8
valid_sources[0x5c]	7230	1			T1	4		T4	5		T5	29
valid_sources[0x5d]	7781	1			T1	20		T4	7		T5	23
valid_sources[0x5e]	10261	1			T1	17		T4	7		T5	15
valid_sources[0x5f]	7245	1			T1	25		T5	5		T6	13
valid_sources[0x60]	10315	1			T1	17		T4	8		T5	7
valid_sources[0x61]	8524	1			T1	11		T4	8		T5	20
valid_sources[0x62]	6966	1			T1	13		T4	3		T5	6
valid_sources[0x63]	8260	1			T1	36		T4	16		T5	14
valid_sources[0x64]	8736	1			T1	10		T4	5		T5	15
valid_sources[0x65]	11519	1			T1	5		T4	6		T5	36
valid_sources[0x66]	7587	1			T1	5		T4	11		T5	11
valid_sources[0x67]	12586	1			T1	4		T4	2		T5	45
valid_sources[0x68]	7016	1			T1	15		T4	2		T5	30
valid_sources[0x69]	7545	1			T1	32		T4	10		T5	3
valid_sources[0x6a]	8179	1			T1	7		T4	9		T5	32
valid_sources[0x6b]	19545	1			T1	1		T4	9		T5	16
valid_sources[0x6c]	8160	1			T1	8		T4	4		T5	18
valid_sources[0x6d]	8303	1			T1	7		T3	43		T4	3
valid_sources[0x6e]	8466	1			T1	14		T4	4		T5	9
valid_sources[0x6f]	8978	1			T1	8		T5	14		T6	5
valid_sources[0x70]	14433	1			T1	6		T4	3		T5	1
valid_sources[0x71]	7310	1			T1	15		T4	3		T5	19
valid_sources[0x72]	8819	1			T1	6		T4	8		T5	8
valid_sources[0x73]	12045	1			T1	23		T4	8		T5	11
valid_sources[0x74]	6926	1			T1	4		T4	2		T5	26
valid_sources[0x75]	20435	1			T1	5		T4	9		T5	18
valid_sources[0x76]	7051	1			T1	13		T4	9		T5	34
valid_sources[0x77]	6607	1			T1	8		T4	10		T5	24
valid_sources[0x78]	7547	1			T1	17		T4	5		T5	2
valid_sources[0x79]	8303	1			T1	5		T4	6		T5	9
valid_sources[0x7a]	10641	1			T1	2		T4	5		T5	35
valid_sources[0x7b]	11607	1			T1	7		T4	5		T5	25
valid_sources[0x7c]	7817	1			T1	6		T4	12		T5	17
valid_sources[0x7d]	7110	1			T1	23		T4	8		T5	15
valid_sources[0x7e]	11018	1			T1	11		T4	1		T5	39
valid_sources[0x7f]	8134	1			T1	3		T4	2		T5	37
valid_sources[0x80]	7319	1			T1	11		T4	9		T5	11

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1065680

1

T1

1283

T2

2123

T4

805

values[0x0]

all_enables

biggest_size

80488

1

T1

100

T2

65

T3

11

values[0x1]

all_enables

biggest_size

57783

1

T1

62

T2

35

T3

15