Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
86.67	86.67	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	86.67	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
86.67	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	6	39	86.67

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	5	11	68.75	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	28061	1			T1	24		T2	8		T4	10
auto[PWRUP]	119	1			T31	3		T39	2		T59	5
auto[ONEST_0]	72	1			T45	2		T59	2		T60	2
auto[ONEST_021]	12	1			T71	1		T72	1		T218	1
auto[ONEST_1]	78	1			T39	2		T41	1		T45	1
auto[ONEST_DONE]	6	1			T59	1		T219	1		T220	1
auto[LP_0]	127	1			T31	3		T39	2		T41	1
auto[LP_021]	28	1			T39	1		T41	3		T64	1
auto[LP_1]	130	1			T31	1		T39	2		T45	3
auto[LP_EVAL]	57	1			T31	1		T41	1		T45	1
auto[LP_SLP]	497	1			T31	5		T39	8		T41	3
auto[LP_PWRUP]	24	1			T45	1		T64	1		T197	2
auto[NP_0]	150	1			T31	1		T39	3		T45	2
auto[NP_021]	30	1			T39	1		T60	1		T64	1
auto[NP_1]	159	1			T31	1		T39	2		T41	1
auto[NP_EVAL]	40	1			T41	1		T64	1		T221	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

13

1

T45

1

T59

1

T197

1

min

27542

1

T1

24

T2

8

T4

10

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	27554	1			T1	24		T2	8		T4	10
pow[0x1]	5	1			T222	1		T223	1		T224	1
pow[0x2]	15	1			T64	1		T33	1		T69	1
pow[0x3]	38	1			T64	1		T33	1		T221	1
pow[0x4]	66	1			T31	1		T39	2		T41	1
pow[0x5]	124	1			T39	6		T45	3		T59	1
pow[0x6]	261	1			T31	3		T39	7		T41	4
pow[0x7]	499	1			T31	5		T39	13		T41	6

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

214

1

T31

3

T39

6

T41

2

min

27083

1

T1

24

T2

8

T4

10

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	5	11	68.75

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x2]	0	1	1
pow[0x3]	0	1	1
pow[0x5]	0	1	1
pow[0x6]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	27083	1			T1	24		T2	8		T4	10
pow[0x4]	1	1			T225	1		-	-		-	-
pow[0x7]	2	1			T219	1		T226	1		-	-
pow[0x8]	2	1			T45	1		T64	1		-	-
pow[0x9]	17	1			T39	1		T45	1		T60	1
pow[0xa]	20	1			T64	1		T197	1		T227	1
pow[0xb]	38	1			T39	1		T59	1		T64	2
pow[0xc]	60	1			T31	1		T39	1		T45	2
pow[0xd]	140	1			T39	5		T41	3		T45	2
pow[0xe]	277	1			T31	5		T39	2		T41	3
pow[0xf]	610	1			T31	6		T39	8		T41	7