Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
97.78	97.78	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	97.78	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.78	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	1	44	97.78

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	0	16	100.00	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2335	1			T5	3		T31	13		T39	17
auto[PWRUP]	139	1			T31	2		T39	1		T41	1
auto[ONEST_0]	71	1			T31	1		T39	2		T45	1
auto[ONEST_021]	16	1			T45	1		T72	1		T218	1
auto[ONEST_1]	89	1			T31	1		T41	2		T45	2
auto[ONEST_DONE]	6	1			T64	1		T69	1		T217	1
auto[LP_0]	136	1			T31	2		T39	4		T59	4
auto[LP_021]	35	1			T31	1		T60	1		T221	1
auto[LP_1]	151	1			T31	1		T39	1		T41	1
auto[LP_EVAL]	52	1			T39	2		T59	1		T64	1
auto[LP_SLP]	571	1			T31	5		T39	4		T41	4
auto[LP_PWRUP]	21	1			T60	2		T221	1		T48	1
auto[NP_0]	213	1			T31	3		T39	4		T41	2
auto[NP_021]	44	1			T45	1		T33	1		T221	1
auto[NP_1]	215	1			T31	3		T39	1		T41	1
auto[NP_EVAL]	36	1			T39	1		T45	1		T59	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

11

1

T69

1

T227

1

T70

1

min

2009

1

T5

3

T31

9

T39

7

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	2021	1			T5	3		T31	9		T39	7
pow[0x1]	18	1			T45	2		T33	1		T221	1
pow[0x2]	29	1			T59	1		T71	1		T50	2
pow[0x3]	39	1			T31	1		T41	2		T45	1
pow[0x4]	60	1			T41	1		T45	1		T64	1
pow[0x5]	115	1			T39	1		T41	1		T45	2
pow[0x6]	248	1			T31	3		T39	1		T41	3
pow[0x7]	552	1			T31	6		T39	11		T41	7

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

196

1

T31

1

T39

3

T41

2

min

1389

1

T5

3

T31

7

T39

3

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	0	16	100.00

User Defined Bins for np_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1394	1			T5	3		T31	7		T39	3
pow[0x1]	16	1			T46	5		T47	2		T51	1
pow[0x2]	13	1			T48	1		T52	1		T135	1
pow[0x3]	33	1			T54	2		T298	2		T135	4
pow[0x4]	61	1			T47	2		T48	3		T49	2
pow[0x5]	1	1			T50	1		-	-		-	-
pow[0x6]	3	1			T15	1		T323	1		T361	1
pow[0x7]	1	1			T197	1		-	-		-	-
pow[0x8]	6	1			T362	1		T192	1		T363	1
pow[0x9]	9	1			T127	1		T54	1		T70	1
pow[0xa]	22	1			T221	1		T362	1		T49	1
pow[0xb]	38	1			T39	1		T41	1		T45	1
pow[0xc]	76	1			T31	1		T41	1		T45	2
pow[0xd]	138	1			T31	1		T39	2		T41	1
pow[0xe]	303	1			T31	4		T39	2		T41	4
pow[0xf]	647	1			T31	4		T39	6		T41	5