Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	96.00						96.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	24	96.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	24	96.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	0	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	1654	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	1684	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	1603	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	1559	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	1470	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	1769	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	1648	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	1513	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	1639	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	1591	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	1643	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	1617	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	1563	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	1657	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	1496	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	1709	0	0
adc_en_ctl_rd_A	2147483647	1226	0	0
adc_fsm_rst_rd_A	2147483647	1080	0	0
adc_intr_ctl_rd_A	2147483647	2234	0	0
adc_lp_sample_ctl_rd_A	2147483647	1164	0	0
adc_pd_ctl_rd_A	2147483647	1479	0	0
adc_sample_ctl_rd_A	2147483647	1035	0	0
adc_wakeup_ctl_rd_A	2147483647	1215	0	0
intr_enable_rd_A	2147483647	2092	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1654	0	0
T12	339608	41	0	0
T13	0	22	0	0
T14	0	15	0	0
T15	0	33	0	0
T16	0	37	0	0
T17	0	13	0	0
T18	0	5	0	0
T19	0	22	0	0
T20	0	23	0	0
T21	0	36	0	0
T22	119239	0	0	0
T23	32949	0	0	0
T24	195755	0	0	0
T25	11370	0	0	0
T26	140931	0	0	0
T27	162741	0	0	0
T28	491260	0	0	0
T29	580333	0	0	0
T30	11299	0	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1684	0	0
T12	339608	29	0	0
T13	0	21	0	0
T14	0	16	0	0
T15	0	55	0	0
T16	0	46	0	0
T17	0	12	0	0
T18	0	14	0	0
T19	0	20	0	0
T20	0	29	0	0
T21	0	41	0	0
T22	119239	0	0	0
T23	32949	0	0	0
T24	195755	0	0	0
T25	11370	0	0	0
T26	140931	0	0	0
T27	162741	0	0	0
T28	491260	0	0	0
T29	580333	0	0	0
T30	11299	0	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1603	0	0
T12	339608	34	0	0
T13	0	16	0	0
T14	0	13	0	0
T15	0	43	0	0
T16	0	31	0	0
T17	0	12	0	0
T18	0	14	0	0
T19	0	41	0	0
T20	0	23	0	0
T21	0	17	0	0
T22	119239	0	0	0
T23	32949	0	0	0
T24	195755	0	0	0
T25	11370	0	0	0
T26	140931	0	0	0
T27	162741	0	0	0
T28	491260	0	0	0
T29	580333	0	0	0
T30	11299	0	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1559	0	0
T12	339608	30	0	0
T13	0	24	0	0
T14	0	18	0	0
T15	0	52	0	0
T16	0	29	0	0
T17	0	9	0	0
T18	0	27	0	0
T19	0	15	0	0
T20	0	20	0	0
T21	0	35	0	0
T22	119239	0	0	0
T23	32949	0	0	0
T24	195755	0	0	0
T25	11370	0	0	0
T26	140931	0	0	0
T27	162741	0	0	0
T28	491260	0	0	0
T29	580333	0	0	0
T30	11299	0	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1470	0	0
T12	339608	31	0	0
T13	0	8	0	0
T14	0	16	0	0
T15	0	31	0	0
T16	0	40	0	0
T17	0	7	0	0
T18	0	12	0	0
T19	0	42	0	0
T20	0	16	0	0
T21	0	38	0	0
T22	119239	0	0	0
T23	32949	0	0	0
T24	195755	0	0	0
T25	11370	0	0	0
T26	140931	0	0	0
T27	162741	0	0	0
T28	491260	0	0	0
T29	580333	0	0	0
T30	11299	0	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1769	0	0
T12	339608	54	0	0
T13	0	14	0	0
T14	0	27	0	0
T15	0	44	0	0
T16	0	29	0	0
T17	0	12	0	0
T18	0	18	0	0
T19	0	28	0	0
T20	0	23	0	0
T21	0	30	0	0
T22	119239	0	0	0
T23	32949	0	0	0
T24	195755	0	0	0
T25	11370	0	0	0
T26	140931	0	0	0
T27	162741	0	0	0
T28	491260	0	0	0
T29	580333	0	0	0
T30	11299	0	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1648	0	0
T12	339608	42	0	0
T13	0	14	0	0
T14	0	21	0	0
T15	0	36	0	0
T16	0	39	0	0
T17	0	20	0	0
T18	0	21	0	0
T19	0	17	0	0
T20	0	29	0	0
T21	0	15	0	0
T22	119239	0	0	0
T23	32949	0	0	0
T24	195755	0	0	0
T25	11370	0	0	0
T26	140931	0	0	0
T27	162741	0	0	0
T28	491260	0	0	0
T29	580333	0	0	0
T30	11299	0	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1513	0	0
T12	339608	23	0	0
T13	0	26	0	0
T14	0	7	0	0
T15	0	48	0	0
T16	0	25	0	0
T17	0	15	0	0
T18	0	6	0	0
T19	0	20	0	0
T20	0	11	0	0
T21	0	37	0	0
T22	119239	0	0	0
T23	32949	0	0	0
T24	195755	0	0	0
T25	11370	0	0	0
T26	140931	0	0	0
T27	162741	0	0	0
T28	491260	0	0	0
T29	580333	0	0	0
T30	11299	0	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1639	0	0
T12	339608	39	0	0
T13	0	12	0	0
T14	0	21	0	0
T15	0	24	0	0
T16	0	36	0	0
T17	0	18	0	0
T18	0	6	0	0
T19	0	31	0	0
T20	0	18	0	0
T21	0	29	0	0
T22	119239	0	0	0
T23	32949	0	0	0
T24	195755	0	0	0
T25	11370	0	0	0
T26	140931	0	0	0
T27	162741	0	0	0
T28	491260	0	0	0
T29	580333	0	0	0
T30	11299	0	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1591	0	0
T12	339608	52	0	0
T13	0	14	0	0
T14	0	17	0	0
T15	0	47	0	0
T16	0	43	0	0
T17	0	12	0	0
T18	0	18	0	0
T19	0	31	0	0
T20	0	21	0	0
T21	0	15	0	0
T22	119239	0	0	0
T23	32949	0	0	0
T24	195755	0	0	0
T25	11370	0	0	0
T26	140931	0	0	0
T27	162741	0	0	0
T28	491260	0	0	0
T29	580333	0	0	0
T30	11299	0	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1643	0	0
T12	339608	44	0	0
T13	0	12	0	0
T14	0	24	0	0
T15	0	39	0	0
T16	0	43	0	0
T17	0	12	0	0
T18	0	7	0	0
T19	0	24	0	0
T20	0	14	0	0
T21	0	44	0	0
T22	119239	0	0	0
T23	32949	0	0	0
T24	195755	0	0	0
T25	11370	0	0	0
T26	140931	0	0	0
T27	162741	0	0	0
T28	491260	0	0	0
T29	580333	0	0	0
T30	11299	0	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1617	0	0
T12	339608	41	0	0
T13	0	19	0	0
T14	0	23	0	0
T15	0	42	0	0
T16	0	46	0	0
T17	0	4	0	0
T18	0	26	0	0
T19	0	19	0	0
T20	0	21	0	0
T21	0	43	0	0
T22	119239	0	0	0
T23	32949	0	0	0
T24	195755	0	0	0
T25	11370	0	0	0
T26	140931	0	0	0
T27	162741	0	0	0
T28	491260	0	0	0
T29	580333	0	0	0
T30	11299	0	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1563	0	0
T12	339608	49	0	0
T13	0	14	0	0
T14	0	28	0	0
T15	0	45	0	0
T16	0	30	0	0
T17	0	13	0	0
T18	0	15	0	0
T19	0	30	0	0
T20	0	18	0	0
T21	0	33	0	0
T22	119239	0	0	0
T23	32949	0	0	0
T24	195755	0	0	0
T25	11370	0	0	0
T26	140931	0	0	0
T27	162741	0	0	0
T28	491260	0	0	0
T29	580333	0	0	0
T30	11299	0	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1657	0	0
T12	339608	46	0	0
T13	0	14	0	0
T14	0	23	0	0
T15	0	47	0	0
T16	0	24	0	0
T17	0	9	0	0
T18	0	14	0	0
T19	0	22	0	0
T20	0	25	0	0
T21	0	31	0	0
T22	119239	0	0	0
T23	32949	0	0	0
T24	195755	0	0	0
T25	11370	0	0	0
T26	140931	0	0	0
T27	162741	0	0	0
T28	491260	0	0	0
T29	580333	0	0	0
T30	11299	0	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1496	0	0
T12	339608	31	0	0
T13	0	19	0	0
T14	0	12	0	0
T15	0	34	0	0
T16	0	36	0	0
T17	0	19	0	0
T18	0	14	0	0
T19	0	29	0	0
T20	0	17	0	0
T21	0	29	0	0
T22	119239	0	0	0
T23	32949	0	0	0
T24	195755	0	0	0
T25	11370	0	0	0
T26	140931	0	0	0
T27	162741	0	0	0
T28	491260	0	0	0
T29	580333	0	0	0
T30	11299	0	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1709	0	0
T12	339608	35	0	0
T13	0	27	0	0
T14	0	20	0	0
T15	0	22	0	0
T16	0	38	0	0
T17	0	12	0	0
T18	0	27	0	0
T19	0	17	0	0
T20	0	29	0	0
T21	0	30	0	0
T22	119239	0	0	0
T23	32949	0	0	0
T24	195755	0	0	0
T25	11370	0	0	0
T26	140931	0	0	0
T27	162741	0	0	0
T28	491260	0	0	0
T29	580333	0	0	0
T30	11299	0	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1226	0	0
T12	339608	37	0	0
T13	0	8	0	0
T14	0	17	0	0
T15	0	27	0	0
T16	0	9	0	0
T17	0	16	0	0
T18	0	15	0	0
T19	0	35	0	0
T20	0	26	0	0
T21	0	20	0	0
T22	119239	0	0	0
T23	32949	0	0	0
T24	195755	0	0	0
T25	11370	0	0	0
T26	140931	0	0	0
T27	162741	0	0	0
T28	491260	0	0	0
T29	580333	0	0	0
T30	11299	0	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1080	0	0
T12	339608	33	0	0
T13	0	15	0	0
T14	0	25	0	0
T15	0	35	0	0
T16	0	23	0	0
T17	0	11	0	0
T18	0	16	0	0
T19	0	18	0	0
T20	0	21	0	0
T21	0	26	0	0
T22	119239	0	0	0
T23	32949	0	0	0
T24	195755	0	0	0
T25	11370	0	0	0
T26	140931	0	0	0
T27	162741	0	0	0
T28	491260	0	0	0
T29	580333	0	0	0
T30	11299	0	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2234	0	0
T12	339608	37	0	0
T13	0	6	0	0
T14	0	18	0	0
T15	0	36	0	0
T16	0	30	0	0
T17	0	24	0	0
T18	0	8	0	0
T19	0	29	0	0
T20	0	18	0	0
T21	0	42	0	0
T22	119239	0	0	0
T23	32949	0	0	0
T24	195755	0	0	0
T25	11370	0	0	0
T26	140931	0	0	0
T27	162741	0	0	0
T28	491260	0	0	0
T29	580333	0	0	0
T30	11299	0	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1164	0	0
T12	339608	48	0	0
T13	0	20	0	0
T14	0	32	0	0
T15	0	40	0	0
T16	0	24	0	0
T17	0	11	0	0
T18	0	15	0	0
T19	0	24	0	0
T20	0	29	0	0
T21	0	27	0	0
T22	119239	0	0	0
T23	32949	0	0	0
T24	195755	0	0	0
T25	11370	0	0	0
T26	140931	0	0	0
T27	162741	0	0	0
T28	491260	0	0	0
T29	580333	0	0	0
T30	11299	0	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1479	0	0
T12	339608	40	0	0
T13	0	17	0	0
T14	0	14	0	0
T15	0	47	0	0
T16	0	35	0	0
T17	0	20	0	0
T18	0	12	0	0
T19	0	16	0	0
T20	0	25	0	0
T21	0	44	0	0
T22	119239	0	0	0
T23	32949	0	0	0
T24	195755	0	0	0
T25	11370	0	0	0
T26	140931	0	0	0
T27	162741	0	0	0
T28	491260	0	0	0
T29	580333	0	0	0
T30	11299	0	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1035	0	0
T12	339608	35	0	0
T13	0	25	0	0
T14	0	15	0	0
T15	0	51	0	0
T16	0	40	0	0
T17	0	9	0	0
T18	0	16	0	0
T19	0	29	0	0
T20	0	32	0	0
T21	0	21	0	0
T22	119239	0	0	0
T23	32949	0	0	0
T24	195755	0	0	0
T25	11370	0	0	0
T26	140931	0	0	0
T27	162741	0	0	0
T28	491260	0	0	0
T29	580333	0	0	0
T30	11299	0	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1215	0	0
T12	339608	31	0	0
T13	0	23	0	0
T14	0	9	0	0
T15	0	20	0	0
T16	0	54	0	0
T17	0	14	0	0
T18	0	8	0	0
T19	0	13	0	0
T20	0	30	0	0
T21	0	43	0	0
T22	119239	0	0	0
T23	32949	0	0	0
T24	195755	0	0	0
T25	11370	0	0	0
T26	140931	0	0	0
T27	162741	0	0	0
T28	491260	0	0	0
T29	580333	0	0	0
T30	11299	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2092	0	0
T12	0	64	0	0
T13	0	26	0	0
T14	0	10	0	0
T15	0	49	0	0
T31	102066	16	0	0
T32	0	18	0	0
T33	0	18	0	0
T34	0	42	0	0
T35	0	36	0	0
T36	0	15	0	0
T37	630583	0	0	0
T38	793307	0	0	0
T39	364153	0	0	0
T40	580107	0	0	0
T41	624962	0	0	0
T42	21282	0	0	0
T43	239843	0	0	0
T44	180090	0	0	0
T45	179131	0	0	0