Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1181604	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1153380

1

T1

1368

T2

444

T3

380

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2038925	1			T1	2489		T2	846		T14	1
values[0x0]	147301	1			T1	151		T2	55		T3	497
values[0x1]	148758	1			T1	168		T2	53		T3	451

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	947032	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1387952

1

T1

1662

T2

544

T3

455

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	8013	1			T1	20		T2	4		T3	2
valid_sources[0x01]	9907	1			T1	11		T3	4		T4	7
valid_sources[0x02]	6778	1			T1	5		T3	3		T4	6
valid_sources[0x03]	11202	1			T1	14		T2	11		T3	2
valid_sources[0x04]	8712	1			T1	15		T2	3		T3	1
valid_sources[0x05]	9287	1			T1	7		T3	6		T4	7
valid_sources[0x06]	11050	1			T1	7		T3	3		T4	4
valid_sources[0x07]	14937	1			T1	11		T3	3		T4	7
valid_sources[0x08]	7005	1			T1	8		T2	5		T3	6
valid_sources[0x09]	10971	1			T1	9		T4	2		T5	1
valid_sources[0x0a]	9083	1			T1	21		T2	2		T3	8
valid_sources[0x0b]	6844	1			T1	12		T2	4		T3	2
valid_sources[0x0c]	9152	1			T1	12		T2	7		T3	5
valid_sources[0x0d]	9371	1			T1	12		T3	2		T4	2
valid_sources[0x0e]	9114	1			T1	11		T2	11		T3	6
valid_sources[0x0f]	10194	1			T1	2		T2	12		T3	2
valid_sources[0x10]	7035	1			T1	10		T3	6		T4	5
valid_sources[0x11]	8414	1			T1	10		T2	7		T3	4
valid_sources[0x12]	6669	1			T1	21		T2	10		T3	8
valid_sources[0x13]	11760	1			T1	12		T3	1		T4	1
valid_sources[0x14]	7121	1			T1	4		T2	4		T3	4
valid_sources[0x15]	7939	1			T1	4		T2	1		T3	9
valid_sources[0x16]	6682	1			T1	3		T3	4		T4	3
valid_sources[0x17]	11370	1			T1	11		T2	8		T3	1
valid_sources[0x18]	6895	1			T1	7		T3	1		T4	4
valid_sources[0x19]	6401	1			T1	12		T2	3		T3	2
valid_sources[0x1a]	13226	1			T1	6		T2	1		T3	1
valid_sources[0x1b]	11115	1			T1	15		T3	1		T5	4
valid_sources[0x1c]	7008	1			T1	11		T2	2		T4	3
valid_sources[0x1d]	7825	1			T1	10		T2	5		T3	6
valid_sources[0x1e]	6869	1			T1	8		T2	5		T3	6
valid_sources[0x1f]	11073	1			T1	16		T2	4		T3	6
valid_sources[0x20]	11568	1			T1	21		T2	6		T4	6
valid_sources[0x21]	10535	1			T1	14		T2	3		T3	3
valid_sources[0x22]	8888	1			T1	15		T2	7		T3	4
valid_sources[0x23]	6828	1			T1	8		T2	6		T3	4
valid_sources[0x24]	11730	1			T1	19		T2	3		T3	3
valid_sources[0x25]	11492	1			T1	9		T3	11		T5	4
valid_sources[0x26]	6971	1			T1	13		T2	1		T3	2
valid_sources[0x27]	16810	1			T1	6		T2	6		T3	4
valid_sources[0x28]	7829	1			T1	17		T2	10		T3	9
valid_sources[0x29]	6809	1			T1	6		T3	3		T4	2
valid_sources[0x2a]	11228	1			T1	14		T2	8		T3	3
valid_sources[0x2b]	6819	1			T1	9		T3	5		T4	5
valid_sources[0x2c]	6840	1			T1	12		T2	10		T3	6
valid_sources[0x2d]	6740	1			T1	14		T2	1		T3	9
valid_sources[0x2e]	6664	1			T1	8		T2	3		T3	5
valid_sources[0x2f]	7643	1			T1	24		T2	1		T3	5
valid_sources[0x30]	10914	1			T1	3		T3	3		T4	4
valid_sources[0x31]	10997	1			T1	22		T3	6		T5	3
valid_sources[0x32]	7372	1			T1	10		T2	1		T3	11
valid_sources[0x33]	11070	1			T1	10		T2	1		T3	7
valid_sources[0x34]	6869	1			T1	11		T2	2		T3	4
valid_sources[0x35]	6889	1			T1	5		T2	2		T3	2
valid_sources[0x36]	7927	1			T1	12		T2	9		T3	4
valid_sources[0x37]	11347	1			T1	8		T2	2		T3	3
valid_sources[0x38]	7562	1			T1	12		T2	3		T3	5
valid_sources[0x39]	6370	1			T1	11		T2	2		T3	2
valid_sources[0x3a]	6967	1			T1	24		T2	2		T3	6
valid_sources[0x3b]	7423	1			T1	9		T3	5		T4	1
valid_sources[0x3c]	7341	1			T1	5		T3	2		T4	1
valid_sources[0x3d]	6909	1			T1	9		T2	2		T3	6
valid_sources[0x3e]	7174	1			T1	6		T3	3		T5	2
valid_sources[0x3f]	8149	1			T1	10		T2	1		T3	3
valid_sources[0x40]	7047	1			T1	5		T3	4		T4	5
valid_sources[0x41]	8015	1			T1	7		T2	1		T3	3
valid_sources[0x42]	10033	1			T1	15		T2	3		T3	2
valid_sources[0x43]	12170	1			T1	7		T2	4		T3	2
valid_sources[0x44]	6798	1			T1	23		T2	1		T3	5
valid_sources[0x45]	11520	1			T1	9		T2	1		T3	4
valid_sources[0x46]	6706	1			T1	9		T2	9		T3	3
valid_sources[0x47]	6754	1			T1	13		T4	2		T5	3
valid_sources[0x48]	10808	1			T1	13		T3	1		T5	5
valid_sources[0x49]	11288	1			T1	11		T2	4		T3	1
valid_sources[0x4a]	17311	1			T1	8		T2	6		T3	6
valid_sources[0x4b]	6629	1			T1	14		T3	2		T5	2
valid_sources[0x4c]	9908	1			T1	12		T2	8		T3	4
valid_sources[0x4d]	8669	1			T1	6		T2	5		T3	3
valid_sources[0x4e]	6918	1			T1	12		T2	9		T3	8
valid_sources[0x4f]	6754	1			T1	12		T3	4		T4	1
valid_sources[0x50]	7704	1			T1	11		T3	3		T5	3
valid_sources[0x51]	7999	1			T1	12		T2	8		T4	1
valid_sources[0x52]	6975	1			T1	12		T3	5		T4	3
valid_sources[0x53]	6685	1			T1	11		T2	10		T4	3
valid_sources[0x54]	9537	1			T1	14		T3	2		T4	1
valid_sources[0x55]	11197	1			T1	17		T2	2		T3	3
valid_sources[0x56]	7842	1			T1	11		T4	4		T5	4
valid_sources[0x57]	7016	1			T1	11		T2	2		T3	6
valid_sources[0x58]	6784	1			T1	12		T3	3		T4	1
valid_sources[0x59]	7005	1			T1	22		T2	2		T3	3
valid_sources[0x5a]	6852	1			T1	9		T3	2		T4	2
valid_sources[0x5b]	6663	1			T1	10		T2	7		T3	5
valid_sources[0x5c]	6537	1			T1	12		T3	6		T4	6
valid_sources[0x5d]	6911	1			T1	11		T2	12		T3	4
valid_sources[0x5e]	6637	1			T1	19		T2	7		T3	2
valid_sources[0x5f]	10799	1			T1	5		T2	4		T3	3
valid_sources[0x60]	9406	1			T1	16		T3	1		T4	8
valid_sources[0x61]	7094	1			T1	6		T3	5		T4	2
valid_sources[0x62]	10861	1			T1	6		T2	10		T3	1
valid_sources[0x63]	6709	1			T1	10		T2	4		T3	2
valid_sources[0x64]	11063	1			T1	12		T3	10		T4	9
valid_sources[0x65]	6869	1			T1	9		T2	5		T3	4
valid_sources[0x66]	11421	1			T1	18		T3	1		T5	6
valid_sources[0x67]	11165	1			T1	11		T2	2		T3	3
valid_sources[0x68]	11107	1			T1	11		T3	3		T15	2
valid_sources[0x69]	8742	1			T1	15		T3	1		T4	2
valid_sources[0x6a]	11211	1			T1	17		T3	1		T15	1
valid_sources[0x6b]	7891	1			T1	18		T2	6		T3	3
valid_sources[0x6c]	14540	1			T1	10		T3	1		T4	3
valid_sources[0x6d]	6596	1			T1	10		T2	3		T3	2
valid_sources[0x6e]	6886	1			T1	12		T2	2		T3	1
valid_sources[0x6f]	11374	1			T1	9		T2	2		T3	5
valid_sources[0x70]	7045	1			T1	1		T2	6		T3	4
valid_sources[0x71]	11687	1			T1	5		T2	3		T3	2
valid_sources[0x72]	11797	1			T1	6		T2	3		T3	1
valid_sources[0x73]	19370	1			T1	10		T3	3		T4	8
valid_sources[0x74]	10784	1			T1	12		T2	2		T3	1
valid_sources[0x75]	6815	1			T1	8		T2	9		T3	2
valid_sources[0x76]	12048	1			T1	11		T2	13		T3	5
valid_sources[0x77]	11153	1			T1	5		T3	4		T4	4
valid_sources[0x78]	7090	1			T1	9		T2	6		T3	7
valid_sources[0x79]	7875	1			T1	13		T2	1		T3	6
valid_sources[0x7a]	10500	1			T1	12		T2	7		T3	8
valid_sources[0x7b]	11265	1			T1	3		T2	5		T3	3
valid_sources[0x7c]	7263	1			T1	13		T3	5		T4	6
valid_sources[0x7d]	7762	1			T1	17		T2	2		T3	5
valid_sources[0x7e]	7318	1			T1	11		T3	2		T4	5
valid_sources[0x7f]	11633	1			T1	22		T2	15		T3	3
valid_sources[0x80]	7273	1			T1	9		T2	5		T3	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1016084

1

T1

1215

T2

398

T15

1

values[0x0]

all_enables

biggest_size

79742

1

T1

83

T2

23

T3

233

values[0x1]

all_enables

biggest_size

57554

1

T1

70

T2

23

T3

147