Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
88.89	88.89	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	88.89	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.89	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	5	40	88.89

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	4	12	75.00	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	31097	1			T1	27		T2	9		T3	211
auto[PWRUP]	110	1			T3	1		T12	2		T41	1
auto[ONEST_0]	71	1			T10	1		T12	1		T41	1
auto[ONEST_021]	11	1			T53	1		T54	1		T227	1
auto[ONEST_1]	92	1			T3	1		T10	1		T12	1
auto[ONEST_DONE]	3	1			T228	1		T229	1		T230	1
auto[LP_0]	117	1			T3	2		T10	1		T12	1
auto[LP_021]	40	1			T41	1		T36	1		T178	1
auto[LP_1]	134	1			T12	3		T41	3		T42	2
auto[LP_EVAL]	81	1			T3	1		T10	1		T41	1
auto[LP_SLP]	520	1			T3	5		T10	3		T12	7
auto[LP_PWRUP]	21	1			T41	1		T214	1		T48	1
auto[NP_0]	165	1			T3	1		T10	2		T12	2
auto[NP_021]	42	1			T3	2		T10	1		T178	1
auto[NP_1]	163	1			T3	2		T10	1		T12	2
auto[NP_EVAL]	41	1			T3	3		T12	1		T41	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
max	2	1			T231	2		-	-		-	-
min	30450	1			T1	27		T2	9		T3	205

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	30457	1			T1	27		T2	9		T3	205
pow[0x1]	8	1			T232	1		T233	1		T234	2
pow[0x2]	15	1			T36	1		T86	1		T214	1
pow[0x3]	28	1			T12	1		T150	1		T16	1
pow[0x4]	67	1			T3	3		T10	1		T12	1
pow[0x5]	130	1			T3	1		T10	1		T12	2
pow[0x6]	285	1			T3	3		T10	2		T12	1
pow[0x7]	560	1			T3	6		T10	5		T12	7

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

226

1

T3

1

T10

3

T12

2

min

29970

1

T1

27

T2

9

T3

202

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	4	12	75.00

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x2]	0	1	1
pow[0x4]	0	1	1
pow[0x5]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	29970	1			T1	27		T2	9		T3	202
pow[0x3]	1	1			T235	1		-	-		-	-
pow[0x6]	1	1			T236	1		-	-		-	-
pow[0x7]	1	1			T150	1		-	-		-	-
pow[0x8]	4	1			T42	1		T19	1		T237	1
pow[0x9]	4	1			T232	1		T238	1		T239	1
pow[0xa]	21	1			T12	3		T86	1		T53	1
pow[0xb]	35	1			T41	1		T150	2		T214	1
pow[0xc]	73	1			T3	1		T41	1		T178	1
pow[0xd]	156	1			T3	3		T12	1		T42	2
pow[0xe]	341	1			T3	1		T10	1		T12	7
pow[0xf]	618	1			T3	4		T10	8		T12	5