Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.56	95.56	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	95.56	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.56	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	2	43	95.56

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	1	15	93.75	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2449	1			T3	17		T7	3		T10	17
auto[PWRUP]	136	1			T3	1		T10	2		T12	2
auto[ONEST_0]	96	1			T3	1		T11	1		T36	1
auto[ONEST_021]	17	1			T55	1		T377	1		T227	1
auto[ONEST_1]	87	1			T10	3		T11	1		T41	1
auto[ONEST_DONE]	7	1			T178	1		T240	1		T378	1
auto[LP_0]	152	1			T3	1		T10	2		T12	1
auto[LP_021]	30	1			T12	1		T150	2		T54	1
auto[LP_1]	143	1			T3	5		T10	2		T41	4
auto[LP_EVAL]	63	1			T10	1		T42	1		T178	2
auto[LP_SLP]	587	1			T3	7		T10	4		T12	4
auto[LP_PWRUP]	28	1			T12	1		T41	1		T42	1
auto[NP_0]	225	1			T3	1		T10	2		T12	2
auto[NP_021]	54	1			T12	1		T41	1		T42	1
auto[NP_1]	261	1			T3	3		T10	1		T41	5
auto[NP_EVAL]	38	1			T11	1		T12	2		T42	2

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

6

1

T214

1

T378

2

T25

1

min

2041

1

T3

8

T7

3

T10

5

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	2058	1			T3	9		T7	3		T10	5
pow[0x1]	13	1			T42	1		T36	2		T178	1
pow[0x2]	18	1			T53	1		T54	1		T48	1
pow[0x3]	35	1			T3	1		T42	1		T150	3
pow[0x4]	78	1			T3	1		T10	2		T41	2
pow[0x5]	158	1			T3	2		T10	1		T41	1
pow[0x6]	306	1			T3	3		T10	3		T12	2
pow[0x7]	567	1			T3	6		T10	7		T11	1

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

207

1

T3

2

T10

6

T12

2

min

1406

1

T3

1

T7

3

T11

8

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	1	15	93.75

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x5]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1410	1			T3	1		T7	3		T11	8
pow[0x1]	12	1			T291	1		T21	1		T284	2
pow[0x2]	34	1			T18	1		T48	1		T255	2
pow[0x3]	31	1			T11	1		T36	1		T38	2
pow[0x4]	51	1			T37	1		T16	1		T40	1
pow[0x6]	1	1			T379	1		-	-		-	-
pow[0x7]	3	1			T380	1		T240	1		T381	1
pow[0x8]	7	1			T178	1		T53	1		T48	1
pow[0x9]	5	1			T42	1		T240	1		T382	1
pow[0xa]	17	1			T12	1		T18	1		T240	1
pow[0xb]	44	1			T41	2		T42	1		T86	1
pow[0xc]	85	1			T10	1		T12	1		T41	2
pow[0xd]	157	1			T3	5		T10	1		T12	2
pow[0xe]	329	1			T3	7		T10	3		T12	4
pow[0xf]	668	1			T3	3		T10	7		T12	7