Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	96.00						96.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	24	96.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	24	96.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	0	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	2607	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	2472	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	2302	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	2708	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	2531	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	2513	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	2589	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	2406	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	2494	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	2377	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	2367	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	2471	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	2370	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	2488	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	2649	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	2530	0	0
adc_en_ctl_rd_A	2147483647	2150	0	0
adc_fsm_rst_rd_A	2147483647	1962	0	0
adc_intr_ctl_rd_A	2147483647	2214	0	0
adc_lp_sample_ctl_rd_A	2147483647	1967	0	0
adc_pd_ctl_rd_A	2147483647	2177	0	0
adc_sample_ctl_rd_A	2147483647	2066	0	0
adc_wakeup_ctl_rd_A	2147483647	1987	0	0
intr_enable_rd_A	2147483647	2622	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2607	0	0
T16	242698	29	0	0
T17	0	17	0	0
T18	0	21	0	0
T19	0	4	0	0
T20	0	22	0	0
T21	0	28	0	0
T22	0	25	0	0
T23	0	14	0	0
T24	0	28	0	0
T25	0	47	0	0
T26	151617	0	0	0
T27	452062	0	0	0
T28	10673	0	0	0
T29	896807	0	0	0
T30	283457	0	0	0
T31	100991	0	0	0
T32	173527	0	0	0
T33	388299	0	0	0
T34	184595	0	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2472	0	0
T16	242698	34	0	0
T17	0	20	0	0
T18	0	19	0	0
T19	0	3	0	0
T20	0	38	0	0
T21	0	43	0	0
T22	0	21	0	0
T23	0	24	0	0
T24	0	25	0	0
T25	0	22	0	0
T26	151617	0	0	0
T27	452062	0	0	0
T28	10673	0	0	0
T29	896807	0	0	0
T30	283457	0	0	0
T31	100991	0	0	0
T32	173527	0	0	0
T33	388299	0	0	0
T34	184595	0	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2302	0	0
T16	242698	40	0	0
T17	0	11	0	0
T18	0	40	0	0
T19	0	6	0	0
T20	0	34	0	0
T21	0	52	0	0
T22	0	28	0	0
T23	0	13	0	0
T24	0	13	0	0
T25	0	41	0	0
T26	151617	0	0	0
T27	452062	0	0	0
T28	10673	0	0	0
T29	896807	0	0	0
T30	283457	0	0	0
T31	100991	0	0	0
T32	173527	0	0	0
T33	388299	0	0	0
T34	184595	0	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2708	0	0
T16	242698	41	0	0
T17	0	11	0	0
T18	0	26	0	0
T19	0	15	0	0
T20	0	38	0	0
T21	0	25	0	0
T22	0	13	0	0
T23	0	22	0	0
T24	0	15	0	0
T25	0	45	0	0
T26	151617	0	0	0
T27	452062	0	0	0
T28	10673	0	0	0
T29	896807	0	0	0
T30	283457	0	0	0
T31	100991	0	0	0
T32	173527	0	0	0
T33	388299	0	0	0
T34	184595	0	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2531	0	0
T16	242698	34	0	0
T17	0	13	0	0
T18	0	41	0	0
T19	0	12	0	0
T20	0	27	0	0
T21	0	17	0	0
T22	0	11	0	0
T23	0	17	0	0
T24	0	15	0	0
T25	0	15	0	0
T26	151617	0	0	0
T27	452062	0	0	0
T28	10673	0	0	0
T29	896807	0	0	0
T30	283457	0	0	0
T31	100991	0	0	0
T32	173527	0	0	0
T33	388299	0	0	0
T34	184595	0	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2513	0	0
T16	242698	37	0	0
T17	0	21	0	0
T18	0	44	0	0
T19	0	7	0	0
T20	0	45	0	0
T21	0	42	0	0
T22	0	11	0	0
T23	0	12	0	0
T24	0	12	0	0
T25	0	23	0	0
T26	151617	0	0	0
T27	452062	0	0	0
T28	10673	0	0	0
T29	896807	0	0	0
T30	283457	0	0	0
T31	100991	0	0	0
T32	173527	0	0	0
T33	388299	0	0	0
T34	184595	0	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2589	0	0
T16	242698	36	0	0
T17	0	19	0	0
T18	0	24	0	0
T19	0	8	0	0
T20	0	35	0	0
T21	0	45	0	0
T22	0	9	0	0
T23	0	27	0	0
T24	0	34	0	0
T25	0	28	0	0
T26	151617	0	0	0
T27	452062	0	0	0
T28	10673	0	0	0
T29	896807	0	0	0
T30	283457	0	0	0
T31	100991	0	0	0
T32	173527	0	0	0
T33	388299	0	0	0
T34	184595	0	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2406	0	0
T16	242698	26	0	0
T17	0	12	0	0
T18	0	38	0	0
T19	0	10	0	0
T20	0	24	0	0
T21	0	39	0	0
T22	0	16	0	0
T23	0	20	0	0
T24	0	27	0	0
T25	0	28	0	0
T26	151617	0	0	0
T27	452062	0	0	0
T28	10673	0	0	0
T29	896807	0	0	0
T30	283457	0	0	0
T31	100991	0	0	0
T32	173527	0	0	0
T33	388299	0	0	0
T34	184595	0	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2494	0	0
T16	242698	20	0	0
T17	0	29	0	0
T18	0	12	0	0
T19	0	6	0	0
T20	0	32	0	0
T21	0	53	0	0
T22	0	11	0	0
T23	0	15	0	0
T24	0	14	0	0
T25	0	39	0	0
T26	151617	0	0	0
T27	452062	0	0	0
T28	10673	0	0	0
T29	896807	0	0	0
T30	283457	0	0	0
T31	100991	0	0	0
T32	173527	0	0	0
T33	388299	0	0	0
T34	184595	0	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2377	0	0
T16	242698	39	0	0
T17	0	16	0	0
T18	0	16	0	0
T19	0	1	0	0
T20	0	50	0	0
T21	0	36	0	0
T22	0	9	0	0
T23	0	23	0	0
T24	0	8	0	0
T25	0	37	0	0
T26	151617	0	0	0
T27	452062	0	0	0
T28	10673	0	0	0
T29	896807	0	0	0
T30	283457	0	0	0
T31	100991	0	0	0
T32	173527	0	0	0
T33	388299	0	0	0
T34	184595	0	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2367	0	0
T16	242698	27	0	0
T17	0	20	0	0
T18	0	33	0	0
T19	0	4	0	0
T20	0	27	0	0
T21	0	30	0	0
T22	0	8	0	0
T23	0	8	0	0
T24	0	25	0	0
T25	0	39	0	0
T26	151617	0	0	0
T27	452062	0	0	0
T28	10673	0	0	0
T29	896807	0	0	0
T30	283457	0	0	0
T31	100991	0	0	0
T32	173527	0	0	0
T33	388299	0	0	0
T34	184595	0	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2471	0	0
T16	242698	63	0	0
T17	0	18	0	0
T18	0	38	0	0
T19	0	14	0	0
T20	0	31	0	0
T21	0	38	0	0
T22	0	19	0	0
T23	0	9	0	0
T24	0	23	0	0
T25	0	20	0	0
T26	151617	0	0	0
T27	452062	0	0	0
T28	10673	0	0	0
T29	896807	0	0	0
T30	283457	0	0	0
T31	100991	0	0	0
T32	173527	0	0	0
T33	388299	0	0	0
T34	184595	0	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2370	0	0
T16	242698	38	0	0
T17	0	21	0	0
T18	0	39	0	0
T19	0	5	0	0
T20	0	55	0	0
T21	0	32	0	0
T22	0	16	0	0
T23	0	25	0	0
T24	0	25	0	0
T25	0	24	0	0
T26	151617	0	0	0
T27	452062	0	0	0
T28	10673	0	0	0
T29	896807	0	0	0
T30	283457	0	0	0
T31	100991	0	0	0
T32	173527	0	0	0
T33	388299	0	0	0
T34	184595	0	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2488	0	0
T16	242698	38	0	0
T17	0	11	0	0
T18	0	24	0	0
T19	0	1	0	0
T20	0	24	0	0
T21	0	34	0	0
T22	0	18	0	0
T23	0	12	0	0
T24	0	13	0	0
T25	0	32	0	0
T26	151617	0	0	0
T27	452062	0	0	0
T28	10673	0	0	0
T29	896807	0	0	0
T30	283457	0	0	0
T31	100991	0	0	0
T32	173527	0	0	0
T33	388299	0	0	0
T34	184595	0	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2649	0	0
T16	242698	43	0	0
T17	0	16	0	0
T18	0	22	0	0
T19	0	15	0	0
T20	0	36	0	0
T21	0	31	0	0
T22	0	15	0	0
T23	0	16	0	0
T24	0	41	0	0
T25	0	39	0	0
T26	151617	0	0	0
T27	452062	0	0	0
T28	10673	0	0	0
T29	896807	0	0	0
T30	283457	0	0	0
T31	100991	0	0	0
T32	173527	0	0	0
T33	388299	0	0	0
T34	184595	0	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2530	0	0
T16	242698	53	0	0
T17	0	22	0	0
T18	0	34	0	0
T19	0	17	0	0
T20	0	21	0	0
T21	0	49	0	0
T22	0	13	0	0
T23	0	25	0	0
T24	0	21	0	0
T25	0	25	0	0
T26	151617	0	0	0
T27	452062	0	0	0
T28	10673	0	0	0
T29	896807	0	0	0
T30	283457	0	0	0
T31	100991	0	0	0
T32	173527	0	0	0
T33	388299	0	0	0
T34	184595	0	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2150	0	0
T16	242698	39	0	0
T17	0	14	0	0
T18	0	32	0	0
T19	0	6	0	0
T20	0	40	0	0
T21	0	61	0	0
T22	0	9	0	0
T23	0	12	0	0
T24	0	16	0	0
T25	0	36	0	0
T26	151617	0	0	0
T27	452062	0	0	0
T28	10673	0	0	0
T29	896807	0	0	0
T30	283457	0	0	0
T31	100991	0	0	0
T32	173527	0	0	0
T33	388299	0	0	0
T34	184595	0	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1962	0	0
T16	242698	39	0	0
T17	0	19	0	0
T18	0	30	0	0
T19	0	5	0	0
T20	0	31	0	0
T21	0	30	0	0
T22	0	8	0	0
T23	0	27	0	0
T24	0	9	0	0
T25	0	31	0	0
T26	151617	0	0	0
T27	452062	0	0	0
T28	10673	0	0	0
T29	896807	0	0	0
T30	283457	0	0	0
T31	100991	0	0	0
T32	173527	0	0	0
T33	388299	0	0	0
T34	184595	0	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2214	0	0
T16	242698	40	0	0
T17	0	25	0	0
T18	0	22	0	0
T19	0	10	0	0
T20	0	44	0	0
T21	0	31	0	0
T22	0	11	0	0
T23	0	20	0	0
T24	0	13	0	0
T25	0	39	0	0
T26	151617	0	0	0
T27	452062	0	0	0
T28	10673	0	0	0
T29	896807	0	0	0
T30	283457	0	0	0
T31	100991	0	0	0
T32	173527	0	0	0
T33	388299	0	0	0
T34	184595	0	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1967	0	0
T16	242698	46	0	0
T17	0	19	0	0
T18	0	22	0	0
T19	0	8	0	0
T20	0	43	0	0
T21	0	31	0	0
T22	0	11	0	0
T23	0	11	0	0
T24	0	21	0	0
T25	0	54	0	0
T26	151617	0	0	0
T27	452062	0	0	0
T28	10673	0	0	0
T29	896807	0	0	0
T30	283457	0	0	0
T31	100991	0	0	0
T32	173527	0	0	0
T33	388299	0	0	0
T34	184595	0	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2177	0	0
T16	242698	37	0	0
T17	0	22	0	0
T18	0	42	0	0
T19	0	17	0	0
T20	0	36	0	0
T21	0	32	0	0
T22	0	9	0	0
T23	0	23	0	0
T24	0	14	0	0
T25	0	21	0	0
T26	151617	0	0	0
T27	452062	0	0	0
T28	10673	0	0	0
T29	896807	0	0	0
T30	283457	0	0	0
T31	100991	0	0	0
T32	173527	0	0	0
T33	388299	0	0	0
T34	184595	0	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2066	0	0
T16	242698	48	0	0
T17	0	33	0	0
T18	0	49	0	0
T19	0	12	0	0
T20	0	32	0	0
T21	0	37	0	0
T22	0	28	0	0
T23	0	13	0	0
T24	0	17	0	0
T25	0	36	0	0
T26	151617	0	0	0
T27	452062	0	0	0
T28	10673	0	0	0
T29	896807	0	0	0
T30	283457	0	0	0
T31	100991	0	0	0
T32	173527	0	0	0
T33	388299	0	0	0
T34	184595	0	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1987	0	0
T16	242698	47	0	0
T17	0	17	0	0
T18	0	14	0	0
T19	0	17	0	0
T20	0	38	0	0
T21	0	35	0	0
T22	0	16	0	0
T23	0	18	0	0
T24	0	16	0	0
T25	0	55	0	0
T26	151617	0	0	0
T27	452062	0	0	0
T28	10673	0	0	0
T29	896807	0	0	0
T30	283457	0	0	0
T31	100991	0	0	0
T32	173527	0	0	0
T33	388299	0	0	0
T34	184595	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2622	0	0
T16	242698	58	0	0
T17	0	31	0	0
T18	0	94	0	0
T19	0	10	0	0
T20	0	47	0	0
T21	0	25	0	0
T22	0	9	0	0
T23	0	16	0	0
T24	0	55	0	0
T26	151617	0	0	0
T27	452062	0	0	0
T28	10673	0	0	0
T29	896807	0	0	0
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