Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1218119	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1191288

1

T1

475

T2

2876

T3

22

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2115403	1			T1	857		T2	5140		T14	1
values[0x0]	146436	1			T1	47		T2	333		T3	26
values[0x1]	147568	1			T1	50		T2	290		T3	11

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	974977	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1434430

1

T1

570

T2

3461

T3

24

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7228	1			T1	7		T2	22		T3	1
valid_sources[0x01]	9891	1			T1	2		T2	25		T4	32
valid_sources[0x02]	10915	1			T1	2		T2	25		T4	39
valid_sources[0x03]	7081	1			T1	3		T2	9		T4	48
valid_sources[0x04]	7584	1			T1	4		T2	24		T4	40
valid_sources[0x05]	12588	1			T1	3		T2	26		T4	39
valid_sources[0x06]	7725	1			T1	2		T2	23		T4	39
valid_sources[0x07]	8471	1			T1	3		T2	35		T4	30
valid_sources[0x08]	7520	1			T1	2		T2	22		T4	24
valid_sources[0x09]	10489	1			T1	2		T2	20		T4	32
valid_sources[0x0a]	21981	1			T1	5		T2	24		T4	28
valid_sources[0x0b]	7337	1			T1	3		T2	17		T4	39
valid_sources[0x0c]	11795	1			T1	3		T2	19		T4	38
valid_sources[0x0d]	6895	1			T2	33		T4	36		T5	3
valid_sources[0x0e]	10682	1			T1	4		T2	15		T4	31
valid_sources[0x0f]	7731	1			T1	3		T2	14		T4	42
valid_sources[0x10]	7412	1			T1	2		T2	17		T4	31
valid_sources[0x11]	7347	1			T1	5		T2	31		T4	39
valid_sources[0x12]	15369	1			T1	4		T2	31		T4	33
valid_sources[0x13]	7142	1			T1	2		T2	21		T3	1
valid_sources[0x14]	7543	1			T1	6		T2	22		T4	41
valid_sources[0x15]	8261	1			T1	2		T2	17		T4	41
valid_sources[0x16]	11438	1			T1	3		T2	24		T4	32
valid_sources[0x17]	16241	1			T1	3		T2	14		T4	46
valid_sources[0x18]	7178	1			T1	3		T2	24		T4	41
valid_sources[0x19]	9264	1			T1	2		T2	25		T4	26
valid_sources[0x1a]	8595	1			T1	5		T2	26		T4	30
valid_sources[0x1b]	7164	1			T1	4		T2	23		T4	24
valid_sources[0x1c]	7156	1			T1	3		T2	25		T4	35
valid_sources[0x1d]	12095	1			T1	3		T2	22		T4	21
valid_sources[0x1e]	9164	1			T1	1		T2	25		T4	38
valid_sources[0x1f]	7298	1			T1	5		T2	23		T4	23
valid_sources[0x20]	7716	1			T1	1		T2	21		T4	35
valid_sources[0x21]	11385	1			T1	2		T2	24		T3	1
valid_sources[0x22]	12981	1			T1	3		T2	20		T3	2
valid_sources[0x23]	15520	1			T1	2		T2	26		T4	40
valid_sources[0x24]	7168	1			T1	3		T2	30		T4	38
valid_sources[0x25]	8326	1			T1	1		T2	16		T4	33
valid_sources[0x26]	7258	1			T2	18		T4	27		T5	5
valid_sources[0x27]	7284	1			T1	2		T2	32		T4	40
valid_sources[0x28]	7350	1			T1	4		T2	19		T3	2
valid_sources[0x29]	7379	1			T1	6		T2	19		T4	34
valid_sources[0x2a]	8630	1			T1	3		T2	30		T4	30
valid_sources[0x2b]	7589	1			T1	3		T2	21		T4	36
valid_sources[0x2c]	11476	1			T1	4		T2	26		T3	2
valid_sources[0x2d]	11591	1			T1	5		T2	20		T4	36
valid_sources[0x2e]	10691	1			T1	5		T2	22		T4	29
valid_sources[0x2f]	8095	1			T1	2		T2	16		T4	32
valid_sources[0x30]	10357	1			T1	2		T2	28		T4	25
valid_sources[0x31]	9996	1			T2	30		T4	35		T5	8
valid_sources[0x32]	10711	1			T1	5		T2	17		T4	34
valid_sources[0x33]	7744	1			T1	6		T2	15		T4	28
valid_sources[0x34]	12170	1			T1	2		T2	16		T4	32
valid_sources[0x35]	7370	1			T1	8		T2	23		T4	30
valid_sources[0x36]	12037	1			T1	2		T2	22		T3	1
valid_sources[0x37]	6868	1			T1	7		T2	16		T4	35
valid_sources[0x38]	15367	1			T1	3		T2	26		T4	28
valid_sources[0x39]	8153	1			T1	5		T2	18		T4	28
valid_sources[0x3a]	8043	1			T1	7		T2	20		T4	38
valid_sources[0x3b]	11035	1			T1	3		T2	25		T4	28
valid_sources[0x3c]	7169	1			T1	4		T2	23		T4	28
valid_sources[0x3d]	7589	1			T1	4		T2	21		T4	31
valid_sources[0x3e]	7239	1			T1	3		T2	25		T4	27
valid_sources[0x3f]	8810	1			T1	3		T2	23		T4	32
valid_sources[0x40]	10139	1			T1	6		T2	24		T4	37
valid_sources[0x41]	7529	1			T1	5		T2	30		T4	29
valid_sources[0x42]	11798	1			T1	2		T2	22		T4	25
valid_sources[0x43]	7381	1			T1	3		T2	36		T3	1
valid_sources[0x44]	8260	1			T1	7		T2	20		T4	30
valid_sources[0x45]	7961	1			T1	2		T2	28		T4	31
valid_sources[0x46]	7039	1			T1	1		T2	19		T4	41
valid_sources[0x47]	7294	1			T1	7		T2	26		T4	48
valid_sources[0x48]	7113	1			T1	2		T2	23		T4	35
valid_sources[0x49]	8262	1			T1	4		T2	31		T4	32
valid_sources[0x4a]	10249	1			T1	6		T2	18		T4	29
valid_sources[0x4b]	8239	1			T1	3		T2	19		T4	34
valid_sources[0x4c]	7855	1			T1	3		T2	18		T4	39
valid_sources[0x4d]	7171	1			T1	4		T2	23		T3	1
valid_sources[0x4e]	7995	1			T1	9		T2	14		T3	2
valid_sources[0x4f]	7780	1			T1	3		T2	23		T4	34
valid_sources[0x50]	12481	1			T1	7		T2	37		T4	27
valid_sources[0x51]	12063	1			T1	3		T2	28		T4	31
valid_sources[0x52]	7460	1			T1	6		T2	25		T4	25
valid_sources[0x53]	10883	1			T1	3		T2	22		T4	31
valid_sources[0x54]	7412	1			T1	5		T2	18		T4	35
valid_sources[0x55]	7345	1			T1	2		T2	22		T4	33
valid_sources[0x56]	7110	1			T1	4		T2	18		T4	24
valid_sources[0x57]	9860	1			T1	6		T2	22		T4	29
valid_sources[0x58]	7070	1			T1	1		T2	25		T3	1
valid_sources[0x59]	7218	1			T1	3		T2	28		T4	31
valid_sources[0x5a]	9911	1			T1	5		T2	27		T3	1
valid_sources[0x5b]	17160	1			T1	4		T2	26		T4	35
valid_sources[0x5c]	6771	1			T1	1		T2	20		T3	1
valid_sources[0x5d]	7552	1			T1	3		T2	23		T3	1
valid_sources[0x5e]	9866	1			T1	2		T2	19		T4	40
valid_sources[0x5f]	18007	1			T1	1		T2	25		T4	31
valid_sources[0x60]	15456	1			T1	3		T2	13		T4	25
valid_sources[0x61]	11158	1			T1	4		T2	16		T3	1
valid_sources[0x62]	8536	1			T1	4		T2	22		T4	35
valid_sources[0x63]	7478	1			T1	5		T2	27		T4	30
valid_sources[0x64]	7475	1			T1	8		T2	8		T4	25
valid_sources[0x65]	7135	1			T1	2		T2	29		T4	39
valid_sources[0x66]	9412	1			T1	2		T2	18		T4	30
valid_sources[0x67]	11480	1			T1	6		T2	19		T4	27
valid_sources[0x68]	24415	1			T1	2		T2	22		T4	34
valid_sources[0x69]	9681	1			T1	3		T2	26		T4	42
valid_sources[0x6a]	7389	1			T1	4		T2	23		T4	44
valid_sources[0x6b]	7433	1			T1	3		T2	18		T4	20
valid_sources[0x6c]	10095	1			T1	7		T2	20		T4	41
valid_sources[0x6d]	12230	1			T1	4		T2	23		T4	34
valid_sources[0x6e]	7648	1			T1	5		T2	26		T4	24
valid_sources[0x6f]	8670	1			T1	6		T2	9		T4	44
valid_sources[0x70]	7316	1			T1	2		T2	29		T4	41
valid_sources[0x71]	9668	1			T1	6		T2	17		T4	31
valid_sources[0x72]	8249	1			T1	4		T2	19		T4	36
valid_sources[0x73]	12280	1			T1	6		T2	25		T4	33
valid_sources[0x74]	7242	1			T1	2		T2	21		T3	1
valid_sources[0x75]	8010	1			T1	8		T2	24		T4	36
valid_sources[0x76]	7347	1			T1	6		T2	26		T4	34
valid_sources[0x77]	9733	1			T1	5		T2	21		T4	34
valid_sources[0x78]	7247	1			T1	5		T2	23		T4	33
valid_sources[0x79]	8194	1			T1	6		T2	20		T4	38
valid_sources[0x7a]	7863	1			T1	8		T2	22		T4	35
valid_sources[0x7b]	7195	1			T1	5		T2	30		T3	1
valid_sources[0x7c]	7564	1			T1	3		T2	25		T4	36
valid_sources[0x7d]	8517	1			T1	6		T2	13		T4	40
valid_sources[0x7e]	7368	1			T1	1		T2	18		T4	30
valid_sources[0x7f]	10933	1			T1	4		T2	26		T4	32
valid_sources[0x80]	7435	1			T1	2		T2	25		T4	31

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1053629

1

T1

432

T2

2621

T4

4084

values[0x0]

all_enables

biggest_size

79719

1

T1

28

T2

165

T3

16

values[0x1]

all_enables

biggest_size

57940

1

T1

15

T2

90

T3

6