Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
86.67	86.67	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	86.67	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
86.67	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	6	39	86.67

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	5	11	68.75	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	29660	1			T1	8		T2	15		T4	17
auto[PWRUP]	104	1			T5	3		T8	1		T45	1
auto[ONEST_0]	53	1			T45	2		T13	1		T15	1
auto[ONEST_021]	19	1			T28	1		T58	1		T210	1
auto[ONEST_1]	85	1			T5	1		T13	1		T57	1
auto[ONEST_DONE]	3	1			T211	1		T212	1		T213	1
auto[LP_0]	123	1			T5	1		T8	2		T45	2
auto[LP_021]	18	1			T45	1		T57	1		T214	2
auto[LP_1]	136	1			T5	1		T8	3		T45	1
auto[LP_EVAL]	61	1			T5	2		T45	2		T15	1
auto[LP_SLP]	497	1			T5	10		T8	9		T45	4
auto[LP_PWRUP]	23	1			T45	1		T57	1		T60	1
auto[NP_0]	147	1			T5	2		T8	4		T45	2
auto[NP_021]	34	1			T45	1		T57	1		T60	1
auto[NP_1]	166	1			T5	4		T8	2		T45	4
auto[NP_EVAL]	40	1			T5	1		T8	1		T13	2

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

11

1

T215

2

T157

1

T216

1

min

29174

1

T1

8

T2

15

T4

17

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	29186	1			T1	8		T2	15		T4	17
pow[0x1]	9	1			T45	1		T217	1		T216	1
pow[0x2]	13	1			T8	1		T16	1		T18	1
pow[0x3]	19	1			T45	1		T57	1		T59	1
pow[0x4]	71	1			T5	2		T8	1		T57	1
pow[0x5]	128	1			T8	2		T13	1		T57	4
pow[0x6]	247	1			T5	3		T8	5		T45	5
pow[0x7]	487	1			T5	11		T8	4		T45	4

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

196

1

T5

4

T8

1

T45

1

min

28697

1

T1

8

T2

15

T4

17

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	5	11	68.75

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x2]	0	1	1
pow[0x3]	0	1	1
pow[0x4]	0	1	1
pow[0x5]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	28697	1			T1	8		T2	15		T4	17
pow[0x6]	1	1			T218	1		-	-		-	-
pow[0x7]	2	1			T217	1		T219	1		-	-
pow[0x8]	4	1			T45	1		T220	1		T221	1
pow[0x9]	9	1			T222	2		T223	1		T175	1
pow[0xa]	18	1			T5	1		T45	2		T224	1
pow[0xb]	39	1			T57	1		T18	2		T215	1
pow[0xc]	68	1			T5	1		T8	1		T45	1
pow[0xd]	149	1			T5	3		T8	4		T45	1
pow[0xe]	272	1			T5	4		T8	5		T45	3
pow[0xf]	581	1			T5	8		T8	11		T45	8