Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
93.33	93.33	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	93.33	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.33	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	3	42	93.33

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	2	14	87.50	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2306	1			T2	4		T5	24		T8	13
auto[PWRUP]	128	1			T5	3		T8	3		T45	1
auto[ONEST_0]	71	1			T5	1		T8	3		T9	1
auto[ONEST_021]	16	1			T13	1		T60	1		T210	1
auto[ONEST_1]	99	1			T8	2		T57	4		T15	1
auto[ONEST_DONE]	2	1			T16	1		T337	1		-	-
auto[LP_0]	134	1			T5	3		T8	1		T45	4
auto[LP_021]	20	1			T45	1		T58	1		T210	1
auto[LP_1]	144	1			T5	3		T8	1		T45	5
auto[LP_EVAL]	50	1			T5	2		T57	1		T48	1
auto[LP_SLP]	508	1			T5	10		T8	6		T9	1
auto[LP_PWRUP]	30	1			T8	3		T13	1		T16	1
auto[NP_0]	219	1			T5	3		T45	1		T57	2
auto[NP_021]	40	1			T5	1		T45	1		T57	1
auto[NP_1]	230	1			T5	2		T9	1		T45	3
auto[NP_EVAL]	33	1			T8	1		T48	1		T49	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

9

1

T58

1

T224

1

T338

1

min

1984

1

T2

4

T5

16

T8

9

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1989	1			T2	4		T5	16		T8	9
pow[0x1]	12	1			T9	1		T57	1		T339	1
pow[0x2]	16	1			T60	1		T49	1		T17	1
pow[0x3]	40	1			T5	2		T45	1		T60	1
pow[0x4]	54	1			T5	1		T60	2		T58	2
pow[0x5]	121	1			T5	1		T8	1		T45	1
pow[0x6]	238	1			T5	7		T8	4		T45	5
pow[0x7]	548	1			T5	7		T8	5		T45	9

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

204

1

T5

3

T8

3

T45

5

min

1387

1

T2

4

T5

6

T8

1

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	2	14	87.50

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x6]	0	1	1
pow[0x7]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1392	1			T2	4		T5	6		T8	1
pow[0x1]	21	1			T28	2		T48	1		T17	1
pow[0x2]	18	1			T15	1		T267	1		T20	1
pow[0x3]	31	1			T49	1		T52	1		T216	1
pow[0x4]	72	1			T9	1		T28	1		T16	1
pow[0x5]	1	1			T218	1		-	-		-	-
pow[0x8]	3	1			T28	1		T210	1		T216	1
pow[0x9]	10	1			T45	1		T242	1		T338	1
pow[0xa]	31	1			T5	2		T57	1		T164	1
pow[0xb]	23	1			T8	2		T58	1		T164	1
pow[0xc]	69	1			T5	1		T8	1		T45	1
pow[0xd]	120	1			T5	1		T8	1		T45	1
pow[0xe]	278	1			T5	5		T8	5		T45	4
pow[0xf]	592	1			T5	7		T8	6		T45	5