Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	96.00						96.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	24	96.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	24	96.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	0	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	2328	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	2192	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	2312	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	2301	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	2259	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	2339	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	2121	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	2229	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	2117	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	2334	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	2321	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	2385	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	2222	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	2300	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	2287	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	2179	0	0
adc_en_ctl_rd_A	2147483647	2008	0	0
adc_fsm_rst_rd_A	2147483647	1707	0	0
adc_intr_ctl_rd_A	2147483647	2115	0	0
adc_lp_sample_ctl_rd_A	2147483647	1873	0	0
adc_pd_ctl_rd_A	2147483647	1949	0	0
adc_sample_ctl_rd_A	2147483647	1899	0	0
adc_wakeup_ctl_rd_A	2147483647	1938	0	0
intr_enable_rd_A	2147483647	2410	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2328	0	0
T15	313020	37	0	0
T16	0	5	0	0
T17	0	3	0	0
T18	0	1	0	0
T19	0	23	0	0
T20	0	32	0	0
T21	0	25	0	0
T22	0	19	0	0
T23	0	33	0	0
T24	0	34	0	0
T25	341897	0	0	0
T26	271789	0	0	0
T27	170366	0	0	0
T28	384768	0	0	0
T29	326154	0	0	0
T30	294559	0	0	0
T31	414185	0	0	0
T32	394289	0	0	0
T33	159491	0	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2192	0	0
T15	313020	30	0	0
T16	0	9	0	0
T17	0	10	0	0
T18	0	20	0	0
T19	0	26	0	0
T20	0	35	0	0
T21	0	13	0	0
T22	0	10	0	0
T23	0	33	0	0
T24	0	49	0	0
T25	341897	0	0	0
T26	271789	0	0	0
T27	170366	0	0	0
T28	384768	0	0	0
T29	326154	0	0	0
T30	294559	0	0	0
T31	414185	0	0	0
T32	394289	0	0	0
T33	159491	0	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2312	0	0
T15	313020	50	0	0
T16	0	8	0	0
T17	0	14	0	0
T18	0	23	0	0
T19	0	24	0	0
T20	0	32	0	0
T21	0	22	0	0
T22	0	28	0	0
T23	0	23	0	0
T24	0	41	0	0
T25	341897	0	0	0
T26	271789	0	0	0
T27	170366	0	0	0
T28	384768	0	0	0
T29	326154	0	0	0
T30	294559	0	0	0
T31	414185	0	0	0
T32	394289	0	0	0
T33	159491	0	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2301	0	0
T15	313020	29	0	0
T16	0	14	0	0
T17	0	21	0	0
T18	0	18	0	0
T19	0	4	0	0
T20	0	38	0	0
T21	0	17	0	0
T22	0	32	0	0
T23	0	10	0	0
T24	0	36	0	0
T25	341897	0	0	0
T26	271789	0	0	0
T27	170366	0	0	0
T28	384768	0	0	0
T29	326154	0	0	0
T30	294559	0	0	0
T31	414185	0	0	0
T32	394289	0	0	0
T33	159491	0	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2259	0	0
T15	313020	37	0	0
T16	0	19	0	0
T17	0	14	0	0
T18	0	8	0	0
T19	0	7	0	0
T20	0	49	0	0
T21	0	20	0	0
T22	0	19	0	0
T23	0	13	0	0
T24	0	19	0	0
T25	341897	0	0	0
T26	271789	0	0	0
T27	170366	0	0	0
T28	384768	0	0	0
T29	326154	0	0	0
T30	294559	0	0	0
T31	414185	0	0	0
T32	394289	0	0	0
T33	159491	0	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2339	0	0
T15	313020	27	0	0
T16	0	9	0	0
T17	0	21	0	0
T18	0	19	0	0
T19	0	16	0	0
T20	0	35	0	0
T21	0	21	0	0
T22	0	25	0	0
T23	0	20	0	0
T24	0	39	0	0
T25	341897	0	0	0
T26	271789	0	0	0
T27	170366	0	0	0
T28	384768	0	0	0
T29	326154	0	0	0
T30	294559	0	0	0
T31	414185	0	0	0
T32	394289	0	0	0
T33	159491	0	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2121	0	0
T15	313020	39	0	0
T16	0	7	0	0
T17	0	12	0	0
T18	0	15	0	0
T19	0	15	0	0
T20	0	34	0	0
T21	0	23	0	0
T22	0	24	0	0
T23	0	16	0	0
T24	0	40	0	0
T25	341897	0	0	0
T26	271789	0	0	0
T27	170366	0	0	0
T28	384768	0	0	0
T29	326154	0	0	0
T30	294559	0	0	0
T31	414185	0	0	0
T32	394289	0	0	0
T33	159491	0	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2229	0	0
T15	313020	38	0	0
T16	0	9	0	0
T17	0	12	0	0
T18	0	12	0	0
T19	0	10	0	0
T20	0	32	0	0
T21	0	21	0	0
T22	0	23	0	0
T23	0	28	0	0
T24	0	33	0	0
T25	341897	0	0	0
T26	271789	0	0	0
T27	170366	0	0	0
T28	384768	0	0	0
T29	326154	0	0	0
T30	294559	0	0	0
T31	414185	0	0	0
T32	394289	0	0	0
T33	159491	0	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2117	0	0
T15	313020	25	0	0
T17	0	9	0	0
T18	0	16	0	0
T19	0	14	0	0
T20	0	28	0	0
T21	0	18	0	0
T22	0	29	0	0
T23	0	17	0	0
T24	0	38	0	0
T25	341897	0	0	0
T26	271789	0	0	0
T27	170366	0	0	0
T28	384768	0	0	0
T29	326154	0	0	0
T30	294559	0	0	0
T31	414185	0	0	0
T32	394289	0	0	0
T33	159491	0	0	0
T34	0	27	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2334	0	0
T15	313020	31	0	0
T16	0	15	0	0
T17	0	10	0	0
T18	0	26	0	0
T19	0	24	0	0
T20	0	29	0	0
T21	0	23	0	0
T22	0	18	0	0
T23	0	17	0	0
T24	0	41	0	0
T25	341897	0	0	0
T26	271789	0	0	0
T27	170366	0	0	0
T28	384768	0	0	0
T29	326154	0	0	0
T30	294559	0	0	0
T31	414185	0	0	0
T32	394289	0	0	0
T33	159491	0	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2321	0	0
T15	313020	38	0	0
T16	0	22	0	0
T17	0	16	0	0
T18	0	24	0	0
T19	0	22	0	0
T20	0	31	0	0
T21	0	12	0	0
T22	0	11	0	0
T23	0	12	0	0
T24	0	38	0	0
T25	341897	0	0	0
T26	271789	0	0	0
T27	170366	0	0	0
T28	384768	0	0	0
T29	326154	0	0	0
T30	294559	0	0	0
T31	414185	0	0	0
T32	394289	0	0	0
T33	159491	0	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2385	0	0
T15	313020	26	0	0
T16	0	9	0	0
T17	0	13	0	0
T18	0	29	0	0
T19	0	24	0	0
T20	0	39	0	0
T21	0	23	0	0
T22	0	25	0	0
T23	0	25	0	0
T24	0	52	0	0
T25	341897	0	0	0
T26	271789	0	0	0
T27	170366	0	0	0
T28	384768	0	0	0
T29	326154	0	0	0
T30	294559	0	0	0
T31	414185	0	0	0
T32	394289	0	0	0
T33	159491	0	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2222	0	0
T15	313020	28	0	0
T16	0	15	0	0
T17	0	13	0	0
T18	0	21	0	0
T19	0	21	0	0
T20	0	32	0	0
T21	0	17	0	0
T22	0	14	0	0
T23	0	21	0	0
T24	0	50	0	0
T25	341897	0	0	0
T26	271789	0	0	0
T27	170366	0	0	0
T28	384768	0	0	0
T29	326154	0	0	0
T30	294559	0	0	0
T31	414185	0	0	0
T32	394289	0	0	0
T33	159491	0	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2300	0	0
T15	313020	35	0	0
T16	0	6	0	0
T17	0	3	0	0
T18	0	31	0	0
T19	0	17	0	0
T20	0	24	0	0
T21	0	9	0	0
T22	0	21	0	0
T23	0	14	0	0
T24	0	41	0	0
T25	341897	0	0	0
T26	271789	0	0	0
T27	170366	0	0	0
T28	384768	0	0	0
T29	326154	0	0	0
T30	294559	0	0	0
T31	414185	0	0	0
T32	394289	0	0	0
T33	159491	0	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2287	0	0
T15	313020	52	0	0
T16	0	16	0	0
T17	0	1	0	0
T18	0	40	0	0
T19	0	16	0	0
T20	0	51	0	0
T21	0	30	0	0
T22	0	17	0	0
T23	0	16	0	0
T24	0	38	0	0
T25	341897	0	0	0
T26	271789	0	0	0
T27	170366	0	0	0
T28	384768	0	0	0
T29	326154	0	0	0
T30	294559	0	0	0
T31	414185	0	0	0
T32	394289	0	0	0
T33	159491	0	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2179	0	0
T15	313020	57	0	0
T16	0	22	0	0
T17	0	1	0	0
T18	0	20	0	0
T19	0	19	0	0
T20	0	23	0	0
T21	0	24	0	0
T22	0	22	0	0
T23	0	29	0	0
T24	0	28	0	0
T25	341897	0	0	0
T26	271789	0	0	0
T27	170366	0	0	0
T28	384768	0	0	0
T29	326154	0	0	0
T30	294559	0	0	0
T31	414185	0	0	0
T32	394289	0	0	0
T33	159491	0	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2008	0	0
T15	313020	28	0	0
T16	0	22	0	0
T17	0	13	0	0
T18	0	20	0	0
T19	0	16	0	0
T20	0	20	0	0
T21	0	8	0	0
T22	0	15	0	0
T23	0	25	0	0
T24	0	49	0	0
T25	341897	0	0	0
T26	271789	0	0	0
T27	170366	0	0	0
T28	384768	0	0	0
T29	326154	0	0	0
T30	294559	0	0	0
T31	414185	0	0	0
T32	394289	0	0	0
T33	159491	0	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1707	0	0
T15	313020	50	0	0
T16	0	19	0	0
T17	0	15	0	0
T18	0	11	0	0
T19	0	19	0	0
T20	0	33	0	0
T21	0	16	0	0
T22	0	13	0	0
T23	0	18	0	0
T24	0	33	0	0
T25	341897	0	0	0
T26	271789	0	0	0
T27	170366	0	0	0
T28	384768	0	0	0
T29	326154	0	0	0
T30	294559	0	0	0
T31	414185	0	0	0
T32	394289	0	0	0
T33	159491	0	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2115	0	0
T15	313020	28	0	0
T16	0	4	0	0
T17	0	4	0	0
T18	0	4	0	0
T19	0	20	0	0
T20	0	37	0	0
T21	0	24	0	0
T22	0	26	0	0
T23	0	29	0	0
T24	0	43	0	0
T25	341897	0	0	0
T26	271789	0	0	0
T27	170366	0	0	0
T28	384768	0	0	0
T29	326154	0	0	0
T30	294559	0	0	0
T31	414185	0	0	0
T32	394289	0	0	0
T33	159491	0	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1873	0	0
T15	313020	25	0	0
T16	0	12	0	0
T17	0	7	0	0
T18	0	24	0	0
T19	0	26	0	0
T20	0	25	0	0
T21	0	19	0	0
T22	0	13	0	0
T23	0	19	0	0
T24	0	30	0	0
T25	341897	0	0	0
T26	271789	0	0	0
T27	170366	0	0	0
T28	384768	0	0	0
T29	326154	0	0	0
T30	294559	0	0	0
T31	414185	0	0	0
T32	394289	0	0	0
T33	159491	0	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1949	0	0
T15	313020	30	0	0
T16	0	10	0	0
T17	0	10	0	0
T18	0	9	0	0
T19	0	30	0	0
T20	0	39	0	0
T21	0	27	0	0
T22	0	34	0	0
T23	0	16	0	0
T24	0	45	0	0
T25	341897	0	0	0
T26	271789	0	0	0
T27	170366	0	0	0
T28	384768	0	0	0
T29	326154	0	0	0
T30	294559	0	0	0
T31	414185	0	0	0
T32	394289	0	0	0
T33	159491	0	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1899	0	0
T15	313020	17	0	0
T16	0	1	0	0
T17	0	9	0	0
T18	0	29	0	0
T19	0	18	0	0
T20	0	51	0	0
T21	0	25	0	0
T22	0	15	0	0
T23	0	9	0	0
T24	0	28	0	0
T25	341897	0	0	0
T26	271789	0	0	0
T27	170366	0	0	0
T28	384768	0	0	0
T29	326154	0	0	0
T30	294559	0	0	0
T31	414185	0	0	0
T32	394289	0	0	0
T33	159491	0	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1938	0	0
T15	313020	40	0	0
T16	0	5	0	0
T17	0	30	0	0
T18	0	18	0	0
T19	0	17	0	0
T20	0	31	0	0
T21	0	25	0	0
T22	0	23	0	0
T23	0	27	0	0
T24	0	32	0	0
T25	341897	0	0	0
T26	271789	0	0	0
T27	170366	0	0	0
T28	384768	0	0	0
T29	326154	0	0	0
T30	294559	0	0	0
T31	414185	0	0	0
T32	394289	0	0	0
T33	159491	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2410	0	0
T15	0	80	0	0
T16	0	2	0	0
T17	0	38	0	0
T18	0	38	0	0
T19	0	17	0	0
T20	0	75	0	0
T21	0	55	0	0
T22	0	11	0	0
T23	0	14	0	0
T35	242743	10	0	0
T36	42396	0	0	0
T37	290089	0	0	0
T38	368902	0	0	0
T39	154407	0	0	0
T40	156667	0	0	0
T41	9419	0	0	0
T42	157127	0	0	0
T43	286362	0	0	0
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