Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1234414	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1205916

1

T1

4215

T2

1464

T4

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2139000	1			T1	7960		T2	2607		T4	1
values[0x0]	149616	1			T1	288		T2	159		T4	1
values[0x1]	151714	1			T1	292		T2	164		T4	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	988679	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1451651

1

T1

5046

T2

1742

T4

2

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	8418	1			T1	13		T2	11		T6	22
valid_sources[0x01]	6937	1			T1	35		T2	5		T6	7
valid_sources[0x02]	8199	1			T1	23		T2	18		T6	12
valid_sources[0x03]	12380	1			T1	44		T2	27		T4	1
valid_sources[0x04]	12326	1			T1	25		T2	5		T6	9
valid_sources[0x05]	8036	1			T1	10		T2	6		T6	13
valid_sources[0x06]	7543	1			T1	10		T2	13		T6	15
valid_sources[0x07]	11895	1			T1	61		T2	6		T6	21
valid_sources[0x08]	6736	1			T1	19		T2	17		T6	17
valid_sources[0x09]	8145	1			T1	15		T2	12		T6	14
valid_sources[0x0a]	7517	1			T1	57		T2	7		T6	19
valid_sources[0x0b]	10114	1			T1	26		T2	25		T6	13
valid_sources[0x0c]	7460	1			T1	50		T2	7		T6	16
valid_sources[0x0d]	7161	1			T1	28		T2	11		T6	18
valid_sources[0x0e]	7452	1			T1	21		T2	17		T6	19
valid_sources[0x0f]	7146	1			T1	97		T2	15		T6	26
valid_sources[0x10]	20264	1			T1	50		T2	12		T6	14
valid_sources[0x11]	8204	1			T1	21		T2	11		T6	17
valid_sources[0x12]	12011	1			T1	20		T2	21		T6	18
valid_sources[0x13]	7303	1			T1	32		T2	11		T6	24
valid_sources[0x14]	13057	1			T1	31		T2	14		T6	12
valid_sources[0x15]	12878	1			T1	57		T2	12		T6	26
valid_sources[0x16]	8059	1			T1	37		T2	8		T6	13
valid_sources[0x17]	12377	1			T1	53		T2	17		T6	16
valid_sources[0x18]	7529	1			T1	71		T2	17		T6	18
valid_sources[0x19]	7017	1			T1	29		T2	8		T6	17
valid_sources[0x1a]	11898	1			T1	27		T2	5		T3	837
valid_sources[0x1b]	11647	1			T1	16		T2	6		T6	23
valid_sources[0x1c]	7041	1			T1	40		T2	14		T6	14
valid_sources[0x1d]	7059	1			T1	19		T2	12		T6	16
valid_sources[0x1e]	6963	1			T1	35		T2	14		T6	23
valid_sources[0x1f]	12839	1			T1	70		T2	23		T6	25
valid_sources[0x20]	8000	1			T1	42		T2	8		T6	17
valid_sources[0x21]	8838	1			T1	22		T2	10		T6	22
valid_sources[0x22]	9739	1			T1	40		T2	8		T6	10
valid_sources[0x23]	7755	1			T1	33		T2	7		T6	16
valid_sources[0x24]	9928	1			T1	114		T2	17		T6	13
valid_sources[0x25]	7259	1			T1	13		T2	6		T6	9
valid_sources[0x26]	7237	1			T1	43		T2	6		T6	23
valid_sources[0x27]	7614	1			T1	23		T2	9		T6	10
valid_sources[0x28]	8596	1			T1	63		T2	9		T6	16
valid_sources[0x29]	7087	1			T1	46		T2	11		T6	23
valid_sources[0x2a]	10091	1			T1	51		T2	8		T6	21
valid_sources[0x2b]	7065	1			T1	17		T2	9		T6	22
valid_sources[0x2c]	7261	1			T1	40		T2	4		T6	19
valid_sources[0x2d]	11478	1			T1	30		T2	3		T6	17
valid_sources[0x2e]	7584	1			T1	41		T2	19		T6	17
valid_sources[0x2f]	17269	1			T1	13		T2	21		T6	14
valid_sources[0x30]	11818	1			T1	41		T2	8		T6	22
valid_sources[0x31]	7471	1			T1	20		T2	8		T6	17
valid_sources[0x32]	7516	1			T1	24		T2	21		T6	19
valid_sources[0x33]	7450	1			T1	11		T2	6		T6	21
valid_sources[0x34]	6995	1			T1	22		T2	8		T6	17
valid_sources[0x35]	8293	1			T1	36		T2	6		T6	14
valid_sources[0x36]	11165	1			T1	19		T2	18		T6	19
valid_sources[0x37]	8572	1			T1	26		T2	15		T6	12
valid_sources[0x38]	7480	1			T1	27		T2	7		T6	16
valid_sources[0x39]	7130	1			T1	21		T2	4		T6	13
valid_sources[0x3a]	8102	1			T1	11		T2	6		T6	11
valid_sources[0x3b]	11228	1			T1	12		T2	11		T6	14
valid_sources[0x3c]	15493	1			T1	20		T2	17		T6	10
valid_sources[0x3d]	7661	1			T1	10		T2	27		T6	21
valid_sources[0x3e]	7666	1			T1	21		T2	5		T6	14
valid_sources[0x3f]	9960	1			T1	37		T2	5		T6	17
valid_sources[0x40]	7310	1			T1	20		T2	15		T6	18
valid_sources[0x41]	7189	1			T1	14		T2	8		T6	21
valid_sources[0x42]	7062	1			T1	25		T2	10		T6	21
valid_sources[0x43]	6895	1			T1	41		T2	20		T6	13
valid_sources[0x44]	7472	1			T1	54		T2	5		T6	15
valid_sources[0x45]	7181	1			T1	22		T2	13		T6	12
valid_sources[0x46]	20072	1			T1	43		T2	6		T6	22
valid_sources[0x47]	7746	1			T1	28		T2	6		T6	28
valid_sources[0x48]	11470	1			T1	32		T2	5		T6	18
valid_sources[0x49]	24297	1			T1	27		T2	5		T6	10
valid_sources[0x4a]	13828	1			T1	35		T2	27		T6	11
valid_sources[0x4b]	7555	1			T1	48		T2	7		T6	14
valid_sources[0x4c]	8001	1			T1	28		T2	7		T6	16
valid_sources[0x4d]	10781	1			T1	22		T2	7		T6	18
valid_sources[0x4e]	7161	1			T1	19		T2	4		T6	24
valid_sources[0x4f]	11547	1			T1	11		T2	8		T6	11
valid_sources[0x50]	8584	1			T1	53		T2	9		T6	12
valid_sources[0x51]	20836	1			T1	18		T2	8		T6	20
valid_sources[0x52]	12571	1			T1	18		T2	7		T6	16
valid_sources[0x53]	7187	1			T1	57		T2	15		T6	18
valid_sources[0x54]	15668	1			T1	21		T2	28		T6	18
valid_sources[0x55]	7204	1			T1	51		T2	7		T6	10
valid_sources[0x56]	8985	1			T1	24		T2	14		T6	24
valid_sources[0x57]	15338	1			T1	35		T2	6		T6	15
valid_sources[0x58]	7430	1			T1	22		T2	6		T6	19
valid_sources[0x59]	7244	1			T1	31		T2	7		T6	13
valid_sources[0x5a]	8328	1			T1	70		T2	17		T6	15
valid_sources[0x5b]	9946	1			T1	39		T2	13		T6	18
valid_sources[0x5c]	8889	1			T1	11		T2	7		T6	14
valid_sources[0x5d]	12928	1			T1	45		T2	16		T6	13
valid_sources[0x5e]	7091	1			T1	19		T2	5		T6	16
valid_sources[0x5f]	7377	1			T1	44		T2	8		T6	17
valid_sources[0x60]	7292	1			T1	34		T2	38		T6	21
valid_sources[0x61]	7080	1			T1	23		T2	10		T6	13
valid_sources[0x62]	6870	1			T1	17		T2	12		T6	15
valid_sources[0x63]	14964	1			T1	29		T2	12		T6	18
valid_sources[0x64]	15872	1			T1	27		T2	38		T6	19
valid_sources[0x65]	6911	1			T1	12		T2	5		T6	13
valid_sources[0x66]	7422	1			T1	24		T2	17		T6	16
valid_sources[0x67]	8110	1			T1	33		T2	8		T6	13
valid_sources[0x68]	6961	1			T1	16		T2	3		T6	19
valid_sources[0x69]	8447	1			T1	41		T2	10		T6	10
valid_sources[0x6a]	7943	1			T1	48		T2	6		T6	15
valid_sources[0x6b]	11179	1			T1	24		T2	15		T6	11
valid_sources[0x6c]	7609	1			T1	17		T2	12		T6	17
valid_sources[0x6d]	15652	1			T1	30		T2	8		T6	23
valid_sources[0x6e]	11566	1			T1	14		T2	7		T6	14
valid_sources[0x6f]	12723	1			T1	35		T2	9		T4	2
valid_sources[0x70]	7033	1			T1	36		T2	8		T6	14
valid_sources[0x71]	7162	1			T1	39		T2	23		T6	17
valid_sources[0x72]	8080	1			T1	36		T2	10		T6	12
valid_sources[0x73]	8233	1			T1	10		T2	5		T6	17
valid_sources[0x74]	15918	1			T1	14		T2	47		T6	16
valid_sources[0x75]	11989	1			T1	30		T2	8		T6	19
valid_sources[0x76]	9974	1			T1	17		T2	7		T6	17
valid_sources[0x77]	12625	1			T1	16		T2	14		T6	14
valid_sources[0x78]	7031	1			T1	35		T2	8		T6	15
valid_sources[0x79]	7826	1			T1	34		T2	7		T6	21
valid_sources[0x7a]	7399	1			T1	35		T2	17		T6	15
valid_sources[0x7b]	10026	1			T1	18		T2	14		T6	11
valid_sources[0x7c]	6989	1			T1	16		T2	26		T6	14
valid_sources[0x7d]	16144	1			T1	25		T2	8		T6	19
valid_sources[0x7e]	8311	1			T1	32		T2	7		T6	19
valid_sources[0x7f]	7261	1			T1	43		T2	6		T6	9
valid_sources[0x80]	10228	1			T1	40		T2	4		T6	19

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1063942

1

T1

4018

T2

1312

T4

1

values[0x0]

all_enables

biggest_size

82039

1

T1

112

T2

87

T4

1

values[0x1]

all_enables

biggest_size

59935

1

T1

85

T2

65

T13

1