Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
88.89	88.89	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	88.89	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.89	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	5	40	88.89

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	4	12	75.00	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	29907	1			T1	18		T2	20		T3	189
auto[PWRUP]	102	1			T3	2		T7	1		T65	2
auto[ONEST_0]	83	1			T3	2		T7	3		T66	2
auto[ONEST_021]	17	1			T49	1		T66	1		T67	1
auto[ONEST_1]	77	1			T65	1		T49	3		T51	1
auto[ONEST_DONE]	4	1			T193	1		T194	1		T195	1
auto[LP_0]	122	1			T3	2		T7	4		T65	2
auto[LP_021]	26	1			T65	1		T101	1		T196	2
auto[LP_1]	128	1			T3	1		T48	1		T65	3
auto[LP_EVAL]	75	1			T7	2		T65	1		T49	1
auto[LP_SLP]	476	1			T3	5		T7	5		T48	3
auto[LP_PWRUP]	22	1			T65	2		T101	1		T144	1
auto[NP_0]	139	1			T3	1		T7	3		T48	1
auto[NP_021]	47	1			T7	1		T66	2		T100	1
auto[NP_1]	140	1			T3	1		T7	1		T65	1
auto[NP_EVAL]	38	1			T49	1		T144	1		T67	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

3

1

T28

1

T197

1

T198

1

min

29317

1

T1

18

T2

20

T3

183

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	29328	1			T1	18		T2	20		T3	183
pow[0x1]	9	1			T100	1		T67	1		T199	1
pow[0x2]	19	1			T7	1		T65	1		T49	1
pow[0x3]	35	1			T3	2		T101	2		T28	1
pow[0x4]	54	1			T49	1		T66	1		T67	2
pow[0x5]	127	1			T3	1		T7	2		T65	2
pow[0x6]	281	1			T3	2		T7	9		T65	5
pow[0x7]	549	1			T3	8		T7	6		T48	6

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

169

1

T7

6

T48

1

T65

4

min

28876

1

T1

18

T2

20

T3

177

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	4	12	75.00

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x2]	0	1	1
pow[0x3]	0	1	1
pow[0x4]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	28876	1			T1	18		T2	20		T3	177
pow[0x5]	2	1			T200	1		T201	1		-	-
pow[0x6]	2	1			T199	1		T202	1		-	-
pow[0x7]	1	1			T51	1		-	-		-	-
pow[0x8]	4	1			T203	1		T204	1		T205	1
pow[0x9]	7	1			T66	1		T144	1		T67	1
pow[0xa]	14	1			T48	1		T49	1		T67	1
pow[0xb]	35	1			T3	1		T65	2		T66	1
pow[0xc]	57	1			T7	1		T65	1		T49	1
pow[0xd]	153	1			T3	3		T7	1		T65	1
pow[0xe]	324	1			T3	3		T7	3		T48	1
pow[0xf]	597	1			T3	7		T7	8		T48	3