Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
93.33	93.33	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	93.33	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.33	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	3	42	93.33

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	2	14	87.50	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2323	1			T4	20		T3	14		T7	11
auto[PWRUP]	109	1			T3	1		T7	1		T49	1
auto[ONEST_0]	79	1			T3	1		T7	2		T48	1
auto[ONEST_021]	23	1			T7	1		T66	1		T51	1
auto[ONEST_1]	86	1			T3	2		T7	1		T100	2
auto[ONEST_DONE]	1	1			T326	1		-	-		-	-
auto[LP_0]	152	1			T3	1		T7	4		T65	2
auto[LP_021]	32	1			T7	1		T66	1		T101	1
auto[LP_1]	115	1			T3	2		T48	2		T65	2
auto[LP_EVAL]	68	1			T49	1		T101	1		T67	3
auto[LP_SLP]	546	1			T3	9		T7	12		T48	3
auto[LP_PWRUP]	26	1			T3	1		T50	1		T100	1
auto[NP_0]	215	1			T3	1		T7	3		T48	2
auto[NP_021]	58	1			T3	1		T48	1		T49	2
auto[NP_1]	237	1			T3	3		T7	1		T48	2
auto[NP_EVAL]	38	1			T48	1		T66	1		T50	2

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

9

1

T100

1

T327

1

T328

1

min

2058

1

T4

20

T3

12

T7

13

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	2067	1			T4	20		T3	12		T7	13
pow[0x1]	10	1			T50	1		T35	1		T280	1
pow[0x2]	14	1			T50	1		T101	1		T327	1
pow[0x3]	42	1			T3	1		T7	1		T49	1
pow[0x4]	73	1			T3	2		T7	1		T49	2
pow[0x5]	120	1			T3	5		T7	1		T66	1
pow[0x6]	256	1			T3	4		T7	1		T65	2
pow[0x7]	539	1			T3	5		T7	8		T48	2

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

201

1

T7

4

T65

1

T49

4

min

1420

1

T4

20

T3

4

T7

3

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	2	14	87.50

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x5]	0	1	1
pow[0x6]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1425	1			T4	20		T3	4		T7	3
pow[0x1]	15	1			T51	1		T52	2		T14	1
pow[0x2]	20	1			T49	3		T107	1		T204	1
pow[0x3]	53	1			T51	2		T107	3		T111	1
pow[0x4]	75	1			T48	1		T49	2		T50	6
pow[0x7]	1	1			T329	1		-	-		-	-
pow[0x8]	2	1			T233	1		T159	1		-	-
pow[0x9]	9	1			T144	1		T159	1		T280	1
pow[0xa]	18	1			T101	1		T196	1		T254	1
pow[0xb]	39	1			T3	1		T7	1		T66	1
pow[0xc]	72	1			T3	3		T7	1		T66	1
pow[0xd]	138	1			T3	2		T7	1		T48	1
pow[0xe]	294	1			T3	6		T7	3		T48	2
pow[0xf]	568	1			T3	8		T7	6		T48	2