Unified Coverage Report :: Module :: adc_ctrl_core

Module : adc_ctrl_core

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_adc_ctrl_core	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_adc_ctrl_core

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.83	100.00	99.76		100.00	99.37	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_adc_ctrl_fsm	99.75	100.00	100.00		100.00	98.73	100.00
u_adc_ctrl_intr	99.00	100.00	96.00			100.00	100.00
u_oneshot_done_sync	100.00	100.00	100.00			100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : adc_ctrl_core

	Line No.	Total	Covered	Percent
TOTAL		63	63	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	63	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
CONT_ASSIGN	73	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	83	1	1	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	117	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	137	1	1	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	141	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	213	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv' or '../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	8	8
63	8	8
72	1	1
73	1	1
74	1	1
75	1	1
83	1	1
86	1	1
87	1	1
88	1	1
89	1	1
104	8	8
107	8	8
117	8	8
121	8	8
137	1	1
138	1	1
140	1	1
141	1	1
145	1	1
213	1	1

---

Cond Coverage for Module : adc_ctrl_core

	Total	Covered	Percent
Conditions	293	293	100.00
Logical	293	293	100.00
Non-Logical	0	0
Event	0	0

 LINE       83
 EXPRESSION (reg2hw_i.adc_en_ctl.oneshot_mode.q ? oneshot_done : (reg2hw_i.adc_en_ctl.adc_enable.q ? ((|match_pulse)) : '0))
             -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T3,T7,T48

 LINE       83
 SUB-EXPRESSION (reg2hw_i.adc_en_ctl.adc_enable.q ? ((|match_pulse)) : '0)
                 ----------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][0].cond)) ? ((aon_filter_ctl[0][0].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][0].max_v)) : ((aon_filter_ctl[0][0].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][0].max_v)))

-1-	Status	Tests
0	Covered	T6,T12,T48
1	Covered	T1,T2,T4

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][0].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][0].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][0].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][0].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T12,T59
0	1	Covered	T6,T12,T59
1	0	Covered	T6,T12,T48

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][1].cond)) ? ((aon_filter_ctl[0][1].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][1].max_v)) : ((aon_filter_ctl[0][1].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][1].max_v)))

-1-	Status	Tests
0	Covered	T1,T2,T8
1	Covered	T1,T2,T4

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][1].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][1].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][1].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][1].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T8
0	1	Covered	T1,T2,T8
1	0	Covered	T1,T8,T12

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][2].cond)) ? ((aon_filter_ctl[0][2].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][2].max_v)) : ((aon_filter_ctl[0][2].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][2].max_v)))

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T1,T2,T4

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][2].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][2].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T2,T3,T5
1	1	Covered	T1,T2,T4

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][2].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][2].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T6
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T6

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][3].cond)) ? ((aon_filter_ctl[0][3].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][3].max_v)) : ((aon_filter_ctl[0][3].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][3].max_v)))

-1-	Status	Tests
0	Covered	T1,T2,T12
1	Covered	T1,T2,T4

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][3].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][3].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][3].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][3].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T12
0	1	Covered	T1,T2,T12
1	0	Covered	T1,T2,T12

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][4].cond)) ? ((aon_filter_ctl[0][4].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][4].max_v)) : ((aon_filter_ctl[0][4].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][4].max_v)))

-1-	Status	Tests
0	Covered	T2,T12,T48
1	Covered	T1,T2,T4

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][4].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][4].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][4].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][4].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T12,T48
0	1	Covered	T2,T12,T59
1	0	Covered	T2,T12,T48

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][5].cond)) ? ((aon_filter_ctl[0][5].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][5].max_v)) : ((aon_filter_ctl[0][5].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][5].max_v)))

-1-	Status	Tests
0	Covered	T1,T2,T8
1	Covered	T1,T2,T4

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][5].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][5].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][5].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][5].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T8
0	1	Covered	T1,T2,T12
1	0	Covered	T1,T2,T8

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][6].cond)) ? ((aon_filter_ctl[0][6].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][6].max_v)) : ((aon_filter_ctl[0][6].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][6].max_v)))

-1-	Status	Tests
0	Covered	T1,T2,T8
1	Covered	T1,T2,T4

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][6].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][6].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][6].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][6].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T8
0	1	Covered	T1,T2,T8
1	0	Covered	T1,T2,T8

 LINE       104
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[0][7].cond)) ? ((aon_filter_ctl[0][7].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][7].max_v)) : ((aon_filter_ctl[0][7].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][7].max_v)))

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T1,T2,T4

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][7].min_v <= chn0_val) && (chn0_val <= aon_filter_ctl[0][7].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       104
 SUB-EXPRESSION ((aon_filter_ctl[0][7].min_v > chn0_val) || (chn0_val > aon_filter_ctl[0][7].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T5
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T5

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][0].cond)) ? ((aon_filter_ctl[1][0].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][0].max_v)) : ((aon_filter_ctl[1][0].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][0].max_v)))

-1-	Status	Tests
0	Covered	T6,T12,T56
1	Covered	T1,T2,T4

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][0].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][0].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][0].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][0].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T12,T56
0	1	Covered	T6,T12,T56
1	0	Covered	T6,T12,T56

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][1].cond)) ? ((aon_filter_ctl[1][1].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][1].max_v)) : ((aon_filter_ctl[1][1].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][1].max_v)))

-1-	Status	Tests
0	Covered	T2,T8,T12
1	Covered	T1,T2,T4

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][1].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][1].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][1].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][1].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T8,T12
0	1	Covered	T2,T8,T12
1	0	Covered	T2,T8,T12

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][2].cond)) ? ((aon_filter_ctl[1][2].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][2].max_v)) : ((aon_filter_ctl[1][2].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][2].max_v)))

-1-	Status	Tests
0	Covered	T1,T2,T6
1	Covered	T1,T2,T4

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][2].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][2].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][2].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][2].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T6
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T6

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][3].cond)) ? ((aon_filter_ctl[1][3].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][3].max_v)) : ((aon_filter_ctl[1][3].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][3].max_v)))

-1-	Status	Tests
0	Covered	T1,T2,T12
1	Covered	T1,T2,T4

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][3].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][3].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][3].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][3].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T12
0	1	Covered	T1,T2,T12
1	0	Covered	T1,T2,T12

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][4].cond)) ? ((aon_filter_ctl[1][4].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][4].max_v)) : ((aon_filter_ctl[1][4].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][4].max_v)))

-1-	Status	Tests
0	Covered	T2,T12,T48
1	Covered	T1,T2,T4

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][4].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][4].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][4].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][4].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T12,T48
0	1	Covered	T2,T12,T59
1	0	Covered	T2,T12,T48

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][5].cond)) ? ((aon_filter_ctl[1][5].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][5].max_v)) : ((aon_filter_ctl[1][5].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][5].max_v)))

-1-	Status	Tests
0	Covered	T1,T2,T8
1	Covered	T1,T2,T4

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][5].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][5].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][5].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][5].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T8
0	1	Covered	T1,T2,T8
1	0	Covered	T1,T2,T8

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][6].cond)) ? ((aon_filter_ctl[1][6].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][6].max_v)) : ((aon_filter_ctl[1][6].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][6].max_v)))

-1-	Status	Tests
0	Covered	T1,T2,T8
1	Covered	T1,T2,T4

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][6].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][6].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][6].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][6].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T8
0	1	Covered	T1,T2,T8
1	0	Covered	T1,T2,T8

 LINE       107
 EXPRESSION 
 Number  Term
      1  ((!aon_filter_ctl[1][7].cond)) ? ((aon_filter_ctl[1][7].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][7].max_v)) : ((aon_filter_ctl[1][7].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][7].max_v)))

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T1,T2,T4

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][7].min_v <= chn1_val) && (chn1_val <= aon_filter_ctl[1][7].max_v))
                 --------------------1-------------------    --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       107
 SUB-EXPRESSION ((aon_filter_ctl[1][7].min_v > chn1_val) || (chn1_val > aon_filter_ctl[1][7].max_v))
                 -------------------1-------------------    -------------------2-------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T5
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T5

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][0].en, aon_filter_ctl[1][0].en})) & 
      2  (((!aon_filter_ctl[0][0].en)) | (chn0_match[0] & aon_filter_ctl[0][0].en)) & 
      3  (((!aon_filter_ctl[1][0].en)) | (chn1_match[0] & aon_filter_ctl[1][0].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T4
1	0	1	Covered	T1,T2,T5
1	1	0	Covered	T1,T2,T5
1	1	1	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][0].en)) | (chn0_match[0] & aon_filter_ctl[0][0].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T5
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4

 LINE       117
 SUB-EXPRESSION (chn0_match[0] & aon_filter_ctl[0][0].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][0].en)) | (chn1_match[0] & aon_filter_ctl[1][0].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T5
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4

 LINE       117
 SUB-EXPRESSION (chn1_match[0] & aon_filter_ctl[1][0].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][1].en, aon_filter_ctl[1][1].en})) & 
      2  (((!aon_filter_ctl[0][1].en)) | (chn0_match[1] & aon_filter_ctl[0][1].en)) & 
      3  (((!aon_filter_ctl[1][1].en)) | (chn1_match[1] & aon_filter_ctl[1][1].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T4
1	0	1	Covered	T1,T2,T5
1	1	0	Covered	T2,T5,T9
1	1	1	Covered	T1,T2,T5

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][1].en)) | (chn0_match[1] & aon_filter_ctl[0][1].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T5
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T4

 LINE       117
 SUB-EXPRESSION (chn0_match[1] & aon_filter_ctl[0][1].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T5

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][1].en)) | (chn1_match[1] & aon_filter_ctl[1][1].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T5,T9
0	1	Covered	T2,T5,T9
1	0	Covered	T1,T2,T4

 LINE       117
 SUB-EXPRESSION (chn1_match[1] & aon_filter_ctl[1][1].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T9
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T5,T9

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][2].en, aon_filter_ctl[1][2].en})) & 
      2  (((!aon_filter_ctl[0][2].en)) | (chn0_match[2] & aon_filter_ctl[0][2].en)) & 
      3  (((!aon_filter_ctl[1][2].en)) | (chn1_match[2] & aon_filter_ctl[1][2].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T4
1	0	1	Covered	T1,T2,T5
1	1	0	Covered	T1,T2,T5
1	1	1	Covered	T1,T2,T5

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][2].en)) | (chn0_match[2] & aon_filter_ctl[0][2].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T5
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T4

 LINE       117
 SUB-EXPRESSION (chn0_match[2] & aon_filter_ctl[0][2].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T5

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][2].en)) | (chn1_match[2] & aon_filter_ctl[1][2].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T5
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T4

 LINE       117
 SUB-EXPRESSION (chn1_match[2] & aon_filter_ctl[1][2].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T5

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][3].en, aon_filter_ctl[1][3].en})) & 
      2  (((!aon_filter_ctl[0][3].en)) | (chn0_match[3] & aon_filter_ctl[0][3].en)) & 
      3  (((!aon_filter_ctl[1][3].en)) | (chn1_match[3] & aon_filter_ctl[1][3].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T4
1	0	1	Covered	T1,T2,T5
1	1	0	Covered	T1,T2,T5
1	1	1	Covered	T1,T2,T5

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][3].en)) | (chn0_match[3] & aon_filter_ctl[0][3].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T5
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T4

 LINE       117
 SUB-EXPRESSION (chn0_match[3] & aon_filter_ctl[0][3].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T5

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][3].en)) | (chn1_match[3] & aon_filter_ctl[1][3].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T5
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T4

 LINE       117
 SUB-EXPRESSION (chn1_match[3] & aon_filter_ctl[1][3].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T5

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][4].en, aon_filter_ctl[1][4].en})) & 
      2  (((!aon_filter_ctl[0][4].en)) | (chn0_match[4] & aon_filter_ctl[0][4].en)) & 
      3  (((!aon_filter_ctl[1][4].en)) | (chn1_match[4] & aon_filter_ctl[1][4].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T4
1	0	1	Covered	T1,T2,T5
1	1	0	Covered	T1,T2,T5
1	1	1	Covered	T1,T2,T5

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][4].en)) | (chn0_match[4] & aon_filter_ctl[0][4].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T5
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T4

 LINE       117
 SUB-EXPRESSION (chn0_match[4] & aon_filter_ctl[0][4].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T5

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][4].en)) | (chn1_match[4] & aon_filter_ctl[1][4].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T5
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T4

 LINE       117
 SUB-EXPRESSION (chn1_match[4] & aon_filter_ctl[1][4].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T5

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][5].en, aon_filter_ctl[1][5].en})) & 
      2  (((!aon_filter_ctl[0][5].en)) | (chn0_match[5] & aon_filter_ctl[0][5].en)) & 
      3  (((!aon_filter_ctl[1][5].en)) | (chn1_match[5] & aon_filter_ctl[1][5].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T4
1	0	1	Covered	T1,T2,T5
1	1	0	Covered	T1,T2,T5
1	1	1	Covered	T1,T2,T5

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][5].en)) | (chn0_match[5] & aon_filter_ctl[0][5].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T5
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T4

 LINE       117
 SUB-EXPRESSION (chn0_match[5] & aon_filter_ctl[0][5].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T5

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][5].en)) | (chn1_match[5] & aon_filter_ctl[1][5].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T5
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T4

 LINE       117
 SUB-EXPRESSION (chn1_match[5] & aon_filter_ctl[1][5].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T5

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][6].en, aon_filter_ctl[1][6].en})) & 
      2  (((!aon_filter_ctl[0][6].en)) | (chn0_match[6] & aon_filter_ctl[0][6].en)) & 
      3  (((!aon_filter_ctl[1][6].en)) | (chn1_match[6] & aon_filter_ctl[1][6].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T4
1	0	1	Covered	T1,T2,T5
1	1	0	Covered	T1,T2,T5
1	1	1	Covered	T1,T2,T5

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][6].en)) | (chn0_match[6] & aon_filter_ctl[0][6].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T5
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T4

 LINE       117
 SUB-EXPRESSION (chn0_match[6] & aon_filter_ctl[0][6].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T5

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][6].en)) | (chn1_match[6] & aon_filter_ctl[1][6].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T5
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T4

 LINE       117
 SUB-EXPRESSION (chn1_match[6] & aon_filter_ctl[1][6].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T5

 LINE       117
 EXPRESSION 
 Number  Term
      1  ((|{aon_filter_ctl[0][7].en, aon_filter_ctl[1][7].en})) & 
      2  (((!aon_filter_ctl[0][7].en)) | (chn0_match[7] & aon_filter_ctl[0][7].en)) & 
      3  (((!aon_filter_ctl[1][7].en)) | (chn1_match[7] & aon_filter_ctl[1][7].en)))

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T4
1	0	1	Covered	T1,T2,T5
1	1	0	Covered	T1,T2,T5
1	1	1	Covered	T1,T2,T5

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[0][7].en)) | (chn0_match[7] & aon_filter_ctl[0][7].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T5
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T4

 LINE       117
 SUB-EXPRESSION (chn0_match[7] & aon_filter_ctl[0][7].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T5

 LINE       117
 SUB-EXPRESSION (((!aon_filter_ctl[1][7].en)) | (chn1_match[7] & aon_filter_ctl[1][7].en))
                 --------------1-------------   --------------------2--------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T5
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T4

 LINE       117
 SUB-EXPRESSION (chn1_match[7] & aon_filter_ctl[1][7].en)
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T5

 LINE       121
 EXPRESSION (adc_ctrl_done && match[0])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T5

 LINE       121
 EXPRESSION (adc_ctrl_done && match[1])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T5

 LINE       121
 EXPRESSION (adc_ctrl_done && match[2])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T5

 LINE       121
 EXPRESSION (adc_ctrl_done && match[3])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T5

 LINE       121
 EXPRESSION (adc_ctrl_done && match[4])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T5

 LINE       121
 EXPRESSION (adc_ctrl_done && match[5])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T5

 LINE       121
 EXPRESSION (adc_ctrl_done && match[6])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T5

 LINE       121
 EXPRESSION (adc_ctrl_done && match[7])
             ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T5

 LINE       140
 EXPRESSION (aon_fsm_trans | reg2hw_i.filter_status.trans.q)
             ------1------   ---------------2--------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T1,T12,T56
1	0	Covered	T1,T12,T56

 LINE       145
 EXPRESSION (((|(reg2hw_i.filter_status.match.q & reg2hw_i.adc_wakeup_ctl.match_en.q))) || (reg2hw_i.filter_status.trans.q & reg2hw_i.adc_wakeup_ctl.trans_en.q))
             -------------------------------------1------------------------------------    ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T1,T56,T63
1	0	Covered	T1,T6,T12

 LINE       145
 SUB-EXPRESSION (reg2hw_i.filter_status.trans.q & reg2hw_i.adc_wakeup_ctl.trans_en.q)
                 ---------------1--------------   -----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T12,T56
1	0	Covered	T12,T56,T59
1	1	Covered	T1,T56,T63

---

Branch Coverage for Module : adc_ctrl_core

	Line No.	Total	Covered	Percent
Branches		35	35	100.00
TERNARY	83	3	3	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00
TERNARY	104	2	2	100.00
TERNARY	107	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv' or '../src/lowrisc_ip_adc_ctrl_1.0/rtl/adc_ctrl_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	83	(reg2hw_i.adc_en_ctl.oneshot_mode.q) ? 
-2-:	83	(reg2hw_i.adc_en_ctl.adc_enable.q) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T7,T48
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][0].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T6,T12,T48

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][0].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T6,T12,T56

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][1].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T8

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][1].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T2,T8,T12

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][2].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][2].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T6

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][3].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T12

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][3].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T12

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][4].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T2,T12,T48

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][4].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T2,T12,T48

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][5].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T8

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][5].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T8

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][6].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T8

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][6].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T8

	LineNo.	Expression
-1-:	104	((!aon_filter_ctl[0][7].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	107	((!aon_filter_ctl[1][7].cond)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T5

---

Assert Coverage for Module : adc_ctrl_core

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	33	33	100.00	33	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	33	33	100.00	33	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
MaxFilters_A	35371625	35062907	0	0
gen_filter_match[0].MatchCheck00_A	35371625	10331240	0	0
gen_filter_match[0].MatchCheck01_A	35371625	2402956	0	0
gen_filter_match[0].MatchCheck10_A	35371625	2926049	0	0
gen_filter_match[0].MatchCheck11_A	35371625	19402662	0	0
gen_filter_match[1].MatchCheck00_A	35371625	12772013	0	0
gen_filter_match[1].MatchCheck01_A	35371625	1248545	0	0
gen_filter_match[1].MatchCheck10_A	35371625	1376932	0	0
gen_filter_match[1].MatchCheck11_A	35371625	19665417	0	0
gen_filter_match[2].MatchCheck00_A	35371625	12603441	0	0
gen_filter_match[2].MatchCheck01_A	35371625	839774	0	0
gen_filter_match[2].MatchCheck10_A	35371625	502512	0	0
gen_filter_match[2].MatchCheck11_A	35371625	21117180	0	0
gen_filter_match[3].MatchCheck00_A	35371625	13011026	0	0
gen_filter_match[3].MatchCheck01_A	35371625	378041	0	0
gen_filter_match[3].MatchCheck10_A	35371625	404425	0	0
gen_filter_match[3].MatchCheck11_A	35371625	21269415	0	0
gen_filter_match[4].MatchCheck00_A	35371625	13220570	0	0
gen_filter_match[4].MatchCheck01_A	35371625	16	0	0
gen_filter_match[4].MatchCheck10_A	35371625	100	0	0
gen_filter_match[4].MatchCheck11_A	35371625	21842221	0	0
gen_filter_match[5].MatchCheck00_A	35371625	13987322	0	0
gen_filter_match[5].MatchCheck01_A	35371625	12	0	0
gen_filter_match[5].MatchCheck10_A	35371625	36688	0	0
gen_filter_match[5].MatchCheck11_A	35371625	21038885	0	0
gen_filter_match[6].MatchCheck00_A	35371625	13926476	0	0
gen_filter_match[6].MatchCheck01_A	35371625	34040	0	0
gen_filter_match[6].MatchCheck10_A	35371625	32082	0	0
gen_filter_match[6].MatchCheck11_A	35371625	21070309	0	0
gen_filter_match[7].MatchCheck00_A	35371625	13616668	0	0
gen_filter_match[7].MatchCheck01_A	35371625	74477	0	0
gen_filter_match[7].MatchCheck10_A	35371625	182488	0	0
gen_filter_match[7].MatchCheck11_A	35371625	21189274	0	0

MaxFilters_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35371625	35062907	0	0
T1	68403	68305	0	0
T2	101891	101820	0	0
T3	18349	15544	0	0
T4	1781	21	0	0
T5	32663	32591	0	0
T6	32061	31964	0	0
T7	21034	18300	0	0
T8	33097	33006	0	0
T9	98638	98550	0	0
T13	100	5	0	0

gen_filter_match[0].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35371625	10331240	0	0
T1	68403	32518	0	0
T2	101891	67982	0	0
T3	18349	15047	0	0
T4	1781	21	0	0
T5	32663	4	0	0
T6	32061	3	0	0
T7	21034	16862	0	0
T8	33097	4	0	0
T9	98638	3	0	0
T13	100	5	0	0

gen_filter_match[0].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35371625	2402956	0	0
T48	21159	900	0	0
T55	100	0	0	0
T56	74336	0	0	0
T57	1223	0	0	0
T58	32811	0	0	0
T59	34713	0	0	0
T60	32353	0	0	0
T61	90	0	0	0
T62	840	0	0	0
T63	120710	0	0	0
T72	0	32309	0	0
T99	0	34204	0	0
T135	0	32346	0	0
T139	0	3	0	0
T140	0	31604	0	0
T141	0	32039	0	0
T142	0	35320	0	0
T143	0	31872	0	0
T144	0	33892	0	0

gen_filter_match[0].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35371625	2926049	0	0
T5	32663	1	0	0
T6	32061	0	0	0
T7	21034	0	0	0
T8	33097	0	0	0
T9	98638	0	0	0
T10	97063	0	0	0
T11	66372	0	0	0
T12	106717	0	0	0
T48	21159	0	0	0
T55	100	0	0	0
T56	0	33601	0	0
T139	0	3	0	0
T145	0	1	0	0
T146	0	1	0	0
T147	0	33206	0	0
T148	0	1	0	0
T149	0	33056	0	0
T150	0	2	0	0
T151	0	32037	0	0

gen_filter_match[0].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35371625	19402662	0	0
T1	68403	35787	0	0
T2	101891	33838	0	0
T3	18349	497	0	0
T4	1781	0	0	0
T5	32663	32586	0	0
T6	32061	31961	0	0
T7	21034	1438	0	0
T8	33097	33002	0	0
T9	98638	98547	0	0
T10	0	96972	0	0
T11	0	66289	0	0
T13	100	0	0	0

gen_filter_match[1].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35371625	12772013	0	0
T1	68403	35790	0	0
T2	101891	34433	0	0
T3	18349	15544	0	0
T4	1781	21	0	0
T5	32663	4	0	0
T6	32061	31964	0	0
T7	21034	18300	0	0
T8	33097	33006	0	0
T9	98638	3	0	0
T13	100	5	0	0

gen_filter_match[1].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35371625	1248545	0	0
T2	101891	33838	0	0
T3	18349	0	0	0
T4	1781	0	0	0
T5	32663	0	0	0
T6	32061	0	0	0
T7	21034	0	0	0
T8	33097	0	0	0
T9	98638	0	0	0
T10	97063	0	0	0
T13	100	0	0	0
T47	0	33317	0	0
T52	0	3329	0	0
T72	0	37511	0	0
T135	0	35188	0	0
T139	0	3	0	0
T152	0	35757	0	0
T153	0	32375	0	0
T154	0	34750	0	0
T155	0	40526	0	0

gen_filter_match[1].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35371625	1376932	0	0
T1	68403	32515	0	0
T2	101891	0	0	0
T3	18349	0	0	0
T4	1781	0	0	0
T5	32663	1	0	0
T6	32061	0	0	0
T7	21034	0	0	0
T8	33097	0	0	0
T9	98638	0	0	0
T13	100	0	0	0
T139	0	3	0	0
T145	0	1	0	0
T146	0	1	0	0
T147	0	31896	0	0
T148	0	1	0	0
T150	0	2	0	0
T156	0	32656	0	0
T157	0	31991	0	0

gen_filter_match[1].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35371625	19665417	0	0
T2	101891	33549	0	0
T3	18349	0	0	0
T4	1781	0	0	0
T5	32663	32586	0	0
T6	32061	0	0	0
T7	21034	0	0	0
T8	33097	0	0	0
T9	98638	98547	0	0
T10	97063	96972	0	0
T11	0	66289	0	0
T12	0	71491	0	0
T13	100	0	0	0
T56	0	40652	0	0
T58	0	32729	0	0
T59	0	34611	0	0
T63	0	120606	0	0

gen_filter_match[2].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35371625	12603441	0	0
T1	68403	3	0	0
T2	101891	67391	0	0
T3	18349	15544	0	0
T4	1781	21	0	0
T5	32663	4	0	0
T6	32061	31964	0	0
T7	21034	18300	0	0
T8	33097	33006	0	0
T9	98638	3	0	0
T13	100	5	0	0

gen_filter_match[2].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35371625	839774	0	0
T12	106717	35127	0	0
T15	0	4927	0	0
T48	21159	0	0	0
T51	0	40337	0	0
T55	100	0	0	0
T56	74336	0	0	0
T57	1223	0	0	0
T58	32811	0	0	0
T59	34713	0	0	0
T60	32353	0	0	0
T61	90	0	0	0
T62	840	0	0	0
T72	0	33020	0	0
T139	0	3	0	0
T152	0	36226	0	0
T158	0	32666	0	0
T159	0	32301	0	0
T160	0	1	0	0
T161	0	1	0	0

gen_filter_match[2].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35371625	502512	0	0
T5	32663	1	0	0
T6	32061	0	0	0
T7	21034	0	0	0
T8	33097	0	0	0
T9	98638	0	0	0
T10	97063	0	0	0
T11	66372	0	0	0
T12	106717	0	0	0
T48	21159	0	0	0
T53	0	9573	0	0
T55	100	0	0	0
T134	0	31846	0	0
T139	0	3	0	0
T143	0	1	0	0
T145	0	1	0	0
T146	0	1	0	0
T148	0	1	0	0
T149	0	33091	0	0
T162	0	1	0	0

gen_filter_match[2].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35371625	21117180	0	0
T1	68403	68302	0	0
T2	101891	34429	0	0
T3	18349	0	0	0
T4	1781	0	0	0
T5	32663	32586	0	0
T6	32061	0	0	0
T7	21034	0	0	0
T8	33097	0	0	0
T9	98638	98547	0	0
T10	0	96972	0	0
T11	0	66289	0	0
T12	0	71491	0	0
T13	100	0	0	0
T48	0	900	0	0
T56	0	33601	0	0
T58	0	32729	0	0

gen_filter_match[3].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35371625	13011026	0	0
T1	68403	32518	0	0
T2	101891	33842	0	0
T3	18349	15544	0	0
T4	1781	21	0	0
T5	32663	4	0	0
T6	32061	3	0	0
T7	21034	18300	0	0
T8	33097	33006	0	0
T9	98638	3	0	0
T13	100	5	0	0

gen_filter_match[3].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35371625	378041	0	0
T51	117721	30508	0	0
T52	4331	0	0	0
T96	57432	0	0	0
T97	565	0	0	0
T98	65149	0	0	0
T99	100179	0	0	0
T100	21078	0	0	0
T101	26626	0	0	0
T102	67	0	0	0
T103	843	0	0	0
T157	0	33498	0	0
T160	0	2	0	0
T161	0	1	0	0
T163	0	32835	0	0
T164	0	33495	0	0
T165	0	33933	0	0
T166	0	39270	0	0
T167	0	22102	0	0
T168	0	1	0	0

gen_filter_match[3].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35371625	404425	0	0
T2	101891	34429	0	0
T3	18349	0	0	0
T4	1781	0	0	0
T5	32663	1	0	0
T6	32061	0	0	0
T7	21034	0	0	0
T8	33097	0	0	0
T9	98638	0	0	0
T10	97063	0	0	0
T13	100	0	0	0
T51	0	12366	0	0
T63	0	1	0	0
T139	0	3	0	0
T141	0	32573	0	0
T145	0	1	0	0
T146	0	1	0	0
T148	0	1	0	0
T156	0	32950	0	0

gen_filter_match[3].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35371625	21269415	0	0
T1	68403	35787	0	0
T2	101891	33549	0	0
T3	18349	0	0	0
T4	1781	0	0	0
T5	32663	32586	0	0
T6	32061	31961	0	0
T7	21034	0	0	0
T8	33097	0	0	0
T9	98638	98547	0	0
T10	0	96972	0	0
T11	0	66289	0	0
T12	0	33708	0	0
T13	100	0	0	0
T48	0	1824	0	0
T56	0	40652	0	0

gen_filter_match[4].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35371625	13220570	0	0
T1	68403	35790	0	0
T2	101891	33842	0	0
T3	18349	15544	0	0
T4	1781	21	0	0
T5	32663	4	0	0
T6	32061	3	0	0
T7	21034	18300	0	0
T8	33097	33006	0	0
T9	98638	3	0	0
T13	100	5	0	0

gen_filter_match[4].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35371625	16	0	0
T24	0	2	0	0
T53	9963	0	0	0
T72	102939	0	0	0
T99	100179	1	0	0
T100	21078	0	0	0
T101	26626	0	0	0
T102	67	0	0	0
T103	843	0	0	0
T109	0	2	0	0
T148	95955	0	0	0
T160	0	1	0	0
T161	0	1	0	0
T169	0	1	0	0
T170	0	1	0	0
T171	0	3	0	0
T172	0	1	0	0
T173	0	2	0	0
T174	121971	0	0	0
T175	80813	0	0	0

gen_filter_match[4].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35371625	100	0	0
T5	32663	1	0	0
T6	32061	0	0	0
T7	21034	0	0	0
T8	33097	0	0	0
T9	98638	0	0	0
T10	97063	0	0	0
T11	66372	0	0	0
T12	106717	0	0	0
T24	0	2	0	0
T48	21159	0	0	0
T55	100	0	0	0
T63	0	1	0	0
T99	0	1	0	0
T139	0	3	0	0
T143	0	1	0	0
T145	0	2	0	0
T146	0	1	0	0
T148	0	1	0	0
T176	0	1	0	0

gen_filter_match[4].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35371625	21842221	0	0
T1	68403	32515	0	0
T2	101891	67978	0	0
T3	18349	0	0	0
T4	1781	0	0	0
T5	32663	32586	0	0
T6	32061	31961	0	0
T7	21034	0	0	0
T8	33097	0	0	0
T9	98638	98547	0	0
T10	0	96972	0	0
T11	0	66289	0	0
T12	0	35127	0	0
T13	100	0	0	0
T48	0	2724	0	0
T56	0	74253	0	0

gen_filter_match[5].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35371625	13987322	0	0
T1	68403	35790	0	0
T2	101891	67391	0	0
T3	18349	15544	0	0
T4	1781	21	0	0
T5	32663	4	0	0
T6	32061	3	0	0
T7	21034	18300	0	0
T8	33097	4	0	0
T9	98638	3	0	0
T13	100	5	0	0

gen_filter_match[5].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35371625	12	0	0
T53	9963	0	0	0
T72	102939	0	0	0
T99	100179	1	0	0
T100	21078	0	0	0
T101	26626	0	0	0
T102	67	0	0	0
T103	843	0	0	0
T143	0	1	0	0
T148	95955	0	0	0
T161	0	1	0	0
T164	0	1	0	0
T168	0	1	0	0
T172	0	1	0	0
T173	0	2	0	0
T174	121971	0	0	0
T175	80813	0	0	0
T177	0	1	0	0
T178	0	1	0	0
T179	0	2	0	0

gen_filter_match[5].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35371625	36688	0	0
T1	68403	1	0	0
T2	101891	0	0	0
T3	18349	0	0	0
T4	1781	0	0	0
T5	32663	1	0	0
T6	32061	0	0	0
T7	21034	0	0	0
T8	33097	0	0	0
T9	98638	0	0	0
T13	100	0	0	0
T63	0	1	0	0
T99	0	2	0	0
T139	0	2	0	0
T143	0	1	0	0
T145	0	2	0	0
T146	0	1	0	0
T148	0	1	0	0
T176	0	1	0	0

gen_filter_match[5].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35371625	21038885	0	0
T1	68403	32514	0	0
T2	101891	34429	0	0
T3	18349	0	0	0
T4	1781	0	0	0
T5	32663	32586	0	0
T6	32061	31961	0	0
T7	21034	0	0	0
T8	33097	33002	0	0
T9	98638	98547	0	0
T10	0	96972	0	0
T11	0	66289	0	0
T12	0	33708	0	0
T13	100	0	0	0
T48	0	2724	0	0

gen_filter_match[6].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35371625	13926476	0	0
T1	68403	32517	0	0
T2	101891	68271	0	0
T3	18349	15544	0	0
T4	1781	21	0	0
T5	32663	4	0	0
T6	32061	31964	0	0
T7	21034	18300	0	0
T8	33097	4	0	0
T9	98638	3	0	0
T13	100	5	0	0

gen_filter_match[6].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35371625	34040	0	0
T1	68403	1	0	0
T2	101891	0	0	0
T3	18349	0	0	0
T4	1781	0	0	0
T5	32663	0	0	0
T6	32061	0	0	0
T7	21034	0	0	0
T8	33097	0	0	0
T9	98638	0	0	0
T13	100	0	0	0
T160	0	1	0	0
T164	0	1	0	0
T168	0	1	0	0
T171	0	3	0	0
T173	0	3	0	0
T180	0	1	0	0
T181	0	1	0	0
T182	0	1	0	0
T183	0	1	0	0

gen_filter_match[6].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35371625	32082	0	0
T5	32663	1	0	0
T6	32061	0	0	0
T7	21034	0	0	0
T8	33097	0	0	0
T9	98638	0	0	0
T10	97063	0	0	0
T11	66372	0	0	0
T12	106717	0	0	0
T48	21159	0	0	0
T55	100	0	0	0
T63	0	1	0	0
T99	0	1	0	0
T139	0	3	0	0
T143	0	1	0	0
T145	0	1	0	0
T146	0	1	0	0
T148	0	1	0	0
T176	0	1	0	0
T184	0	1	0	0

gen_filter_match[6].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35371625	21070309	0	0
T1	68403	35787	0	0
T2	101891	33549	0	0
T3	18349	0	0	0
T4	1781	0	0	0
T5	32663	32586	0	0
T6	32061	0	0	0
T7	21034	0	0	0
T8	33097	33002	0	0
T9	98638	98547	0	0
T10	0	96972	0	0
T11	0	66289	0	0
T12	0	72910	0	0
T13	100	0	0	0
T48	0	900	0	0
T56	0	33601	0	0

gen_filter_match[7].MatchCheck00_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35371625	13616668	0	0
T1	68403	3	0	0
T2	101891	67391	0	0
T3	18349	15544	0	0
T4	1781	21	0	0
T5	32663	4	0	0
T6	32061	31964	0	0
T7	21034	18300	0	0
T8	33097	33006	0	0
T9	98638	3	0	0
T13	100	5	0	0

gen_filter_match[7].MatchCheck01_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35371625	74477	0	0
T43	0	40536	0	0
T109	0	1	0	0
T142	99557	0	0	0
T143	100312	0	0	0
T144	50788	0	0	0
T150	70122	2	0	0
T153	64849	0	0	0
T160	0	1	0	0
T164	0	1	0	0
T170	0	1	0	0
T172	0	1	0	0
T178	0	1	0	0
T185	0	1	0	0
T186	0	1	0	0
T187	66489	0	0	0
T188	1034	0	0	0
T189	5482	0	0	0
T190	1119	0	0	0
T191	82509	0	0	0

gen_filter_match[7].MatchCheck10_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35371625	182488	0	0
T5	32663	1	0	0
T6	32061	0	0	0
T7	21034	0	0	0
T8	33097	0	0	0
T9	98638	0	0	0
T10	97063	0	0	0
T11	66372	0	0	0
T12	106717	0	0	0
T48	21159	0	0	0
T55	100	0	0	0
T63	0	1	0	0
T99	0	1	0	0
T139	0	2	0	0
T145	0	1	0	0
T146	0	1	0	0
T148	0	1	0	0
T150	0	2	0	0
T176	0	1	0	0
T184	0	1	0	0

gen_filter_match[7].MatchCheck11_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35371625	21189274	0	0
T1	68403	68302	0	0
T2	101891	34429	0	0
T3	18349	0	0	0
T4	1781	0	0	0
T5	32663	32586	0	0
T6	32061	0	0	0
T7	21034	0	0	0
T8	33097	0	0	0
T9	98638	98547	0	0
T10	0	96972	0	0
T11	0	66289	0	0
T12	0	68835	0	0
T13	100	0	0	0
T48	0	1824	0	0
T56	0	40652	0	0
T58	0	32729	0	0