Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	96.00						96.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	24	96.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	24	96.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	0	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	2653	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	2525	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	2612	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	2606	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	2670	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	2535	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	2783	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	2699	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	2591	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	2829	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	2747	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	2512	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	2855	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	2497	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	2521	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	2337	0	0
adc_en_ctl_rd_A	2147483647	1920	0	0
adc_fsm_rst_rd_A	2147483647	1660	0	0
adc_intr_ctl_rd_A	2147483647	2552	0	0
adc_lp_sample_ctl_rd_A	2147483647	1636	0	0
adc_pd_ctl_rd_A	2147483647	2241	0	0
adc_sample_ctl_rd_A	2147483647	1521	0	0
adc_wakeup_ctl_rd_A	2147483647	1873	0	0
intr_enable_rd_A	2147483647	2270	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2653	0	0
T14	856929	8	0	0
T15	0	18	0	0
T16	0	29	0	0
T17	0	46	0	0
T18	0	32	0	0
T19	0	39	0	0
T20	0	17	0	0
T21	0	29	0	0
T22	0	40	0	0
T23	0	11	0	0
T24	460774	0	0	0
T25	570588	0	0	0
T26	479181	0	0	0
T27	171577	0	0	0
T28	482917	0	0	0
T29	120230	0	0	0
T30	536379	0	0	0
T31	310978	0	0	0
T32	796906	0	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2525	0	0
T14	856929	6	0	0
T15	0	13	0	0
T16	0	25	0	0
T17	0	40	0	0
T18	0	24	0	0
T19	0	41	0	0
T20	0	22	0	0
T21	0	34	0	0
T22	0	28	0	0
T23	0	19	0	0
T24	460774	0	0	0
T25	570588	0	0	0
T26	479181	0	0	0
T27	171577	0	0	0
T28	482917	0	0	0
T29	120230	0	0	0
T30	536379	0	0	0
T31	310978	0	0	0
T32	796906	0	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2612	0	0
T14	856929	12	0	0
T15	0	7	0	0
T16	0	28	0	0
T17	0	22	0	0
T18	0	23	0	0
T19	0	45	0	0
T20	0	26	0	0
T21	0	20	0	0
T22	0	21	0	0
T23	0	17	0	0
T24	460774	0	0	0
T25	570588	0	0	0
T26	479181	0	0	0
T27	171577	0	0	0
T28	482917	0	0	0
T29	120230	0	0	0
T30	536379	0	0	0
T31	310978	0	0	0
T32	796906	0	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2606	0	0
T14	856929	12	0	0
T15	0	18	0	0
T16	0	15	0	0
T17	0	38	0	0
T18	0	27	0	0
T19	0	39	0	0
T20	0	24	0	0
T21	0	27	0	0
T22	0	42	0	0
T23	0	23	0	0
T24	460774	0	0	0
T25	570588	0	0	0
T26	479181	0	0	0
T27	171577	0	0	0
T28	482917	0	0	0
T29	120230	0	0	0
T30	536379	0	0	0
T31	310978	0	0	0
T32	796906	0	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2670	0	0
T14	856929	10	0	0
T15	0	5	0	0
T16	0	8	0	0
T17	0	31	0	0
T18	0	9	0	0
T19	0	50	0	0
T20	0	15	0	0
T21	0	23	0	0
T22	0	50	0	0
T23	0	22	0	0
T24	460774	0	0	0
T25	570588	0	0	0
T26	479181	0	0	0
T27	171577	0	0	0
T28	482917	0	0	0
T29	120230	0	0	0
T30	536379	0	0	0
T31	310978	0	0	0
T32	796906	0	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2535	0	0
T14	856929	2	0	0
T15	0	26	0	0
T16	0	21	0	0
T17	0	44	0	0
T18	0	27	0	0
T19	0	35	0	0
T20	0	8	0	0
T21	0	9	0	0
T22	0	37	0	0
T23	0	28	0	0
T24	460774	0	0	0
T25	570588	0	0	0
T26	479181	0	0	0
T27	171577	0	0	0
T28	482917	0	0	0
T29	120230	0	0	0
T30	536379	0	0	0
T31	310978	0	0	0
T32	796906	0	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2783	0	0
T14	856929	12	0	0
T15	0	19	0	0
T16	0	26	0	0
T17	0	29	0	0
T18	0	22	0	0
T19	0	37	0	0
T20	0	27	0	0
T21	0	24	0	0
T22	0	49	0	0
T23	0	21	0	0
T24	460774	0	0	0
T25	570588	0	0	0
T26	479181	0	0	0
T27	171577	0	0	0
T28	482917	0	0	0
T29	120230	0	0	0
T30	536379	0	0	0
T31	310978	0	0	0
T32	796906	0	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2699	0	0
T14	856929	12	0	0
T15	0	13	0	0
T16	0	26	0	0
T17	0	50	0	0
T18	0	13	0	0
T19	0	26	0	0
T20	0	24	0	0
T21	0	9	0	0
T22	0	49	0	0
T23	0	26	0	0
T24	460774	0	0	0
T25	570588	0	0	0
T26	479181	0	0	0
T27	171577	0	0	0
T28	482917	0	0	0
T29	120230	0	0	0
T30	536379	0	0	0
T31	310978	0	0	0
T32	796906	0	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2591	0	0
T14	856929	11	0	0
T15	0	1	0	0
T16	0	29	0	0
T17	0	40	0	0
T18	0	15	0	0
T19	0	27	0	0
T20	0	19	0	0
T21	0	6	0	0
T22	0	24	0	0
T23	0	16	0	0
T24	460774	0	0	0
T25	570588	0	0	0
T26	479181	0	0	0
T27	171577	0	0	0
T28	482917	0	0	0
T29	120230	0	0	0
T30	536379	0	0	0
T31	310978	0	0	0
T32	796906	0	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2829	0	0
T14	856929	16	0	0
T15	0	15	0	0
T16	0	18	0	0
T17	0	30	0	0
T18	0	20	0	0
T19	0	37	0	0
T20	0	15	0	0
T21	0	12	0	0
T22	0	43	0	0
T23	0	32	0	0
T24	460774	0	0	0
T25	570588	0	0	0
T26	479181	0	0	0
T27	171577	0	0	0
T28	482917	0	0	0
T29	120230	0	0	0
T30	536379	0	0	0
T31	310978	0	0	0
T32	796906	0	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2747	0	0
T14	856929	5	0	0
T15	0	4	0	0
T16	0	19	0	0
T17	0	36	0	0
T18	0	21	0	0
T19	0	37	0	0
T20	0	14	0	0
T21	0	29	0	0
T22	0	32	0	0
T23	0	13	0	0
T24	460774	0	0	0
T25	570588	0	0	0
T26	479181	0	0	0
T27	171577	0	0	0
T28	482917	0	0	0
T29	120230	0	0	0
T30	536379	0	0	0
T31	310978	0	0	0
T32	796906	0	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2512	0	0
T14	856929	1	0	0
T15	0	11	0	0
T16	0	13	0	0
T17	0	44	0	0
T18	0	15	0	0
T19	0	21	0	0
T20	0	15	0	0
T21	0	28	0	0
T22	0	33	0	0
T23	0	19	0	0
T24	460774	0	0	0
T25	570588	0	0	0
T26	479181	0	0	0
T27	171577	0	0	0
T28	482917	0	0	0
T29	120230	0	0	0
T30	536379	0	0	0
T31	310978	0	0	0
T32	796906	0	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2855	0	0
T14	856929	7	0	0
T16	0	8	0	0
T17	0	19	0	0
T18	0	15	0	0
T19	0	44	0	0
T20	0	8	0	0
T21	0	11	0	0
T22	0	49	0	0
T23	0	9	0	0
T24	460774	0	0	0
T25	570588	0	0	0
T26	479181	0	0	0
T27	171577	0	0	0
T28	482917	0	0	0
T29	120230	0	0	0
T30	536379	0	0	0
T31	310978	0	0	0
T32	796906	0	0	0
T33	0	17	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2497	0	0
T14	856929	12	0	0
T15	0	11	0	0
T16	0	12	0	0
T17	0	33	0	0
T18	0	18	0	0
T19	0	42	0	0
T20	0	12	0	0
T21	0	19	0	0
T22	0	57	0	0
T23	0	18	0	0
T24	460774	0	0	0
T25	570588	0	0	0
T26	479181	0	0	0
T27	171577	0	0	0
T28	482917	0	0	0
T29	120230	0	0	0
T30	536379	0	0	0
T31	310978	0	0	0
T32	796906	0	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2521	0	0
T14	856929	17	0	0
T15	0	5	0	0
T16	0	28	0	0
T17	0	46	0	0
T18	0	20	0	0
T19	0	52	0	0
T20	0	20	0	0
T21	0	7	0	0
T22	0	35	0	0
T23	0	12	0	0
T24	460774	0	0	0
T25	570588	0	0	0
T26	479181	0	0	0
T27	171577	0	0	0
T28	482917	0	0	0
T29	120230	0	0	0
T30	536379	0	0	0
T31	310978	0	0	0
T32	796906	0	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2337	0	0
T14	856929	3	0	0
T15	0	4	0	0
T16	0	33	0	0
T17	0	24	0	0
T18	0	16	0	0
T19	0	29	0	0
T20	0	15	0	0
T21	0	18	0	0
T22	0	32	0	0
T23	0	12	0	0
T24	460774	0	0	0
T25	570588	0	0	0
T26	479181	0	0	0
T27	171577	0	0	0
T28	482917	0	0	0
T29	120230	0	0	0
T30	536379	0	0	0
T31	310978	0	0	0
T32	796906	0	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1920	0	0
T14	856929	14	0	0
T15	0	4	0	0
T16	0	12	0	0
T17	0	40	0	0
T18	0	16	0	0
T19	0	48	0	0
T20	0	9	0	0
T21	0	19	0	0
T22	0	28	0	0
T23	0	13	0	0
T24	460774	0	0	0
T25	570588	0	0	0
T26	479181	0	0	0
T27	171577	0	0	0
T28	482917	0	0	0
T29	120230	0	0	0
T30	536379	0	0	0
T31	310978	0	0	0
T32	796906	0	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1660	0	0
T14	856929	9	0	0
T15	0	13	0	0
T16	0	24	0	0
T17	0	45	0	0
T18	0	20	0	0
T19	0	23	0	0
T20	0	18	0	0
T21	0	26	0	0
T22	0	46	0	0
T23	0	16	0	0
T24	460774	0	0	0
T25	570588	0	0	0
T26	479181	0	0	0
T27	171577	0	0	0
T28	482917	0	0	0
T29	120230	0	0	0
T30	536379	0	0	0
T31	310978	0	0	0
T32	796906	0	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2552	0	0
T14	856929	6	0	0
T15	0	2	0	0
T16	0	23	0	0
T17	0	27	0	0
T18	0	18	0	0
T19	0	31	0	0
T20	0	20	0	0
T21	0	32	0	0
T22	0	18	0	0
T23	0	23	0	0
T24	460774	0	0	0
T25	570588	0	0	0
T26	479181	0	0	0
T27	171577	0	0	0
T28	482917	0	0	0
T29	120230	0	0	0
T30	536379	0	0	0
T31	310978	0	0	0
T32	796906	0	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1636	0	0
T14	856929	17	0	0
T15	0	4	0	0
T16	0	24	0	0
T17	0	39	0	0
T18	0	26	0	0
T19	0	41	0	0
T20	0	20	0	0
T21	0	38	0	0
T22	0	34	0	0
T23	0	17	0	0
T24	460774	0	0	0
T25	570588	0	0	0
T26	479181	0	0	0
T27	171577	0	0	0
T28	482917	0	0	0
T29	120230	0	0	0
T30	536379	0	0	0
T31	310978	0	0	0
T32	796906	0	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2241	0	0
T14	856929	14	0	0
T15	0	15	0	0
T16	0	24	0	0
T17	0	33	0	0
T18	0	19	0	0
T19	0	45	0	0
T20	0	29	0	0
T21	0	22	0	0
T22	0	24	0	0
T23	0	6	0	0
T24	460774	0	0	0
T25	570588	0	0	0
T26	479181	0	0	0
T27	171577	0	0	0
T28	482917	0	0	0
T29	120230	0	0	0
T30	536379	0	0	0
T31	310978	0	0	0
T32	796906	0	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1521	0	0
T14	856929	8	0	0
T15	0	2	0	0
T16	0	22	0	0
T17	0	41	0	0
T18	0	10	0	0
T19	0	30	0	0
T20	0	10	0	0
T21	0	32	0	0
T22	0	22	0	0
T23	0	11	0	0
T24	460774	0	0	0
T25	570588	0	0	0
T26	479181	0	0	0
T27	171577	0	0	0
T28	482917	0	0	0
T29	120230	0	0	0
T30	536379	0	0	0
T31	310978	0	0	0
T32	796906	0	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1873	0	0
T14	856929	11	0	0
T15	0	11	0	0
T16	0	32	0	0
T17	0	39	0	0
T18	0	18	0	0
T19	0	33	0	0
T20	0	8	0	0
T21	0	20	0	0
T22	0	52	0	0
T23	0	16	0	0
T24	460774	0	0	0
T25	570588	0	0	0
T26	479181	0	0	0
T27	171577	0	0	0
T28	482917	0	0	0
T29	120230	0	0	0
T30	536379	0	0	0
T31	310978	0	0	0
T32	796906	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2270	0	0
T14	856929	23	0	0
T16	0	33	0	0
T17	0	34	0	0
T18	0	27	0	0
T34	536599	12	0	0
T35	0	18	0	0
T36	0	24	0	0
T37	0	7	0	0
T38	0	12	0	0
T39	0	20	0	0
T40	163132	0	0	0
T41	152626	0	0	0
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