Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1214593	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1186494

1

T1

450

T4

3

T2

20

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2103708	1			T1	811		T4	1		T3	2561
values[0x0]	147971	1			T1	49		T4	5		T2	13
values[0x1]	149408	1			T1	37		T4	4		T2	18

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	973387	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1427700

1

T1

545

T4

4

T2

21

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	9886	1			T1	1		T3	5		T5	2
valid_sources[0x01]	11578	1			T1	7		T3	10		T5	23
valid_sources[0x02]	11310	1			T1	1		T3	16		T5	8
valid_sources[0x03]	6744	1			T3	19		T5	12		T7	8
valid_sources[0x04]	11132	1			T1	3		T3	7		T5	5
valid_sources[0x05]	6586	1			T1	2		T3	17		T5	2
valid_sources[0x06]	9576	1			T1	1		T3	5		T5	7
valid_sources[0x07]	15986	1			T1	8		T3	16		T5	7
valid_sources[0x08]	11090	1			T1	3		T3	15		T5	7
valid_sources[0x09]	13350	1			T1	8		T3	16		T5	8
valid_sources[0x0a]	6874	1			T1	5		T2	3		T3	11
valid_sources[0x0b]	7332	1			T1	4		T3	8		T5	4
valid_sources[0x0c]	7309	1			T1	7		T3	7		T5	13
valid_sources[0x0d]	7148	1			T1	3		T3	2		T5	4
valid_sources[0x0e]	12101	1			T1	3		T3	8		T5	13
valid_sources[0x0f]	14215	1			T1	3		T3	22		T5	2
valid_sources[0x10]	7133	1			T1	1		T4	1		T3	24
valid_sources[0x11]	11381	1			T1	7		T3	13		T5	16
valid_sources[0x12]	11524	1			T1	3		T3	13		T5	12
valid_sources[0x13]	6995	1			T1	4		T3	15		T5	4
valid_sources[0x14]	7580	1			T1	4		T2	1		T3	9
valid_sources[0x15]	8395	1			T1	7		T3	9		T5	916
valid_sources[0x16]	7986	1			T1	4		T3	7		T5	5
valid_sources[0x17]	11413	1			T1	2		T3	7		T5	5
valid_sources[0x18]	6590	1			T1	2		T3	6		T5	18
valid_sources[0x19]	6763	1			T1	2		T3	13		T5	3
valid_sources[0x1a]	6940	1			T1	3		T3	11		T5	2
valid_sources[0x1b]	6731	1			T1	3		T3	15		T5	5
valid_sources[0x1c]	6808	1			T1	1		T3	14		T5	8
valid_sources[0x1d]	9459	1			T3	8		T5	5		T6	1
valid_sources[0x1e]	7490	1			T1	2		T3	19		T5	15
valid_sources[0x1f]	6908	1			T1	5		T3	14		T5	9
valid_sources[0x20]	6653	1			T1	3		T3	5		T5	2
valid_sources[0x21]	8198	1			T1	3		T3	11		T5	7
valid_sources[0x22]	6903	1			T1	7		T3	5		T5	4
valid_sources[0x23]	7103	1			T1	5		T3	10		T5	2
valid_sources[0x24]	8124	1			T1	1		T3	8		T5	11
valid_sources[0x25]	13873	1			T1	5		T3	15		T5	4
valid_sources[0x26]	8764	1			T1	7		T3	18		T5	6
valid_sources[0x27]	12151	1			T1	2		T3	15		T5	4
valid_sources[0x28]	11451	1			T1	7		T3	18		T5	8
valid_sources[0x29]	6984	1			T1	6		T3	10		T5	12
valid_sources[0x2a]	11069	1			T1	6		T3	13		T5	6
valid_sources[0x2b]	7037	1			T1	1		T3	11		T5	4
valid_sources[0x2c]	7368	1			T1	4		T3	12		T5	10
valid_sources[0x2d]	8485	1			T1	5		T3	11		T5	3
valid_sources[0x2e]	12241	1			T1	2		T3	10		T5	5
valid_sources[0x2f]	11514	1			T1	3		T3	14		T5	13
valid_sources[0x30]	9188	1			T1	1		T3	19		T5	3
valid_sources[0x31]	9288	1			T1	4		T3	11		T5	5
valid_sources[0x32]	7214	1			T1	4		T3	6		T5	10
valid_sources[0x33]	8369	1			T1	3		T3	7		T5	2
valid_sources[0x34]	6870	1			T1	3		T3	5		T5	2
valid_sources[0x35]	8099	1			T1	1		T3	8		T5	5
valid_sources[0x36]	8506	1			T1	4		T3	12		T5	5
valid_sources[0x37]	6711	1			T1	3		T3	8		T5	10
valid_sources[0x38]	7125	1			T1	6		T3	25		T5	2
valid_sources[0x39]	15456	1			T1	3		T3	1		T5	3
valid_sources[0x3a]	16250	1			T1	7		T3	14		T5	2
valid_sources[0x3b]	7178	1			T1	5		T3	18		T5	2
valid_sources[0x3c]	15780	1			T1	3		T3	13		T5	5
valid_sources[0x3d]	6580	1			T1	3		T4	1		T3	5
valid_sources[0x3e]	8408	1			T1	6		T3	23		T5	2
valid_sources[0x3f]	6916	1			T1	5		T3	10		T5	3
valid_sources[0x40]	11107	1			T1	10		T3	10		T5	5
valid_sources[0x41]	11581	1			T1	3		T3	6		T5	9
valid_sources[0x42]	11465	1			T1	5		T3	14		T5	5
valid_sources[0x43]	11151	1			T1	2		T3	12		T5	8
valid_sources[0x44]	7730	1			T1	8		T3	14		T5	4
valid_sources[0x45]	6791	1			T1	3		T3	11		T5	5
valid_sources[0x46]	15150	1			T1	1		T3	5		T5	8
valid_sources[0x47]	7175	1			T1	1		T5	16		T7	7
valid_sources[0x48]	7244	1			T3	12		T5	16		T6	1
valid_sources[0x49]	6793	1			T1	1		T3	9		T5	8
valid_sources[0x4a]	6933	1			T1	4		T3	16		T5	17
valid_sources[0x4b]	23711	1			T1	3		T3	16		T5	10
valid_sources[0x4c]	11513	1			T1	8		T3	12		T5	5
valid_sources[0x4d]	9957	1			T1	1		T3	8		T5	3
valid_sources[0x4e]	7659	1			T1	6		T3	7		T5	3
valid_sources[0x4f]	7656	1			T1	2		T3	6		T5	4
valid_sources[0x50]	6852	1			T1	4		T3	11		T5	5
valid_sources[0x51]	6726	1			T1	2		T3	4		T5	10
valid_sources[0x52]	11893	1			T1	1		T3	15		T5	5
valid_sources[0x53]	13322	1			T1	2		T3	11		T5	14
valid_sources[0x54]	7191	1			T1	3		T3	15		T5	31
valid_sources[0x55]	6844	1			T1	1		T3	3		T5	10
valid_sources[0x56]	6982	1			T1	4		T3	14		T5	6
valid_sources[0x57]	11578	1			T1	2		T2	3		T3	11
valid_sources[0x58]	11609	1			T1	1		T3	6		T5	11
valid_sources[0x59]	15584	1			T1	4		T3	15		T5	4
valid_sources[0x5a]	8921	1			T1	1		T4	1		T3	7
valid_sources[0x5b]	7063	1			T1	7		T3	14		T5	6
valid_sources[0x5c]	10193	1			T1	4		T3	10		T5	12
valid_sources[0x5d]	6930	1			T1	4		T3	4		T5	5
valid_sources[0x5e]	7360	1			T1	7		T4	1		T3	15
valid_sources[0x5f]	7118	1			T3	7		T5	3		T7	9
valid_sources[0x60]	7986	1			T1	2		T2	2		T3	6
valid_sources[0x61]	9394	1			T3	10		T5	6		T7	6
valid_sources[0x62]	11252	1			T1	11		T3	7		T5	15
valid_sources[0x63]	9529	1			T1	4		T3	9		T5	3
valid_sources[0x64]	6911	1			T1	1		T3	5		T5	3
valid_sources[0x65]	6740	1			T1	6		T3	11		T5	12
valid_sources[0x66]	11120	1			T1	2		T3	9		T5	4
valid_sources[0x67]	11540	1			T1	5		T3	7		T5	15
valid_sources[0x68]	7221	1			T1	6		T3	7		T5	4
valid_sources[0x69]	6920	1			T1	2		T3	21		T5	6
valid_sources[0x6a]	11709	1			T1	3		T3	3		T5	7
valid_sources[0x6b]	11686	1			T1	2		T3	5		T5	7
valid_sources[0x6c]	10466	1			T1	2		T2	4		T3	11
valid_sources[0x6d]	6979	1			T1	5		T3	9		T5	11
valid_sources[0x6e]	6600	1			T1	2		T3	19		T5	7
valid_sources[0x6f]	8290	1			T3	6		T5	5		T6	1
valid_sources[0x70]	19604	1			T1	2		T3	25		T5	5
valid_sources[0x71]	7719	1			T1	4		T3	11		T5	13
valid_sources[0x72]	6706	1			T1	5		T3	20		T5	4
valid_sources[0x73]	7622	1			T3	12		T5	11		T6	1
valid_sources[0x74]	8136	1			T1	3		T3	8		T5	12
valid_sources[0x75]	7987	1			T1	2		T3	12		T5	2
valid_sources[0x76]	10051	1			T1	6		T3	10		T5	2
valid_sources[0x77]	7890	1			T1	2		T3	5		T5	7
valid_sources[0x78]	6862	1			T1	2		T3	13		T5	1
valid_sources[0x79]	15481	1			T1	4		T3	22		T5	5
valid_sources[0x7a]	7738	1			T1	3		T3	11		T5	22
valid_sources[0x7b]	6775	1			T1	5		T3	13		T5	4
valid_sources[0x7c]	9436	1			T1	5		T3	2		T5	2
valid_sources[0x7d]	7047	1			T1	3		T3	16		T5	7
valid_sources[0x7e]	6906	1			T1	2		T3	8		T5	11
valid_sources[0x7f]	32912	1			T1	2		T3	14		T5	4
valid_sources[0x80]	11459	1			T1	1		T3	8		T5	11

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1048340

1

T1

402

T3

1317

T5

1204

values[0x0]

all_enables

biggest_size

80282

1

T1

31

T4

2

T2

11

values[0x1]

all_enables

biggest_size

57872

1

T1

17

T4

1

T2

9