Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
88.89	88.89	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	88.89	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.89	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	5	40	88.89

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	4	12	75.00	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	31364	1			T1	5		T3	20		T5	22
auto[PWRUP]	131	1			T27	1		T38	1		T43	4
auto[ONEST_0]	78	1			T27	1		T38	2		T40	2
auto[ONEST_021]	19	1			T43	1		T40	1		T19	1
auto[ONEST_1]	88	1			T38	1		T43	2		T34	2
auto[ONEST_DONE]	6	1			T38	1		T77	1		T91	1
auto[LP_0]	126	1			T27	1		T43	3		T33	1
auto[LP_021]	31	1			T34	1		T39	2		T41	1
auto[LP_1]	141	1			T27	3		T38	1		T43	3
auto[LP_EVAL]	76	1			T9	1		T27	1		T43	2
auto[LP_SLP]	521	1			T27	2		T38	4		T43	11
auto[LP_PWRUP]	37	1			T39	1		T40	2		T209	1
auto[NP_0]	146	1			T38	3		T33	1		T39	3
auto[NP_021]	44	1			T27	1		T34	1		T17	1
auto[NP_1]	138	1			T27	1		T38	3		T43	2
auto[NP_EVAL]	35	1			T34	2		T74	1		T139	2

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

6

1

T71

1

T139

1

T210

1

min

30799

1

T1

5

T3

20

T5

22

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	30806	1			T1	5		T3	20		T5	22
pow[0x1]	9	1			T79	1		T156	1		T211	1
pow[0x2]	17	1			T34	1		T39	1		T74	2
pow[0x3]	29	1			T38	1		T39	1		T209	1
pow[0x4]	72	1			T38	1		T43	2		T39	3
pow[0x5]	167	1			T9	1		T27	1		T38	3
pow[0x6]	262	1			T27	2		T38	1		T43	3
pow[0x7]	540	1			T9	1		T27	3		T38	6

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

216

1

T9

1

T27

1

T38

4

min

30292

1

T1

5

T3

20

T5

22

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	4	12	75.00

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x2]	0	1	1
pow[0x3]	0	1	1
pow[0x7]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	30292	1			T1	5		T3	20		T5	22
pow[0x4]	1	1			T212	1		-	-		-	-
pow[0x5]	3	1			T27	2		T213	1		-	-
pow[0x6]	2	1			T91	1		T214	1		-	-
pow[0x8]	4	1			T215	1		T216	1		T211	1
pow[0x9]	7	1			T38	1		T74	1		T149	1
pow[0xa]	15	1			T27	1		T43	1		T34	1
pow[0xb]	42	1			T43	1		T34	1		T39	1
pow[0xc]	67	1			T34	2		T39	1		T40	2
pow[0xd]	172	1			T38	1		T34	1		T39	2
pow[0xe]	314	1			T27	3		T38	1		T43	6
pow[0xf]	588	1			T27	4		T38	4		T43	13