Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.56	95.56	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	95.56	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.56	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	2	43	95.56

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	1	15	93.75	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2252	1			T9	17		T27	22		T38	13
auto[PWRUP]	149	1			T27	1		T38	1		T43	3
auto[ONEST_0]	86	1			T38	1		T33	1		T34	2
auto[ONEST_021]	16	1			T19	1		T350	1		T351	1
auto[ONEST_1]	87	1			T27	1		T43	1		T34	2
auto[ONEST_DONE]	4	1			T43	1		T352	1		T323	1
auto[LP_0]	116	1			T38	1		T39	2		T209	1
auto[LP_021]	33	1			T38	1		T33	1		T39	2
auto[LP_1]	135	1			T9	1		T33	2		T34	3
auto[LP_EVAL]	74	1			T27	3		T38	1		T43	1
auto[LP_SLP]	550	1			T9	3		T27	6		T38	5
auto[LP_PWRUP]	21	1			T27	1		T40	1		T215	1
auto[NP_0]	219	1			T9	1		T27	1		T38	3
auto[NP_021]	53	1			T9	1		T34	1		T39	2
auto[NP_1]	251	1			T9	1		T27	3		T38	6
auto[NP_EVAL]	36	1			T9	2		T27	1		T43	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

6

1

T71

1

T74

1

T149

1

min

1916

1

T9

24

T27

20

T38

5

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1928	1			T9	24		T27	20		T38	6
pow[0x1]	10	1			T9	1		T33	1		T34	1
pow[0x2]	20	1			T27	1		T43	2		T34	1
pow[0x3]	39	1			T38	1		T209	1		T74	1
pow[0x4]	73	1			T9	1		T38	3		T43	3
pow[0x5]	124	1			T27	1		T38	1		T33	1
pow[0x6]	275	1			T27	5		T38	1		T43	4
pow[0x7]	540	1			T27	3		T38	4		T43	8

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

204

1

T9

1

T38

3

T43

4

min

1330

1

T9

20

T27

14

T38

3

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	1	15	93.75

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x6]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1334	1			T9	20		T27	14		T38	3
pow[0x1]	19	1			T9	4		T27	1		T18	1
pow[0x2]	23	1			T27	1		T36	3		T23	3
pow[0x3]	28	1			T17	1		T18	4		T19	1
pow[0x4]	63	1			T9	1		T33	2		T34	2
pow[0x5]	1	1			T22	1		-	-		-	-
pow[0x7]	5	1			T216	1		T353	1		T22	1
pow[0x8]	5	1			T354	1		T216	1		T91	1
pow[0x9]	9	1			T41	1		T71	1		T350	1
pow[0xa]	22	1			T38	1		T42	1		T20	1
pow[0xb]	33	1			T39	1		T40	1		T354	1
pow[0xc]	62	1			T27	2		T43	3		T33	1
pow[0xd]	154	1			T38	1		T43	3		T34	1
pow[0xe]	314	1			T27	1		T38	2		T43	5
pow[0xf]	586	1			T27	4		T38	8		T43	7