Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	96.00						96.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	24	96.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	24	96.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	0	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	1520	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	1674	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	1523	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	1649	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	1549	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	1588	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	1635	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	1530	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	1554	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	1627	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	1523	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	1594	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	1546	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	1655	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	1606	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	1565	0	0
adc_en_ctl_rd_A	2147483647	1462	0	0
adc_fsm_rst_rd_A	2147483647	1429	0	0
adc_intr_ctl_rd_A	2147483647	1958	0	0
adc_lp_sample_ctl_rd_A	2147483647	1248	0	0
adc_pd_ctl_rd_A	2147483647	1443	0	0
adc_sample_ctl_rd_A	2147483647	1278	0	0
adc_wakeup_ctl_rd_A	2147483647	1239	0	0
intr_enable_rd_A	2147483647	2208	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1520	0	0
T9	367007	33	0	0
T10	343418	0	0	0
T11	157908	0	0	0
T12	194321	0	0	0
T13	380058	0	0	0
T14	191588	0	0	0
T16	0	28	0	0
T17	0	7	0	0
T18	0	38	0	0
T19	0	20	0	0
T20	0	40	0	0
T21	0	19	0	0
T22	0	24	0	0
T23	0	35	0	0
T24	0	8	0	0
T25	124309	0	0	0
T26	507798	0	0	0
T27	424678	0	0	0
T28	123087	0	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1674	0	0
T9	367007	31	0	0
T10	343418	0	0	0
T11	157908	0	0	0
T12	194321	0	0	0
T13	380058	0	0	0
T14	191588	0	0	0
T16	0	35	0	0
T17	0	14	0	0
T18	0	49	0	0
T19	0	11	0	0
T20	0	30	0	0
T21	0	9	0	0
T22	0	11	0	0
T23	0	34	0	0
T24	0	18	0	0
T25	124309	0	0	0
T26	507798	0	0	0
T27	424678	0	0	0
T28	123087	0	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1523	0	0
T9	367007	36	0	0
T10	343418	0	0	0
T11	157908	0	0	0
T12	194321	0	0	0
T13	380058	0	0	0
T14	191588	0	0	0
T16	0	39	0	0
T17	0	24	0	0
T18	0	28	0	0
T19	0	21	0	0
T20	0	35	0	0
T21	0	10	0	0
T22	0	29	0	0
T23	0	28	0	0
T24	0	6	0	0
T25	124309	0	0	0
T26	507798	0	0	0
T27	424678	0	0	0
T28	123087	0	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1649	0	0
T9	367007	24	0	0
T10	343418	0	0	0
T11	157908	0	0	0
T12	194321	0	0	0
T13	380058	0	0	0
T14	191588	0	0	0
T16	0	22	0	0
T17	0	9	0	0
T18	0	50	0	0
T19	0	28	0	0
T20	0	36	0	0
T21	0	10	0	0
T22	0	17	0	0
T23	0	49	0	0
T24	0	11	0	0
T25	124309	0	0	0
T26	507798	0	0	0
T27	424678	0	0	0
T28	123087	0	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1549	0	0
T9	367007	24	0	0
T10	343418	0	0	0
T11	157908	0	0	0
T12	194321	0	0	0
T13	380058	0	0	0
T14	191588	0	0	0
T16	0	23	0	0
T17	0	11	0	0
T18	0	34	0	0
T19	0	26	0	0
T20	0	38	0	0
T21	0	11	0	0
T22	0	32	0	0
T23	0	54	0	0
T24	0	17	0	0
T25	124309	0	0	0
T26	507798	0	0	0
T27	424678	0	0	0
T28	123087	0	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1588	0	0
T9	367007	33	0	0
T10	343418	0	0	0
T11	157908	0	0	0
T12	194321	0	0	0
T13	380058	0	0	0
T14	191588	0	0	0
T16	0	34	0	0
T17	0	29	0	0
T18	0	51	0	0
T19	0	30	0	0
T20	0	24	0	0
T21	0	20	0	0
T22	0	25	0	0
T23	0	42	0	0
T24	0	28	0	0
T25	124309	0	0	0
T26	507798	0	0	0
T27	424678	0	0	0
T28	123087	0	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1635	0	0
T9	367007	38	0	0
T10	343418	0	0	0
T11	157908	0	0	0
T12	194321	0	0	0
T13	380058	0	0	0
T14	191588	0	0	0
T16	0	47	0	0
T17	0	13	0	0
T18	0	32	0	0
T19	0	10	0	0
T20	0	45	0	0
T21	0	10	0	0
T22	0	20	0	0
T23	0	46	0	0
T24	0	22	0	0
T25	124309	0	0	0
T26	507798	0	0	0
T27	424678	0	0	0
T28	123087	0	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1530	0	0
T9	367007	23	0	0
T10	343418	0	0	0
T11	157908	0	0	0
T12	194321	0	0	0
T13	380058	0	0	0
T14	191588	0	0	0
T16	0	36	0	0
T17	0	24	0	0
T18	0	40	0	0
T19	0	7	0	0
T20	0	40	0	0
T21	0	6	0	0
T22	0	32	0	0
T23	0	52	0	0
T24	0	21	0	0
T25	124309	0	0	0
T26	507798	0	0	0
T27	424678	0	0	0
T28	123087	0	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1554	0	0
T9	367007	17	0	0
T10	343418	0	0	0
T11	157908	0	0	0
T12	194321	0	0	0
T13	380058	0	0	0
T14	191588	0	0	0
T16	0	42	0	0
T17	0	19	0	0
T18	0	17	0	0
T19	0	24	0	0
T20	0	46	0	0
T21	0	11	0	0
T22	0	28	0	0
T23	0	29	0	0
T24	0	36	0	0
T25	124309	0	0	0
T26	507798	0	0	0
T27	424678	0	0	0
T28	123087	0	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1627	0	0
T9	367007	23	0	0
T10	343418	0	0	0
T11	157908	0	0	0
T12	194321	0	0	0
T13	380058	0	0	0
T14	191588	0	0	0
T16	0	57	0	0
T17	0	16	0	0
T18	0	26	0	0
T19	0	27	0	0
T20	0	35	0	0
T21	0	8	0	0
T22	0	30	0	0
T23	0	33	0	0
T24	0	10	0	0
T25	124309	0	0	0
T26	507798	0	0	0
T27	424678	0	0	0
T28	123087	0	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1523	0	0
T9	367007	19	0	0
T10	343418	0	0	0
T11	157908	0	0	0
T12	194321	0	0	0
T13	380058	0	0	0
T14	191588	0	0	0
T16	0	46	0	0
T17	0	23	0	0
T18	0	44	0	0
T19	0	4	0	0
T20	0	35	0	0
T21	0	19	0	0
T22	0	17	0	0
T23	0	50	0	0
T24	0	30	0	0
T25	124309	0	0	0
T26	507798	0	0	0
T27	424678	0	0	0
T28	123087	0	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1594	0	0
T9	367007	23	0	0
T10	343418	0	0	0
T11	157908	0	0	0
T12	194321	0	0	0
T13	380058	0	0	0
T14	191588	0	0	0
T16	0	46	0	0
T17	0	7	0	0
T18	0	15	0	0
T19	0	20	0	0
T20	0	30	0	0
T21	0	4	0	0
T22	0	4	0	0
T23	0	37	0	0
T24	0	13	0	0
T25	124309	0	0	0
T26	507798	0	0	0
T27	424678	0	0	0
T28	123087	0	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1546	0	0
T9	367007	38	0	0
T10	343418	0	0	0
T11	157908	0	0	0
T12	194321	0	0	0
T13	380058	0	0	0
T14	191588	0	0	0
T16	0	34	0	0
T17	0	21	0	0
T18	0	21	0	0
T19	0	27	0	0
T20	0	47	0	0
T21	0	19	0	0
T22	0	15	0	0
T23	0	32	0	0
T25	124309	0	0	0
T26	507798	0	0	0
T27	424678	0	0	0
T28	123087	0	0	0
T29	0	42	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1655	0	0
T9	367007	42	0	0
T10	343418	0	0	0
T11	157908	0	0	0
T12	194321	0	0	0
T13	380058	0	0	0
T14	191588	0	0	0
T16	0	29	0	0
T17	0	27	0	0
T18	0	31	0	0
T19	0	7	0	0
T20	0	40	0	0
T21	0	25	0	0
T22	0	31	0	0
T23	0	48	0	0
T24	0	19	0	0
T25	124309	0	0	0
T26	507798	0	0	0
T27	424678	0	0	0
T28	123087	0	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1606	0	0
T9	367007	25	0	0
T10	343418	0	0	0
T11	157908	0	0	0
T12	194321	0	0	0
T13	380058	0	0	0
T14	191588	0	0	0
T16	0	39	0	0
T17	0	22	0	0
T18	0	28	0	0
T19	0	17	0	0
T20	0	34	0	0
T21	0	16	0	0
T22	0	14	0	0
T23	0	40	0	0
T24	0	30	0	0
T25	124309	0	0	0
T26	507798	0	0	0
T27	424678	0	0	0
T28	123087	0	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1565	0	0
T9	367007	38	0	0
T10	343418	0	0	0
T11	157908	0	0	0
T12	194321	0	0	0
T13	380058	0	0	0
T14	191588	0	0	0
T16	0	38	0	0
T17	0	14	0	0
T18	0	43	0	0
T19	0	9	0	0
T20	0	43	0	0
T21	0	18	0	0
T22	0	11	0	0
T23	0	42	0	0
T24	0	26	0	0
T25	124309	0	0	0
T26	507798	0	0	0
T27	424678	0	0	0
T28	123087	0	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1462	0	0
T9	367007	53	0	0
T10	343418	0	0	0
T11	157908	0	0	0
T12	194321	0	0	0
T13	380058	0	0	0
T14	191588	0	0	0
T16	0	47	0	0
T17	0	22	0	0
T18	0	31	0	0
T19	0	18	0	0
T20	0	39	0	0
T21	0	14	0	0
T22	0	33	0	0
T23	0	37	0	0
T24	0	20	0	0
T25	124309	0	0	0
T26	507798	0	0	0
T27	424678	0	0	0
T28	123087	0	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1429	0	0
T9	367007	42	0	0
T10	343418	0	0	0
T11	157908	0	0	0
T12	194321	0	0	0
T13	380058	0	0	0
T14	191588	0	0	0
T16	0	42	0	0
T17	0	9	0	0
T18	0	29	0	0
T19	0	19	0	0
T20	0	41	0	0
T21	0	17	0	0
T22	0	11	0	0
T23	0	31	0	0
T24	0	27	0	0
T25	124309	0	0	0
T26	507798	0	0	0
T27	424678	0	0	0
T28	123087	0	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1958	0	0
T9	367007	32	0	0
T10	343418	0	0	0
T11	157908	0	0	0
T12	194321	0	0	0
T13	380058	0	0	0
T14	191588	0	0	0
T16	0	31	0	0
T17	0	15	0	0
T18	0	29	0	0
T19	0	12	0	0
T20	0	49	0	0
T21	0	16	0	0
T22	0	8	0	0
T23	0	42	0	0
T24	0	30	0	0
T25	124309	0	0	0
T26	507798	0	0	0
T27	424678	0	0	0
T28	123087	0	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1248	0	0
T9	367007	27	0	0
T10	343418	0	0	0
T11	157908	0	0	0
T12	194321	0	0	0
T13	380058	0	0	0
T14	191588	0	0	0
T16	0	30	0	0
T17	0	13	0	0
T18	0	32	0	0
T19	0	8	0	0
T20	0	26	0	0
T21	0	11	0	0
T22	0	22	0	0
T23	0	37	0	0
T24	0	16	0	0
T25	124309	0	0	0
T26	507798	0	0	0
T27	424678	0	0	0
T28	123087	0	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1443	0	0
T9	367007	21	0	0
T10	343418	0	0	0
T11	157908	0	0	0
T12	194321	0	0	0
T13	380058	0	0	0
T14	191588	0	0	0
T16	0	40	0	0
T17	0	14	0	0
T18	0	32	0	0
T19	0	21	0	0
T20	0	32	0	0
T21	0	12	0	0
T22	0	18	0	0
T23	0	32	0	0
T24	0	14	0	0
T25	124309	0	0	0
T26	507798	0	0	0
T27	424678	0	0	0
T28	123087	0	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1278	0	0
T9	367007	27	0	0
T10	343418	0	0	0
T11	157908	0	0	0
T12	194321	0	0	0
T13	380058	0	0	0
T14	191588	0	0	0
T16	0	40	0	0
T17	0	4	0	0
T18	0	32	0	0
T19	0	26	0	0
T20	0	38	0	0
T21	0	11	0	0
T22	0	32	0	0
T23	0	30	0	0
T24	0	9	0	0
T25	124309	0	0	0
T26	507798	0	0	0
T27	424678	0	0	0
T28	123087	0	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1239	0	0
T9	367007	41	0	0
T10	343418	0	0	0
T11	157908	0	0	0
T12	194321	0	0	0
T13	380058	0	0	0
T14	191588	0	0	0
T16	0	40	0	0
T17	0	16	0	0
T18	0	43	0	0
T19	0	10	0	0
T20	0	45	0	0
T21	0	19	0	0
T22	0	22	0	0
T23	0	32	0	0
T24	0	19	0	0
T25	124309	0	0	0
T26	507798	0	0	0
T27	424678	0	0	0
T28	123087	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2208	0	0
T9	367007	68	0	0
T10	343418	0	0	0
T11	157908	0	0	0
T12	194321	0	0	0
T13	380058	0	0	0
T14	191588	0	0	0
T16	0	30	0	0
T17	0	37	0	0
T18	0	30	0	0
T19	0	48	0	0
T20	0	41	0	0
T21	0	36	0	0
T25	124309	0	0	0
T26	507798	0	0	0
T27	424678	0	0	0
T28	123087	0	0	0
T30	0	21	0	0
T31	0	9	0	0
T32	0	16	0	0