Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1183221	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1152455

1

T1

934

T2

62

T3

6182

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2044249	1			T1	1673		T2	81		T3	11937
values[0x0]	145125	1			T1	93		T2	29		T3	361
values[0x1]	146302	1			T1	100		T2	34		T3	356

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	948511	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1387165

1

T1

1115

T2

75

T3

7428

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7884	1			T1	7		T2	1		T3	42
valid_sources[0x01]	7985	1			T1	2		T2	1		T3	86
valid_sources[0x02]	6646	1			T1	4		T3	42		T4	16
valid_sources[0x03]	8922	1			T1	4		T3	40		T4	9
valid_sources[0x04]	7710	1			T1	12		T3	50		T4	6
valid_sources[0x05]	6573	1			T1	20		T3	61		T4	26
valid_sources[0x06]	8226	1			T1	5		T2	1		T3	37
valid_sources[0x07]	6819	1			T1	7		T3	67		T4	10
valid_sources[0x08]	6620	1			T1	5		T3	34		T4	15
valid_sources[0x09]	13772	1			T1	9		T3	48		T4	17
valid_sources[0x0a]	8884	1			T1	6		T2	2		T3	91
valid_sources[0x0b]	11204	1			T1	7		T3	40		T4	14
valid_sources[0x0c]	6634	1			T1	2		T2	1		T3	78
valid_sources[0x0d]	7173	1			T1	9		T3	69		T4	54
valid_sources[0x0e]	6703	1			T1	18		T3	87		T4	3
valid_sources[0x0f]	10663	1			T1	11		T3	30		T7	1
valid_sources[0x10]	7255	1			T1	9		T2	1		T3	44
valid_sources[0x11]	9592	1			T1	14		T3	57		T4	28
valid_sources[0x12]	6690	1			T1	7		T3	51		T4	14
valid_sources[0x13]	8822	1			T1	6		T2	1		T3	33
valid_sources[0x14]	7257	1			T1	4		T2	1		T3	28
valid_sources[0x15]	11262	1			T1	5		T2	3		T3	47
valid_sources[0x16]	6868	1			T1	6		T3	39		T4	22
valid_sources[0x17]	10835	1			T1	9		T3	60		T4	20
valid_sources[0x18]	6760	1			T1	2		T3	43		T4	12
valid_sources[0x19]	6584	1			T1	3		T3	41		T4	9
valid_sources[0x1a]	6539	1			T1	19		T2	5		T3	19
valid_sources[0x1b]	6958	1			T1	12		T3	32		T4	31
valid_sources[0x1c]	11498	1			T1	8		T3	55		T4	2
valid_sources[0x1d]	6781	1			T1	6		T2	4		T3	66
valid_sources[0x1e]	6382	1			T3	44		T4	13		T6	15
valid_sources[0x1f]	6363	1			T1	9		T3	38		T6	1
valid_sources[0x20]	7642	1			T1	11		T3	41		T4	55
valid_sources[0x21]	16412	1			T1	6		T3	41		T4	5
valid_sources[0x22]	10885	1			T1	8		T3	48		T4	4
valid_sources[0x23]	7027	1			T1	6		T3	61		T4	4
valid_sources[0x24]	11145	1			T1	5		T2	1		T3	58
valid_sources[0x25]	7092	1			T1	16		T3	46		T4	35
valid_sources[0x26]	9644	1			T1	12		T2	1		T3	75
valid_sources[0x27]	7036	1			T1	4		T3	51		T4	18
valid_sources[0x28]	6889	1			T1	3		T3	27		T4	20
valid_sources[0x29]	9832	1			T1	1		T3	67		T4	37
valid_sources[0x2a]	7558	1			T1	5		T3	60		T4	41
valid_sources[0x2b]	6488	1			T1	7		T3	72		T4	1
valid_sources[0x2c]	6919	1			T1	6		T3	28		T4	21
valid_sources[0x2d]	6758	1			T1	8		T2	1		T3	43
valid_sources[0x2e]	10816	1			T1	3		T3	70		T4	23
valid_sources[0x2f]	6648	1			T1	16		T3	64		T4	15
valid_sources[0x30]	7314	1			T1	3		T3	47		T4	33
valid_sources[0x31]	8009	1			T1	5		T2	1		T3	47
valid_sources[0x32]	10914	1			T1	16		T3	32		T4	3
valid_sources[0x33]	10465	1			T1	2		T3	60		T4	35
valid_sources[0x34]	11676	1			T1	6		T3	33		T4	48
valid_sources[0x35]	9099	1			T1	3		T3	57		T4	27
valid_sources[0x36]	6430	1			T1	14		T3	68		T4	3
valid_sources[0x37]	7103	1			T1	10		T3	53		T4	54
valid_sources[0x38]	16343	1			T1	15		T2	1		T3	37
valid_sources[0x39]	13375	1			T1	6		T3	55		T4	22
valid_sources[0x3a]	7180	1			T1	4		T3	60		T4	27
valid_sources[0x3b]	9495	1			T1	4		T3	38		T4	8
valid_sources[0x3c]	14816	1			T1	4		T3	60		T4	5
valid_sources[0x3d]	10183	1			T1	7		T2	4		T3	38
valid_sources[0x3e]	7577	1			T1	3		T3	46		T4	1
valid_sources[0x3f]	7609	1			T1	8		T3	53		T4	8
valid_sources[0x40]	6724	1			T1	17		T3	64		T4	1
valid_sources[0x41]	9233	1			T1	9		T3	71		T4	14
valid_sources[0x42]	6827	1			T1	5		T3	41		T4	52
valid_sources[0x43]	6586	1			T1	2		T3	67		T4	4
valid_sources[0x44]	6723	1			T3	22		T4	1		T7	5
valid_sources[0x45]	6921	1			T1	4		T3	29		T6	10
valid_sources[0x46]	7104	1			T1	9		T3	42		T4	12
valid_sources[0x47]	11823	1			T1	6		T3	71		T4	16
valid_sources[0x48]	8557	1			T1	11		T2	1		T3	53
valid_sources[0x49]	6830	1			T1	10		T3	36		T4	15
valid_sources[0x4a]	6708	1			T1	3		T2	1		T3	64
valid_sources[0x4b]	13664	1			T1	3		T2	2		T3	35
valid_sources[0x4c]	6878	1			T1	10		T3	86		T4	31
valid_sources[0x4d]	9902	1			T1	8		T2	1		T3	52
valid_sources[0x4e]	9822	1			T1	9		T3	47		T4	73
valid_sources[0x4f]	7075	1			T1	9		T3	44		T4	6
valid_sources[0x50]	10154	1			T1	5		T3	45		T4	18
valid_sources[0x51]	10012	1			T1	12		T3	56		T4	17
valid_sources[0x52]	10540	1			T1	3		T3	97		T4	2
valid_sources[0x53]	6862	1			T1	7		T3	52		T4	1
valid_sources[0x54]	6553	1			T1	3		T3	62		T4	14
valid_sources[0x55]	10777	1			T2	2		T3	37		T4	4
valid_sources[0x56]	13747	1			T1	11		T3	25		T4	9
valid_sources[0x57]	15347	1			T1	7		T3	50		T4	3
valid_sources[0x58]	8108	1			T1	12		T3	48		T4	33
valid_sources[0x59]	11499	1			T1	2		T3	48		T4	42
valid_sources[0x5a]	8771	1			T1	12		T3	20		T4	1
valid_sources[0x5b]	7053	1			T1	2		T3	58		T4	1
valid_sources[0x5c]	6161	1			T1	9		T3	44		T4	23
valid_sources[0x5d]	6598	1			T1	6		T2	1		T3	48
valid_sources[0x5e]	7662	1			T1	2		T2	3		T3	46
valid_sources[0x5f]	11112	1			T1	4		T3	35		T4	5
valid_sources[0x60]	12112	1			T1	6		T3	60		T7	4
valid_sources[0x61]	6724	1			T1	8		T3	48		T4	9
valid_sources[0x62]	10822	1			T1	14		T3	48		T4	21
valid_sources[0x63]	17323	1			T1	11		T3	67		T4	29
valid_sources[0x64]	6894	1			T1	8		T3	38		T4	2
valid_sources[0x65]	6996	1			T1	6		T3	54		T4	10
valid_sources[0x66]	7037	1			T1	8		T2	1		T3	51
valid_sources[0x67]	6764	1			T1	5		T3	55		T4	12
valid_sources[0x68]	8465	1			T1	6		T2	4		T3	54
valid_sources[0x69]	7886	1			T1	7		T2	2		T3	42
valid_sources[0x6a]	6511	1			T1	6		T2	1		T3	63
valid_sources[0x6b]	6891	1			T1	9		T3	36		T4	9
valid_sources[0x6c]	6700	1			T1	4		T2	2		T3	56
valid_sources[0x6d]	7050	1			T1	21		T3	79		T4	3
valid_sources[0x6e]	20150	1			T1	11		T3	58		T4	16
valid_sources[0x6f]	7669	1			T1	8		T3	65		T4	69
valid_sources[0x70]	13290	1			T1	3		T2	1		T3	78
valid_sources[0x71]	6647	1			T1	4		T3	42		T6	23
valid_sources[0x72]	12207	1			T1	7		T3	35		T4	2
valid_sources[0x73]	7320	1			T1	12		T2	1		T3	26
valid_sources[0x74]	11132	1			T1	10		T3	55		T4	18
valid_sources[0x75]	7484	1			T1	4		T3	16		T4	15
valid_sources[0x76]	6536	1			T1	6		T3	48		T4	28
valid_sources[0x77]	7004	1			T1	5		T2	1		T3	56
valid_sources[0x78]	6941	1			T1	24		T3	49		T4	9
valid_sources[0x79]	6507	1			T1	6		T3	41		T4	18
valid_sources[0x7a]	7859	1			T1	6		T3	35		T7	5
valid_sources[0x7b]	9526	1			T1	5		T3	58		T4	21
valid_sources[0x7c]	10153	1			T1	4		T3	84		T4	29
valid_sources[0x7d]	9827	1			T1	6		T3	89		T4	1
valid_sources[0x7e]	11042	1			T1	7		T3	30		T4	10
valid_sources[0x7f]	11775	1			T1	13		T2	1		T3	26
valid_sources[0x80]	6501	1			T1	8		T3	47		T4	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1017922

1

T1

834

T2

43

T3

5916

values[0x0]

all_enables

biggest_size

78429

1

T1

60

T2

11

T3

165

values[0x1]

all_enables

biggest_size

56104

1

T1

40

T2

8

T3

101