Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.56	95.56	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	95.56	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.56	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	2	43	95.56

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	0	17	100.00	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	2	14	87.50	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	0	17	100.00

Automatically Generated Bins for fsm_state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	28794	1			T1	18		T3	23		T4	7
auto[PWRUP]	103	1			T7	1		T37	1		T13	1
auto[ONEST_0]	71	1			T7	1		T37	1		T12	2
auto[ONEST_021]	18	1			T7	1		T331	1		T242	1
auto[ONEST_1]	92	1			T37	3		T12	1		T49	2
auto[ONEST_DONE]	4	1			T42	1		T332	1		T333	1
auto[LP_0]	119	1			T7	1		T37	1		T12	2
auto[LP_021]	25	1			T7	1		T334	1		T331	1
auto[LP_1]	135	1			T7	1		T37	1		T49	1
auto[LP_EVAL]	90	1			T7	1		T37	1		T12	2
auto[LP_SLP]	511	1			T7	6		T37	6		T12	1
auto[LP_PWRUP]	32	1			T49	1		T50	1		T334	1
auto[NP_0]	129	1			T7	2		T37	2		T12	1
auto[NP_021]	37	1			T7	1		T12	1		T49	1
auto[NP_1]	169	1			T50	2		T334	1		T157	1
auto[NP_EVAL]	33	1			T7	1		T37	1		T49	2
auto[NP_DONE]	1	1			T146	1		-	-		-	-

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

10

1

T332

1

T146

1

T155

1

min

28283

1

T1

18

T3

23

T4

7

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	28289	1			T1	18		T3	23		T4	7
pow[0x1]	7	1			T242	1		T335	1		T336	1
pow[0x2]	16	1			T50	2		T52	1		T17	1
pow[0x3]	26	1			T223	2		T331	1		T19	2
pow[0x4]	79	1			T7	1		T12	1		T334	2
pow[0x5]	133	1			T7	2		T37	2		T12	2
pow[0x6]	245	1			T7	1		T37	3		T13	1
pow[0x7]	544	1			T7	6		T37	9		T12	7

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

197

1

T7

2

T37

5

T12

1

min

27795

1

T1

18

T3

23

T4

7

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	2	14	87.50

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x2]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	27796	1			T1	18		T3	23		T4	7
pow[0x3]	1	1			T332	1		-	-		-	-
pow[0x4]	2	1			T337	1		T338	1		-	-
pow[0x5]	1	1			T331	1		-	-		-	-
pow[0x6]	1	1			T339	1		-	-		-	-
pow[0x7]	4	1			T340	1		T341	1		T342	1
pow[0x8]	1	1			T343	1		-	-		-	-
pow[0x9]	9	1			T37	1		T242	1		T332	1
pow[0xa]	18	1			T223	1		T344	1		T337	1
pow[0xb]	44	1			T49	1		T50	3		T334	2
pow[0xc]	50	1			T12	1		T50	3		T223	1
pow[0xd]	147	1			T7	2		T37	4		T12	2
pow[0xe]	304	1			T7	2		T37	4		T12	3
pow[0xf]	614	1			T7	8		T37	8		T12	1