Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.56	95.56	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	95.56	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.56	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	2	43	95.56

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	1	15	93.75	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2307	1			T4	5		T7	16		T14	10
auto[PWRUP]	144	1			T7	1		T37	2		T13	1
auto[ONEST_0]	85	1			T7	2		T37	2		T12	3
auto[ONEST_021]	16	1			T52	1		T17	1		T242	3
auto[ONEST_1]	105	1			T37	1		T12	1		T13	1
auto[ONEST_DONE]	3	1			T345	1		T155	1		T346	1
auto[LP_0]	152	1			T37	4		T49	1		T50	1
auto[LP_021]	37	1			T37	1		T13	1		T157	1
auto[LP_1]	154	1			T37	5		T12	1		T49	1
auto[LP_EVAL]	70	1			T7	1		T37	1		T13	1
auto[LP_SLP]	528	1			T7	3		T37	8		T12	11
auto[LP_PWRUP]	23	1			T12	1		T50	1		T242	1
auto[NP_0]	236	1			T7	1		T37	4		T12	1
auto[NP_021]	46	1			T52	1		T223	2		T39	2
auto[NP_1]	231	1			T37	1		T12	3		T13	4
auto[NP_EVAL]	33	1			T334	1		T15	1		T38	2

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

13

1

T49

1

T52

1

T242

1

min

1940

1

T4

5

T7

3

T14

10

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1955	1			T4	5		T7	3		T14	10
pow[0x1]	12	1			T16	1		T41	1		T344	1
pow[0x2]	26	1			T12	1		T52	1		T15	1
pow[0x3]	25	1			T157	1		T223	1		T182	1
pow[0x4]	70	1			T12	2		T49	1		T334	1
pow[0x5]	135	1			T37	3		T49	2		T50	2
pow[0x6]	298	1			T7	3		T37	5		T12	4
pow[0x7]	563	1			T7	10		T37	5		T12	1

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

189

1

T7

1

T37

2

T12

2

min

1342

1

T4

5

T7

1

T14

10

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	1	15	93.75

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x5]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1350	1			T4	5		T7	1		T14	10
pow[0x1]	21	1			T16	1		T39	4		T41	1
pow[0x2]	20	1			T12	1		T13	4		T18	2
pow[0x3]	39	1			T12	2		T36	2		T38	1
pow[0x4]	66	1			T15	2		T38	3		T16	1
pow[0x6]	2	1			T182	1		T320	1		-	-
pow[0x7]	6	1			T347	1		T348	1		T349	1
pow[0x8]	3	1			T37	1		T341	1		T350	1
pow[0x9]	6	1			T223	1		T351	1		T352	1
pow[0xa]	15	1			T50	1		T223	2		T331	1
pow[0xb]	41	1			T37	1		T12	1		T50	2
pow[0xc]	84	1			T7	1		T37	1		T12	1
pow[0xd]	132	1			T49	1		T52	1		T157	3
pow[0xe]	323	1			T37	6		T12	1		T13	1
pow[0xf]	619	1			T7	11		T37	13		T12	7