Unified Coverage Report :: Module :: adc_ctrl_fsm_sva

Module : adc_ctrl_fsm_sva

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_sva_0.1/adc_ctrl_fsm_sva.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva	100.00						100.00

---

Module Instance : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.75	100.00	100.00		100.00	98.73	100.00	u_adc_ctrl_fsm

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_fsm_sva

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	11	11	100.00	11	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	11	11	100.00	11	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
FsmDebugOut_A	31506196	31426265	0	0
FsmStateHwReset_A	1143	1143	0	0
FsmStateSwReset_A	31506196	6506	0	0
LpSampleCntHwReset_A	1143	1143	0	0
LpSampleCntSwReset_A	31506196	6506	0	0
NpSampleCntHwReset_A	1143	1143	0	0
NpSampleCntSwReset_A	31506196	6506	0	0
PwrupTimerCntHwReset_A	1143	1143	0	0
PwrupTimerCntSwReset_A	31506196	6506	0	0
WakeupTimerCntHwReset_A	1143	1143	0	0
WakeupTimerCntSwReset_A	31506196	6506	0	0

FsmDebugOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31506196	31426265	0	0
T1	65365	65310	0	0
T2	1166	1115	0	0
T3	96867	96779	0	0
T4	43465	43001	0	0
T5	66965	66902	0	0
T6	41877	41786	0	0
T7	53	1	0	0
T8	97085	97029	0	0
T9	551	499	0	0
T14	93	1	0	0

FsmStateHwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1143	1143	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	6	6	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T14	1	1	0	0

FsmStateSwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31506196	6506	0	0
T1	65365	18	0	0
T2	1166	0	0	0
T3	96867	23	0	0
T4	43465	7	0	0
T5	66965	13	0	0
T6	41877	6	0	0
T7	53	0	0	0
T8	97085	23	0	0
T9	551	0	0	0
T10	0	26	0	0
T11	0	15	0	0
T14	93	0	0	0
T26	0	25	0	0
T27	0	18	0	0

LpSampleCntHwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1143	1143	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	6	6	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T14	1	1	0	0

LpSampleCntSwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31506196	6506	0	0
T1	65365	18	0	0
T2	1166	0	0	0
T3	96867	23	0	0
T4	43465	7	0	0
T5	66965	13	0	0
T6	41877	6	0	0
T7	53	0	0	0
T8	97085	23	0	0
T9	551	0	0	0
T10	0	26	0	0
T11	0	15	0	0
T14	93	0	0	0
T26	0	25	0	0
T27	0	18	0	0

NpSampleCntHwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1143	1143	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	6	6	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T14	1	1	0	0

NpSampleCntSwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31506196	6506	0	0
T1	65365	18	0	0
T2	1166	0	0	0
T3	96867	23	0	0
T4	43465	7	0	0
T5	66965	13	0	0
T6	41877	6	0	0
T7	53	0	0	0
T8	97085	23	0	0
T9	551	0	0	0
T10	0	26	0	0
T11	0	15	0	0
T14	93	0	0	0
T26	0	25	0	0
T27	0	18	0	0

PwrupTimerCntHwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1143	1143	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	6	6	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T14	1	1	0	0

PwrupTimerCntSwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31506196	6506	0	0
T1	65365	18	0	0
T2	1166	0	0	0
T3	96867	23	0	0
T4	43465	7	0	0
T5	66965	13	0	0
T6	41877	6	0	0
T7	53	0	0	0
T8	97085	23	0	0
T9	551	0	0	0
T10	0	26	0	0
T11	0	15	0	0
T14	93	0	0	0
T26	0	25	0	0
T27	0	18	0	0

WakeupTimerCntHwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1143	1143	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	6	6	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T14	1	1	0	0

WakeupTimerCntSwReset_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	31506196	6506	0	0
T1	65365	18	0	0
T2	1166	0	0	0
T3	96867	23	0	0
T4	43465	7	0	0
T5	66965	13	0	0
T6	41877	6	0	0
T7	53	0	0	0
T8	97085	23	0	0
T9	551	0	0	0
T10	0	26	0	0
T11	0	15	0	0
T14	93	0	0	0
T26	0	25	0	0
T27	0	18	0	0